Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/mediatek: dp: Add sdp path reset

When using type-c to type-c to connect to the monitor,
the sound plays normally. If you unplug the type-c and
connect the type-c to hdmi dongle to the monitor, there will be noise.

By capturing the audio data, it is found that
the data position is messy, and there is no error in the data.

Through experiments, it can be restored by resetting the SDP path
when unplugging it.

Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20241128023733.16294-1-liankun.yang@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

authored by

Liankun Yang and committed by
Chun-Kuang Hu
4f0d4a82 40384c84

+16
+15
drivers/gpu/drm/mediatek/mtk_dp.c
··· 1135 1135 0, DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0); 1136 1136 } 1137 1137 1138 + static void mtk_dp_sdp_path_reset(struct mtk_dp *mtk_dp) 1139 + { 1140 + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004, 1141 + SDP_RESET_SW_DP_ENC0_P0, 1142 + SDP_RESET_SW_DP_ENC0_P0); 1143 + 1144 + /* Wait for sdp path reset to complete */ 1145 + usleep_range(1000, 5000); 1146 + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004, 1147 + 0, SDP_RESET_SW_DP_ENC0_P0); 1148 + } 1149 + 1138 1150 static void mtk_dp_set_lanes(struct mtk_dp *mtk_dp, int lanes) 1139 1151 { 1140 1152 mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35F0, ··· 2408 2396 mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, 2409 2397 DP_PWR_STATE_BANDGAP_TPLL, 2410 2398 DP_PWR_STATE_MASK); 2399 + 2400 + /* SDP path reset sw*/ 2401 + mtk_dp_sdp_path_reset(mtk_dp); 2411 2402 2412 2403 /* Ensure the sink is muted */ 2413 2404 msleep(20);
+1
drivers/gpu/drm/mediatek/mtk_dp_reg.h
··· 86 86 #define MTK_DP_ENC0_P0_3004 0x3004 87 87 #define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK BIT(8) 88 88 #define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0 BIT(9) 89 + #define SDP_RESET_SW_DP_ENC0_P0 BIT(13) 89 90 #define MTK_DP_ENC0_P0_3010 0x3010 90 91 #define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0) 91 92 #define MTK_DP_ENC0_P0_3014 0x3014