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drm/i915/icl: Introduce new macros to get combophy registers

combo-phy register instances are at same offset from base for each
combo-phy port, i.e.

Port A base offset: 0x16200
Port B base offset: 0x6C000

All the other addresses for both ports can be derived by calculating
offset to these base addresses.

PORT_CL_DW_OFFSET 0x0
PORT_CL_DW<x> 0 + x * 4

PORT_COMP_OFFSET 0x100
PORT_COMP_DW<x> 0x100 + x * 4

PORT_PCS_AUX_OFFSET 0x300
PORT_PCS_GRP_OFFSET 0x600
PORT_PCS_LN<y>_OFFSET 0x800 + y * 0x100

PORT_TX_AUX_OFFSET 0x380
PORT_TX_GRP_OFFSET 0x680
PORT_TX_LN<y>_OFFSET 0x880 + y * 0x100

And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.

Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>.

v2: make port, dw and ln arguments follow the order in
register's name

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181016023517.8576-1-lucas.demarchi@intel.com

authored by

Lucas De Marchi and committed by
Rodrigo Vivi 4e53840f d72e84cc

+59 -104
+59 -104
drivers/gpu/drm/i915/i915_reg.h
··· 1658 1658 /* 1659 1659 * CNL/ICL Port/COMBO-PHY Registers 1660 1660 */ 1661 + #define _ICL_COMBOPHY_A 0x162000 1662 + #define _ICL_COMBOPHY_B 0x6C000 1663 + #define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \ 1664 + _ICL_COMBOPHY_B) 1665 + 1661 1666 /* CNL/ICL Port CL_DW registers */ 1662 - #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) 1663 - #define _ICL_PORT_CL_DW5_A 0x162014 1664 - #define _ICL_PORT_CL_DW5_B 0x6C014 1665 - #define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \ 1666 - _ICL_PORT_CL_DW5_B) 1667 + #define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \ 1668 + 4 * (dw)) 1669 + 1670 + #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) 1671 + #define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port)) 1667 1672 #define CL_POWER_DOWN_ENABLE (1 << 4) 1668 1673 #define SUS_CLOCK_CONFIG (3 << 0) 1669 1674 1670 - #define _CNL_PORT_CL_DW10_A 0x162028 1671 - #define _ICL_PORT_CL_DW10_B 0x6c028 1672 - #define ICL_PORT_CL_DW10(port) _MMIO_PORT(port, \ 1673 - _CNL_PORT_CL_DW10_A, \ 1674 - _ICL_PORT_CL_DW10_B) 1675 + #define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port)) 1675 1676 #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25) 1676 1677 #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25 1677 1678 #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24) ··· 1688 1687 #define PWR_DOWN_LN_MASK (0xf << 4) 1689 1688 #define PWR_DOWN_LN_SHIFT 4 1690 1689 1691 - #define _ICL_PORT_CL_DW12_A 0x162030 1692 - #define _ICL_PORT_CL_DW12_B 0x6C030 1690 + #define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port)) 1693 1691 #define ICL_LANE_ENABLE_AUX (1 << 0) 1694 - #define ICL_PORT_CL_DW12(port) _MMIO_PORT((port), \ 1695 - _ICL_PORT_CL_DW12_A, \ 1696 - _ICL_PORT_CL_DW12_B) 1697 1692 1698 1693 /* CNL/ICL Port COMP_DW registers */ 1694 + #define _ICL_PORT_COMP 0x100 1695 + #define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \ 1696 + _ICL_PORT_COMP + 4 * (dw)) 1697 + 1699 1698 #define CNL_PORT_COMP_DW0 _MMIO(0x162100) 1700 - #define _ICL_PORT_COMP_DW0_A 0x162100 1701 - #define _ICL_PORT_COMP_DW0_B 0x6C100 1702 - #define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \ 1703 - _ICL_PORT_COMP_DW0_B) 1699 + #define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port)) 1704 1700 #define COMP_INIT (1 << 31) 1705 1701 1706 1702 #define CNL_PORT_COMP_DW1 _MMIO(0x162104) 1707 - #define _ICL_PORT_COMP_DW1_A 0x162104 1708 - #define _ICL_PORT_COMP_DW1_B 0x6C104 1709 - #define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \ 1710 - _ICL_PORT_COMP_DW1_B) 1703 + #define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port)) 1704 + 1711 1705 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) 1712 - #define _ICL_PORT_COMP_DW3_A 0x16210C 1713 - #define _ICL_PORT_COMP_DW3_B 0x6C10C 1714 - #define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \ 1715 - _ICL_PORT_COMP_DW3_B) 1706 + #define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port)) 1716 1707 #define PROCESS_INFO_DOT_0 (0 << 26) 1717 1708 #define PROCESS_INFO_DOT_1 (1 << 26) 1718 1709 #define PROCESS_INFO_DOT_4 (2 << 26) ··· 1717 1724 #define VOLTAGE_INFO_SHIFT 24 1718 1725 1719 1726 #define CNL_PORT_COMP_DW9 _MMIO(0x162124) 1720 - #define _ICL_PORT_COMP_DW9_A 0x162124 1721 - #define _ICL_PORT_COMP_DW9_B 0x6C124 1722 - #define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \ 1723 - _ICL_PORT_COMP_DW9_B) 1727 + #define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port)) 1724 1728 1725 1729 #define CNL_PORT_COMP_DW10 _MMIO(0x162128) 1726 - #define _ICL_PORT_COMP_DW10_A 0x162128 1727 - #define _ICL_PORT_COMP_DW10_B 0x6C128 1728 - #define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \ 1729 - _ICL_PORT_COMP_DW10_A, \ 1730 - _ICL_PORT_COMP_DW10_B) 1730 + #define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port)) 1731 1731 1732 1732 /* CNL/ICL Port PCS registers */ 1733 1733 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 ··· 1740 1754 _CNL_PORT_PCS_DW1_GRP_D, \ 1741 1755 _CNL_PORT_PCS_DW1_GRP_AE, \ 1742 1756 _CNL_PORT_PCS_DW1_GRP_F)) 1743 - 1744 1757 #define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \ 1745 1758 _CNL_PORT_PCS_DW1_LN0_AE, \ 1746 1759 _CNL_PORT_PCS_DW1_LN0_B, \ ··· 1748 1763 _CNL_PORT_PCS_DW1_LN0_AE, \ 1749 1764 _CNL_PORT_PCS_DW1_LN0_F)) 1750 1765 1751 - #define _ICL_PORT_PCS_DW1_GRP_A 0x162604 1752 - #define _ICL_PORT_PCS_DW1_GRP_B 0x6C604 1753 - #define _ICL_PORT_PCS_DW1_LN0_A 0x162804 1754 - #define _ICL_PORT_PCS_DW1_LN0_B 0x6C804 1755 - #define _ICL_PORT_PCS_DW1_AUX_A 0x162304 1756 - #define _ICL_PORT_PCS_DW1_AUX_B 0x6c304 1757 - #define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\ 1758 - _ICL_PORT_PCS_DW1_GRP_A, \ 1759 - _ICL_PORT_PCS_DW1_GRP_B) 1760 - #define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \ 1761 - _ICL_PORT_PCS_DW1_LN0_A, \ 1762 - _ICL_PORT_PCS_DW1_LN0_B) 1763 - #define ICL_PORT_PCS_DW1_AUX(port) _MMIO_PORT(port, \ 1764 - _ICL_PORT_PCS_DW1_AUX_A, \ 1765 - _ICL_PORT_PCS_DW1_AUX_B) 1766 + #define _ICL_PORT_PCS_AUX 0x300 1767 + #define _ICL_PORT_PCS_GRP 0x600 1768 + #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) 1769 + #define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ 1770 + _ICL_PORT_PCS_AUX + 4 * (dw)) 1771 + #define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ 1772 + _ICL_PORT_PCS_GRP + 4 * (dw)) 1773 + #define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ 1774 + _ICL_PORT_PCS_LN(ln) + 4 * (dw)) 1775 + #define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port)) 1776 + #define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port)) 1777 + #define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port)) 1766 1778 #define COMMON_KEEPER_EN (1 << 26) 1767 1779 1768 1780 /* CNL/ICL Port TX registers */ ··· 1790 1808 _CNL_PORT_TX_F_LN0_OFFSET) + \ 1791 1809 4 * (dw)) 1792 1810 1793 - #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2)) 1794 - #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2)) 1795 - #define _ICL_PORT_TX_DW2_GRP_A 0x162688 1796 - #define _ICL_PORT_TX_DW2_GRP_B 0x6C688 1797 - #define _ICL_PORT_TX_DW2_LN0_A 0x162888 1798 - #define _ICL_PORT_TX_DW2_LN0_B 0x6C888 1799 - #define _ICL_PORT_TX_DW2_AUX_A 0x162388 1800 - #define _ICL_PORT_TX_DW2_AUX_B 0x6c388 1801 - #define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \ 1802 - _ICL_PORT_TX_DW2_GRP_A, \ 1803 - _ICL_PORT_TX_DW2_GRP_B) 1804 - #define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \ 1805 - _ICL_PORT_TX_DW2_LN0_A, \ 1806 - _ICL_PORT_TX_DW2_LN0_B) 1807 - #define ICL_PORT_TX_DW2_AUX(port) _MMIO_PORT(port, \ 1808 - _ICL_PORT_TX_DW2_AUX_A, \ 1809 - _ICL_PORT_TX_DW2_AUX_B) 1811 + #define _ICL_PORT_TX_AUX 0x380 1812 + #define _ICL_PORT_TX_GRP 0x680 1813 + #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) 1814 + 1815 + #define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ 1816 + _ICL_PORT_TX_AUX + 4 * (dw)) 1817 + #define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ 1818 + _ICL_PORT_TX_GRP + 4 * (dw)) 1819 + #define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ 1820 + _ICL_PORT_TX_LN(ln) + 4 * (dw)) 1821 + 1822 + #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port)) 1823 + #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port)) 1824 + #define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port)) 1825 + #define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port)) 1826 + #define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port)) 1810 1827 #define SWING_SEL_UPPER(x) (((x) >> 3) << 15) 1811 1828 #define SWING_SEL_UPPER_MASK (1 << 15) 1812 1829 #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) ··· 1822 1841 #define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \ 1823 1842 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ 1824 1843 _CNL_PORT_TX_DW4_LN0_AE))) 1825 - #define _ICL_PORT_TX_DW4_GRP_A 0x162690 1826 - #define _ICL_PORT_TX_DW4_GRP_B 0x6C690 1827 - #define _ICL_PORT_TX_DW4_LN0_A 0x162890 1828 - #define _ICL_PORT_TX_DW4_LN1_A 0x162990 1829 - #define _ICL_PORT_TX_DW4_LN0_B 0x6C890 1830 - #define _ICL_PORT_TX_DW4_AUX_A 0x162390 1831 - #define _ICL_PORT_TX_DW4_AUX_B 0x6c390 1832 - #define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \ 1833 - _ICL_PORT_TX_DW4_GRP_A, \ 1834 - _ICL_PORT_TX_DW4_GRP_B) 1835 - #define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \ 1836 - _ICL_PORT_TX_DW4_LN0_A, \ 1837 - _ICL_PORT_TX_DW4_LN0_B) + \ 1838 - ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \ 1839 - _ICL_PORT_TX_DW4_LN0_A))) 1840 - #define ICL_PORT_TX_DW4_AUX(port) _MMIO_PORT(port, \ 1841 - _ICL_PORT_TX_DW4_AUX_A, \ 1842 - _ICL_PORT_TX_DW4_AUX_B) 1844 + #define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port)) 1845 + #define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port)) 1846 + #define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port)) 1847 + #define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port)) 1843 1848 #define LOADGEN_SELECT (1 << 31) 1844 1849 #define POST_CURSOR_1(x) ((x) << 12) 1845 1850 #define POST_CURSOR_1_MASK (0x3F << 12) ··· 1834 1867 #define CURSOR_COEFF(x) ((x) << 0) 1835 1868 #define CURSOR_COEFF_MASK (0x3F << 0) 1836 1869 1837 - #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5)) 1838 - #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5)) 1839 - #define _ICL_PORT_TX_DW5_GRP_A 0x162694 1840 - #define _ICL_PORT_TX_DW5_GRP_B 0x6C694 1841 - #define _ICL_PORT_TX_DW5_LN0_A 0x162894 1842 - #define _ICL_PORT_TX_DW5_LN0_B 0x6C894 1843 - #define _ICL_PORT_TX_DW5_AUX_A 0x162394 1844 - #define _ICL_PORT_TX_DW5_AUX_B 0x6c394 1845 - #define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \ 1846 - _ICL_PORT_TX_DW5_GRP_A, \ 1847 - _ICL_PORT_TX_DW5_GRP_B) 1848 - #define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \ 1849 - _ICL_PORT_TX_DW5_LN0_A, \ 1850 - _ICL_PORT_TX_DW5_LN0_B) 1851 - #define ICL_PORT_TX_DW5_AUX(port) _MMIO_PORT(port, \ 1852 - _ICL_PORT_TX_DW5_AUX_A, \ 1853 - _ICL_PORT_TX_DW5_AUX_B) 1870 + #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port)) 1871 + #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port)) 1872 + #define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port)) 1873 + #define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port)) 1874 + #define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port)) 1854 1875 #define TX_TRAINING_EN (1 << 31) 1855 1876 #define TAP2_DISABLE (1 << 30) 1856 1877 #define TAP3_DISABLE (1 << 29)