Merge tag 'renesas-dts-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

+172

Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller 8 + 9 + maintainers: 10 + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 11 + 12 + description: 13 + The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller. 14 + Pin multiplexing and GPIO configuration are performed on a per-pin basis. 15 + Each port supports up to 8 pins, each configurable for either GPIO (port mode) 16 + or alternate function mode. Each pin supports function mode values ranging from 17 + 0x0 to 0x2A, allowing selection from up to 43 different functions. 18 + 19 + properties: 20 + compatible: 21 + enum: 22 + - renesas,r9a09g077-pinctrl # RZ/T2H 23 + - renesas,r9a09g087-pinctrl # RZ/N2H 24 + 25 + reg: 26 + minItems: 1 27 + items: 28 + - description: Non-safety I/O Port base 29 + - description: Safety I/O Port safety region base 30 + - description: Safety I/O Port Non-safety region base 31 + 32 + reg-names: 33 + minItems: 1 34 + items: 35 + - const: nsr 36 + - const: srs 37 + - const: srn 38 + 39 + gpio-controller: true 40 + 41 + '#gpio-cells': 42 + const: 2 43 + description: 44 + The first cell contains the global GPIO port index, constructed using the 45 + RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> 46 + (e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer 47 + flag. Use the macros defined in include/dt-bindings/gpio/gpio.h. 48 + 49 + gpio-ranges: 50 + maxItems: 1 51 + 52 + clocks: 53 + maxItems: 1 54 + 55 + power-domains: 56 + maxItems: 1 57 + 58 + definitions: 59 + renesas-rzt2h-n2h-pins-node: 60 + type: object 61 + allOf: 62 + - $ref: pincfg-node.yaml# 63 + - $ref: pinmux-node.yaml# 64 + properties: 65 + pinmux: 66 + description: 67 + Values are constructed from I/O port number, pin number, and 68 + alternate function configuration number using the RZT2H_PORT_PINMUX() 69 + helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>. 70 + pins: true 71 + phandle: true 72 + input: true 73 + input-enable: true 74 + output-enable: true 75 + oneOf: 76 + - required: [pinmux] 77 + - required: [pins] 78 + additionalProperties: false 79 + 80 + patternProperties: 81 + # Grouping nodes: allow multiple "-pins" subnodes within a "-group" 82 + '.*-group$': 83 + type: object 84 + description: 85 + Pin controller client devices can organize pin configuration entries into 86 + grouping nodes ending in "-group". These group nodes may contain multiple 87 + child nodes each ending in "-pins" to configure distinct sets of pins. 88 + additionalProperties: false 89 + patternProperties: 90 + '-pins$': 91 + $ref: '#/definitions/renesas-rzt2h-n2h-pins-node' 92 + 93 + # Standalone "-pins" nodes under client devices or groups 94 + '-pins$': 95 + $ref: '#/definitions/renesas-rzt2h-n2h-pins-node' 96 + 97 + '-hog$': 98 + type: object 99 + description: GPIO hog node 100 + properties: 101 + gpio-hog: true 102 + gpios: true 103 + input: true 104 + output-high: true 105 + output-low: true 106 + line-name: true 107 + required: 108 + - gpio-hog 109 + - gpios 110 + additionalProperties: false 111 + 112 + allOf: 113 + - $ref: pinctrl.yaml# 114 + 115 + required: 116 + - compatible 117 + - reg 118 + - reg-names 119 + - gpio-controller 120 + - '#gpio-cells' 121 + - gpio-ranges 122 + - clocks 123 + - power-domains 124 + 125 + unevaluatedProperties: false 126 + 127 + examples: 128 + - | 129 + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> 130 + #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> 131 + 132 + pinctrl@802c0000 { 133 + compatible = "renesas,r9a09g077-pinctrl"; 134 + reg = <0x802c0000 0x2000>, 135 + <0x812c0000 0x2000>, 136 + <0x802b0000 0x2000>; 137 + reg-names = "nsr", "srs", "srn"; 138 + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 139 + gpio-controller; 140 + #gpio-cells = <2>; 141 + gpio-ranges = <&pinctrl 0 0 288>; 142 + power-domains = <&cpg>; 143 + 144 + serial0-pins { 145 + pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */ 146 + <RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */ 147 + }; 148 + 149 + sd1-pwr-en-hog { 150 + gpio-hog; 151 + gpios = <RZT2H_GPIO(39, 2) 0>; 152 + output-high; 153 + line-name = "sd1_pwr_en"; 154 + }; 155 + 156 + i2c0-pins { 157 + pins = "RIIC0_SDA", "RIIC0_SCL"; 158 + input-enable; 159 + }; 160 + 161 + sd0-sd-group { 162 + ctrl-pins { 163 + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ 164 + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */ 165 + }; 166 + 167 + data-pins { 168 + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ 169 + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */ 170 + }; 171 + }; 172 + };

+3 -1

arch/arm/boot/dts/renesas/r7s72100-genmai.dts

··· 203 203 }; 204 204 205 205 &ostm0 { 206 + bootph-all; 206 207 status = "okay"; 207 208 }; 208 209 ··· 259 258 }; 260 259 261 260 scif2_pins: serial2 { 261 + bootph-all; 262 262 /* P3_0 as TxD2; P3_2 as RxD2 */ 263 263 pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>; 264 264 }; ··· 288 286 &scif2 { 289 287 pinctrl-names = "default"; 290 288 pinctrl-0 = <&scif2_pins>; 291 - 289 + bootph-all; 292 290 status = "okay"; 293 291 }; 294 292

+3 -1

arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts

··· 59 59 60 60 &pinctrl { 61 61 scif2_pins: serial2 { 62 + bootph-all; 62 63 /* P6_2 as RxD2; P6_3 as TxD2 */ 63 64 pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>; 64 65 }; ··· 100 99 }; 101 100 102 101 &ostm0 { 102 + bootph-all; 103 103 status = "okay"; 104 104 }; 105 105 ··· 111 109 &scif2 { 112 110 pinctrl-names = "default"; 113 111 pinctrl-0 = <&scif2_pins>; 114 - 112 + bootph-all; 115 113 status = "okay"; 116 114 }; 117 115

+3

arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts

··· 199 199 200 200 /* Serial Console */ 201 201 scif2_pins: serial2 { 202 + bootph-all; 202 203 pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */ 203 204 <RZA1_PINMUX(3, 2, 4)>; /* RxD2 */ 204 205 }; ··· 265 264 }; 266 265 267 266 &ostm0 { 267 + bootph-all; 268 268 status = "okay"; 269 269 }; 270 270 ··· 280 278 &scif2 { 281 279 pinctrl-names = "default"; 282 280 pinctrl-0 = <&scif2_pins>; 281 + bootph-all; 283 282 status = "okay"; 284 283 }; 285 284

+3

arch/arm/boot/dts/renesas/r7s72100.dtsi

··· 41 41 #address-cells = <1>; 42 42 #size-cells = <1>; 43 43 ranges = <0 0 0x18000000>; 44 + bootph-all; 44 45 }; 45 46 46 47 cpus { ··· 108 107 #address-cells = <1>; 109 108 #size-cells = <1>; 110 109 ranges; 110 + bootph-all; 111 111 112 112 L2: cache-controller@3ffff000 { 113 113 compatible = "arm,pl310-cache"; ··· 559 557 560 558 pinctrl: pinctrl@fcfe3000 { 561 559 compatible = "renesas,r7s72100-ports"; 560 + bootph-all; 562 561 563 562 reg = <0xfcfe3000 0x4230>; 564 563

+1 -1

arch/arm/boot/dts/renesas/r8a7791-porter.dts

··· 289 289 }; 290 290 291 291 can0_pins: can0 { 292 - groups = "can0_data"; 292 + groups = "can0_data_b"; 293 293 function = "can0"; 294 294 }; 295 295

+4

arch/arm64/boot/dts/renesas/Makefile

··· 180 180 dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk-cn15-sd.dtb 181 181 dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb 182 182 183 + dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb 184 + 185 + dtb-$(CONFIG_ARCH_R9A09G087) += r9a09g087m44-rzn2h-evk.dtb 186 + 183 187 dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo 184 188 dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo

+1 -1

arch/arm64/boot/dts/renesas/r8a774a1.dtsi

··· 1186 1186 <&can_clk>; 1187 1187 clock-names = "fck", "canfd", "can_clk"; 1188 1188 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1189 - assigned-clock-rates = <40000000>; 1189 + assigned-clock-rates = <80000000>; 1190 1190 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1191 1191 resets = <&cpg 914>; 1192 1192 status = "disabled";

+1 -1

arch/arm64/boot/dts/renesas/r8a774b1.dtsi

··· 1070 1070 <&can_clk>; 1071 1071 clock-names = "fck", "canfd", "can_clk"; 1072 1072 assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; 1073 - assigned-clock-rates = <40000000>; 1073 + assigned-clock-rates = <80000000>; 1074 1074 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1075 1075 resets = <&cpg 914>; 1076 1076 status = "disabled";

+1 -1

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

··· 1029 1029 <&can_clk>; 1030 1030 clock-names = "fck", "canfd", "can_clk"; 1031 1031 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 1032 - assigned-clock-rates = <40000000>; 1032 + assigned-clock-rates = <80000000>; 1033 1033 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1034 1034 resets = <&cpg 914>; 1035 1035 status = "disabled";

+1 -1

arch/arm64/boot/dts/renesas/r8a774e1.dtsi

··· 1298 1298 <&can_clk>; 1299 1299 clock-names = "fck", "canfd", "can_clk"; 1300 1300 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1301 - assigned-clock-rates = <40000000>; 1301 + assigned-clock-rates = <80000000>; 1302 1302 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1303 1303 resets = <&cpg 914>; 1304 1304 status = "disabled";

+1 -1

arch/arm64/boot/dts/renesas/r8a77951.dtsi

··· 1373 1373 <&can_clk>; 1374 1374 clock-names = "fck", "canfd", "can_clk"; 1375 1375 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 1376 - assigned-clock-rates = <40000000>; 1376 + assigned-clock-rates = <80000000>; 1377 1377 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1378 1378 resets = <&cpg 914>; 1379 1379 status = "disabled";

+1 -1

arch/arm64/boot/dts/renesas/r8a77960.dtsi

··· 1245 1245 <&can_clk>; 1246 1246 clock-names = "fck", "canfd", "can_clk"; 1247 1247 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; 1248 - assigned-clock-rates = <40000000>; 1248 + assigned-clock-rates = <80000000>; 1249 1249 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1250 1250 resets = <&cpg 914>; 1251 1251 status = "disabled";

+1 -1

arch/arm64/boot/dts/renesas/r8a77961.dtsi

··· 1245 1245 <&can_clk>; 1246 1246 clock-names = "fck", "canfd", "can_clk"; 1247 1247 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; 1248 - assigned-clock-rates = <40000000>; 1248 + assigned-clock-rates = <80000000>; 1249 1249 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1250 1250 resets = <&cpg 914>; 1251 1251 status = "disabled";

+1 -1

arch/arm64/boot/dts/renesas/r8a77965.dtsi

··· 1108 1108 <&can_clk>; 1109 1109 clock-names = "fck", "canfd", "can_clk"; 1110 1110 assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; 1111 - assigned-clock-rates = <40000000>; 1111 + assigned-clock-rates = <80000000>; 1112 1112 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; 1113 1113 resets = <&cpg 914>; 1114 1114 status = "disabled";

+1 -1

arch/arm64/boot/dts/renesas/r8a77970.dtsi

··· 568 568 <&can_clk>; 569 569 clock-names = "fck", "canfd", "can_clk"; 570 570 assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; 571 - assigned-clock-rates = <40000000>; 571 + assigned-clock-rates = <80000000>; 572 572 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 573 573 resets = <&cpg 914>; 574 574 status = "disabled";

+1 -1

arch/arm64/boot/dts/renesas/r8a77980.dtsi

··· 621 621 <&can_clk>; 622 622 clock-names = "fck", "canfd", "can_clk"; 623 623 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 624 - assigned-clock-rates = <40000000>; 624 + assigned-clock-rates = <80000000>; 625 625 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 626 626 resets = <&cpg 914>; 627 627 status = "disabled";

+1 -1

arch/arm64/boot/dts/renesas/r8a77990.dtsi

··· 1061 1061 <&can_clk>; 1062 1062 clock-names = "fck", "canfd", "can_clk"; 1063 1063 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; 1064 - assigned-clock-rates = <40000000>; 1064 + assigned-clock-rates = <80000000>; 1065 1065 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1066 1066 resets = <&cpg 914>; 1067 1067 status = "disabled";

+147 -2

arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts

··· 38 38 39 39 /dts-v1/; 40 40 #include <dt-bindings/gpio/gpio.h> 41 + #include <dt-bindings/thermal/thermal.h> 41 42 42 43 #include "r8a779g3.dtsi" 43 44 ··· 186 185 regulator-max-microvolt = <3300000>; 187 186 gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; 188 187 gpios-states = <1>; 189 - states = <3300000 0>, <1800000 1>; 188 + states = <1800000 0>, <3300000 1>; 189 + }; 190 + }; 191 + 192 + /* Use thermal-idle cooling for all SoC cores */ 193 + &a76_0 { 194 + #cooling-cells = <2>; 195 + 196 + a76_0_thermal_idle: thermal-idle { 197 + #cooling-cells = <2>; 198 + duration-us = <10000>; 199 + exit-latency-us = <500>; 200 + }; 201 + }; 202 + 203 + &a76_1 { 204 + a76_1_thermal_idle: thermal-idle { 205 + #cooling-cells = <2>; 206 + duration-us = <10000>; 207 + exit-latency-us = <500>; 208 + }; 209 + }; 210 + 211 + &a76_2 { 212 + a76_2_thermal_idle: thermal-idle { 213 + #cooling-cells = <2>; 214 + duration-us = <10000>; 215 + exit-latency-us = <500>; 216 + }; 217 + }; 218 + 219 + &a76_3 { 220 + a76_3_thermal_idle: thermal-idle { 221 + #cooling-cells = <2>; 222 + duration-us = <10000>; 223 + exit-latency-us = <500>; 190 224 }; 191 225 }; 192 226 ··· 592 556 drive-strength = <21>; 593 557 }; 594 558 559 + pins-vddq18-25-avb { 560 + pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0"; 561 + power-source = <1800>; 562 + }; 595 563 }; 596 564 597 565 /* Page 28 / CANFD_IF */ ··· 796 756 status = "okay"; 797 757 798 758 flash@0 { 799 - compatible = "spansion,s25fs512s", "jedec,spi-nor"; 759 + /* 760 + * EVTA1 is populated with Spansion S25FS512S 761 + * EVTB1 is populated with Winbond W77Q51NW 762 + */ 763 + compatible = "jedec,spi-nor"; 800 764 reg = <0>; 801 765 spi-max-frequency = <40000000>; 802 766 spi-rx-bus-width = <4>; ··· 840 796 /* Page 6 / SCIF_CLK_SOC_V */ 841 797 &scif_clk { /* X12 */ 842 798 clock-frequency = <24000000>; 799 + }; 800 + 801 + /* THS sensors in SoC, critical temperature trip point is 100C */ 802 + &sensor1_crit { 803 + temperature = <100000>; 804 + }; 805 + 806 + &sensor2_crit { 807 + temperature = <100000>; 808 + }; 809 + 810 + &sensor3_crit { 811 + temperature = <100000>; 812 + }; 813 + 814 + &sensor4_crit { 815 + temperature = <100000>; 816 + }; 817 + 818 + /* THS sensor in SoC near CA76 cores does more progressive cooling. */ 819 + &sensor_thermal_ca76 { 820 + critical-action = "shutdown"; 821 + 822 + cooling-maps { 823 + /* 824 + * The cooling-device minimum and maximum parameters inversely 825 + * match opp-table-0 {} node entries in r8a779g0.dtsi, in other 826 + * words, 0 refers to 1.8 GHz OPP and 4 refers to 500 MHz OPP. 827 + * This is because they refer to cooling levels, where maximum 828 + * cooling level happens at 500 MHz OPP, when the CPU core is 829 + * running slowly and therefore generates least heat. 830 + */ 831 + map0 { 832 + /* At 68C, inhibit 1.7 GHz and 1.8 GHz modes */ 833 + trip = <&sensor3_passive_low>; 834 + cooling-device = <&a76_0 2 4>; 835 + contribution = <128>; 836 + }; 837 + 838 + map1 { 839 + /* At 72C, inhibit 1.5 GHz mode */ 840 + trip = <&sensor3_passive_mid>; 841 + cooling-device = <&a76_0 3 4>; 842 + contribution = <256>; 843 + }; 844 + 845 + map2 { 846 + /* At 76C, start injecting idle states 0..80% of time */ 847 + trip = <&sensor3_passive_hi>; 848 + cooling-device = <&a76_0_thermal_idle 0 80>, 849 + <&a76_1_thermal_idle 0 80>, 850 + <&a76_2_thermal_idle 0 80>, 851 + <&a76_3_thermal_idle 0 80>; 852 + contribution = <512>; 853 + }; 854 + 855 + map3 { 856 + /* At 80C, inhibit 1.0 GHz mode */ 857 + trip = <&sensor3_passive_crit>; 858 + cooling-device = <&a76_0 4 4>; 859 + contribution = <1024>; 860 + }; 861 + }; 862 + 863 + trips { 864 + sensor3_passive_low: sensor3-passive-low { 865 + temperature = <68000>; 866 + hysteresis = <2000>; 867 + type = "passive"; 868 + }; 869 + 870 + sensor3_passive_mid: sensor3-passive-mid { 871 + temperature = <72000>; 872 + hysteresis = <2000>; 873 + type = "passive"; 874 + }; 875 + 876 + sensor3_passive_hi: sensor3-passive-hi { 877 + temperature = <76000>; 878 + hysteresis = <2000>; 879 + type = "passive"; 880 + }; 881 + 882 + sensor3_passive_crit: sensor3-passive-crit { 883 + temperature = <80000>; 884 + hysteresis = <2000>; 885 + type = "passive"; 886 + }; 887 + }; 888 + }; 889 + 890 + &sensor_thermal_cnn { 891 + critical-action = "shutdown"; 892 + }; 893 + 894 + &sensor_thermal_cr52 { 895 + critical-action = "shutdown"; 896 + }; 897 + 898 + &sensor_thermal_ddr1 { 899 + critical-action = "shutdown"; 843 900 };

+36

arch/arm64/boot/dts/renesas/r9a08g045.dtsi

··· 272 272 }; 273 273 }; 274 274 275 + i3c: i3c@1005b000 { 276 + compatible = "renesas,r9a08g045-i3c"; 277 + reg = <0 0x1005b000 0 0x1000>; 278 + clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>, 279 + <&cpg CPG_MOD R9A08G045_I3C_TCLK>; 280 + clock-names = "pclk", "tclk"; 281 + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 282 + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 283 + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 284 + <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>, 285 + <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>, 286 + <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 287 + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 288 + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 289 + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 290 + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 291 + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 292 + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 293 + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 294 + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 295 + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 296 + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 297 + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 298 + interrupt-names = "ierr", "terr", "abort", "resp", 299 + "cmd", "ibi", "rx", "tx", "rcv", 300 + "st", "sp", "tend", "nack", "al", 301 + "tmo", "wu", "exit"; 302 + resets = <&cpg R9A08G045_I3C_PRESETN>, 303 + <&cpg R9A08G045_I3C_TRESETN>; 304 + reset-names = "presetn", "tresetn"; 305 + power-domains = <&cpg>; 306 + #address-cells = <3>; 307 + #size-cells = <0>; 308 + status = "disabled"; 309 + }; 310 + 275 311 vbattb: clock-controller@1005c000 { 276 312 compatible = "renesas,r9a08g045-vbattb"; 277 313 reg = <0 0x1005c000 0 0x1000>;

+205

arch/arm64/boot/dts/renesas/r9a09g047.dtsi

··· 301 301 status = "disabled"; 302 302 }; 303 303 304 + dmac0: dma-controller@11400000 { 305 + compatible = "renesas,r9a09g047-dmac", 306 + "renesas,r9a09g057-dmac"; 307 + reg = <0 0x11400000 0 0x10000>; 308 + interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 309 + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 310 + <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 311 + <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 312 + <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 313 + <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 314 + <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 315 + <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 316 + <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 317 + <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 318 + <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 319 + <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 320 + <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 321 + <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 322 + <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 323 + <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 324 + <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 325 + interrupt-names = "error", 326 + "ch0", "ch1", "ch2", "ch3", 327 + "ch4", "ch5", "ch6", "ch7", 328 + "ch8", "ch9", "ch10", "ch11", 329 + "ch12", "ch13", "ch14", "ch15"; 330 + clocks = <&cpg CPG_MOD 0x0>; 331 + power-domains = <&cpg>; 332 + resets = <&cpg 0x31>; 333 + #dma-cells = <1>; 334 + dma-channels = <16>; 335 + renesas,icu = <&icu 4>; 336 + }; 337 + 338 + dmac1: dma-controller@14830000 { 339 + compatible = "renesas,r9a09g047-dmac", 340 + "renesas,r9a09g057-dmac"; 341 + reg = <0 0x14830000 0 0x10000>; 342 + interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 343 + <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 344 + <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 345 + <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 346 + <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 347 + <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 348 + <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 349 + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 350 + <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 351 + <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 352 + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 353 + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 354 + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 355 + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 356 + <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 357 + <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 358 + <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 359 + interrupt-names = "error", 360 + "ch0", "ch1", "ch2", "ch3", 361 + "ch4", "ch5", "ch6", "ch7", 362 + "ch8", "ch9", "ch10", "ch11", 363 + "ch12", "ch13", "ch14", "ch15"; 364 + clocks = <&cpg CPG_MOD 0x1>; 365 + power-domains = <&cpg>; 366 + resets = <&cpg 0x32>; 367 + #dma-cells = <1>; 368 + dma-channels = <16>; 369 + renesas,icu = <&icu 0>; 370 + }; 371 + 372 + dmac2: dma-controller@14840000 { 373 + compatible = "renesas,r9a09g047-dmac", 374 + "renesas,r9a09g057-dmac"; 375 + reg = <0 0x14840000 0 0x10000>; 376 + interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 377 + <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 378 + <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 379 + <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 380 + <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 381 + <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 382 + <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 383 + <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 384 + <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 385 + <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 386 + <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 387 + <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 388 + <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 389 + <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 390 + <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 391 + <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 392 + <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 393 + interrupt-names = "error", 394 + "ch0", "ch1", "ch2", "ch3", 395 + "ch4", "ch5", "ch6", "ch7", 396 + "ch8", "ch9", "ch10", "ch11", 397 + "ch12", "ch13", "ch14", "ch15"; 398 + clocks = <&cpg CPG_MOD 0x2>; 399 + power-domains = <&cpg>; 400 + resets = <&cpg 0x33>; 401 + #dma-cells = <1>; 402 + dma-channels = <16>; 403 + renesas,icu = <&icu 1>; 404 + }; 405 + 406 + dmac3: dma-controller@12000000 { 407 + compatible = "renesas,r9a09g047-dmac", 408 + "renesas,r9a09g057-dmac"; 409 + reg = <0 0x12000000 0 0x10000>; 410 + interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 411 + <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 412 + <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 413 + <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 414 + <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 415 + <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 416 + <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 417 + <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 418 + <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 419 + <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 420 + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 421 + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 422 + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 423 + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 424 + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 425 + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 426 + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 427 + interrupt-names = "error", 428 + "ch0", "ch1", "ch2", "ch3", 429 + "ch4", "ch5", "ch6", "ch7", 430 + "ch8", "ch9", "ch10", "ch11", 431 + "ch12", "ch13", "ch14", "ch15"; 432 + clocks = <&cpg CPG_MOD 0x3>; 433 + power-domains = <&cpg>; 434 + resets = <&cpg 0x34>; 435 + #dma-cells = <1>; 436 + dma-channels = <16>; 437 + renesas,icu = <&icu 2>; 438 + }; 439 + 440 + dmac4: dma-controller@12010000 { 441 + compatible = "renesas,r9a09g047-dmac", 442 + "renesas,r9a09g057-dmac"; 443 + reg = <0 0x12010000 0 0x10000>; 444 + interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 445 + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 446 + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 447 + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 448 + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 449 + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 450 + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 451 + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 452 + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 453 + <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 454 + <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 455 + <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 456 + <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 457 + <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 458 + <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 459 + <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 460 + <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 461 + interrupt-names = "error", 462 + "ch0", "ch1", "ch2", "ch3", 463 + "ch4", "ch5", "ch6", "ch7", 464 + "ch8", "ch9", "ch10", "ch11", 465 + "ch12", "ch13", "ch14", "ch15"; 466 + clocks = <&cpg CPG_MOD 0x4>; 467 + power-domains = <&cpg>; 468 + resets = <&cpg 0x35>; 469 + #dma-cells = <1>; 470 + dma-channels = <16>; 471 + renesas,icu = <&icu 3>; 472 + }; 473 + 304 474 scif0: serial@11c01400 { 305 475 compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; 306 476 reg = <0 0x11c01400 0 0x400>; ··· 489 319 clock-names = "fck"; 490 320 power-domains = <&cpg>; 491 321 resets = <&cpg 0x95>; 322 + status = "disabled"; 323 + }; 324 + 325 + i3c: i3c@12400000 { 326 + compatible = "renesas,r9a09g047-i3c"; 327 + reg = <0 0x12400000 0 0x10000>; 328 + clocks = <&cpg CPG_MOD 0x91>, 329 + <&cpg CPG_MOD 0x92>, 330 + <&cpg CPG_MOD 0x90>; 331 + clock-names = "pclk", "tclk", "pclkrw"; 332 + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 333 + <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 334 + <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 335 + <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 336 + <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 337 + <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 338 + <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 339 + <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 340 + <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 341 + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 342 + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 343 + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 344 + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 345 + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 346 + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 347 + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 348 + interrupt-names = "ierr", "terr", "abort", "resp", 349 + "cmd", "ibi", "rx", "tx", "rcv", 350 + "st", "sp", "tend", "nack", "al", 351 + "tmo", "wu"; 352 + resets = <&cpg 0x96>, <&cpg 0x97>; 353 + reset-names = "presetn", "tresetn"; 354 + power-domains = <&cpg>; 355 + #address-cells = <3>; 356 + #size-cells = <0>; 492 357 status = "disabled"; 493 358 }; 494 359

+8 -8

arch/arm64/boot/dts/renesas/r9a09g056.dtsi

··· 735 735 "rx-queue-0", "rx-queue-1", "rx-queue-2", 736 736 "rx-queue-3", "tx-queue-0", "tx-queue-1", 737 737 "tx-queue-2", "tx-queue-3"; 738 - clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 739 - <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, 740 - <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 741 - <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 738 + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 739 + <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, 740 + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 741 + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 742 742 clock-names = "stmmaceth", "pclk", "ptp_ref", 743 743 "tx", "rx", "tx-180", "rx-180"; 744 744 resets = <&cpg 0xb0>; ··· 836 836 "rx-queue-0", "rx-queue-1", "rx-queue-2", 837 837 "rx-queue-3", "tx-queue-0", "tx-queue-1", 838 838 "tx-queue-2", "tx-queue-3"; 839 - clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 840 - <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, 841 - <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 842 - <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 839 + clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 840 + <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, 841 + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 842 + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 843 843 clock-names = "stmmaceth", "pclk", "ptp_ref", 844 844 "tx", "rx", "tx-180", "rx-180"; 845 845 resets = <&cpg 0xb1>;

+1 -1

arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts

··· 334 334 335 335 usb20_pins: usb20 { 336 336 ovc { 337 - pinmux = <RZV2N_PORT_PINMUX(9, 6, 14)>; /* OVC */ 337 + pinmux = <RZV2N_PORT_PINMUX(9, 6, 14)>; /* OVC */ 338 338 }; 339 339 340 340 vbus {

+71 -8

arch/arm64/boot/dts/renesas/r9a09g057.dtsi

··· 607 607 status = "disabled"; 608 608 }; 609 609 610 + rspi0: spi@12800000 { 611 + compatible = "renesas,r9a09g057-rspi"; 612 + reg = <0x0 0x12800000 0x0 0x400>; 613 + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 614 + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 615 + <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, 616 + <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, 617 + <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>; 618 + interrupt-names = "idle", "error", "end", "rx", "tx"; 619 + clocks = <&cpg CPG_MOD 0x54>, 620 + <&cpg CPG_MOD 0x55>, 621 + <&cpg CPG_MOD 0x56>; 622 + clock-names = "pclk", "pclk_sfr", "tclk"; 623 + resets = <&cpg 0x7b>, <&cpg 0x7c>; 624 + reset-names = "presetn", "tresetn"; 625 + power-domains = <&cpg>; 626 + #address-cells = <1>; 627 + #size-cells = <0>; 628 + status = "disabled"; 629 + }; 630 + 631 + rspi1: spi@12800400 { 632 + compatible = "renesas,r9a09g057-rspi"; 633 + reg = <0x0 0x12800400 0x0 0x400>; 634 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 635 + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 636 + <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, 637 + <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>, 638 + <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>; 639 + interrupt-names = "idle", "error", "end", "rx", "tx"; 640 + clocks = <&cpg CPG_MOD 0x57>, 641 + <&cpg CPG_MOD 0x58>, 642 + <&cpg CPG_MOD 0x59>; 643 + clock-names = "pclk", "pclk_sfr", "tclk"; 644 + resets = <&cpg 0x7d>, <&cpg 0x7e>; 645 + reset-names = "presetn", "tresetn"; 646 + power-domains = <&cpg>; 647 + #address-cells = <1>; 648 + #size-cells = <0>; 649 + status = "disabled"; 650 + }; 651 + 652 + rspi2: spi@12800800 { 653 + compatible = "renesas,r9a09g057-rspi"; 654 + reg = <0x0 0x12800800 0x0 0x400>; 655 + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 656 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 657 + <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 658 + <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>, 659 + <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>; 660 + interrupt-names = "idle", "error", "end", "rx", "tx"; 661 + clocks = <&cpg CPG_MOD 0x5a>, 662 + <&cpg CPG_MOD 0x5b>, 663 + <&cpg CPG_MOD 0x5c>; 664 + clock-names = "pclk", "pclk_sfr", "tclk"; 665 + resets = <&cpg 0x7f>, <&cpg 0x80>; 666 + reset-names = "presetn", "tresetn"; 667 + power-domains = <&cpg>; 668 + #address-cells = <1>; 669 + #size-cells = <0>; 670 + status = "disabled"; 671 + }; 672 + 610 673 i2c0: i2c@14400400 { 611 674 compatible = "renesas,riic-r9a09g057"; 612 675 reg = <0 0x14400400 0 0x400>; ··· 1083 1020 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1084 1021 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1085 1022 "tx-queue-2", "tx-queue-3"; 1086 - clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 1087 - <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, 1088 - <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 1089 - <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 1023 + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 1024 + <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, 1025 + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 1026 + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 1090 1027 clock-names = "stmmaceth", "pclk", "ptp_ref", 1091 1028 "tx", "rx", "tx-180", "rx-180"; 1092 1029 resets = <&cpg 0xb0>; ··· 1184 1121 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1185 1122 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1186 1123 "tx-queue-2", "tx-queue-3"; 1187 - clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1188 - <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, 1189 - <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1190 - <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1124 + clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1125 + <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, 1126 + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1127 + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1191 1128 clock-names = "stmmaceth", "pclk", "ptp_ref", 1192 1129 "tx", "rx", "tx-180", "rx-180"; 1193 1130 resets = <&cpg 0xb1>;

+1 -1

arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts

··· 353 353 354 354 usb20_pins: usb20 { 355 355 ovc { 356 - pinmux = <RZV2H_PORT_PINMUX(9, 6, 14)>; /* OVC */ 356 + pinmux = <RZV2H_PORT_PINMUX(9, 6, 14)>; /* OVC */ 357 357 }; 358 358 359 359 vbus {

+2 -2

arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts

··· 1 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 /* 3 - * Device Tree Source for Yuridenki-Shokai the Kakip board 3 + * Device Tree Source for the Yuridenki-Shokai Kakip board 4 4 * 5 5 * Copyright (C) 2024 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 6 6 */ ··· 84 84 85 85 &pinctrl { 86 86 scif_pins: scif { 87 - pins = "SCIF_RXD", "SCIF_TXD"; 87 + pins = "SCIF_RXD", "SCIF_TXD"; 88 88 }; 89 89 90 90 sd0-pwr-en-hog {

+292

arch/arm64/boot/dts/renesas/r9a09g077.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Device Tree Source for the RZ/T2H SoC 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> 9 + #include <dt-bindings/interrupt-controller/arm-gic.h> 10 + 11 + / { 12 + compatible = "renesas,r9a09g077"; 13 + #address-cells = <2>; 14 + #size-cells = <2>; 15 + 16 + cpus { 17 + #address-cells = <1>; 18 + #size-cells = <0>; 19 + 20 + cpu0: cpu@0 { 21 + compatible = "arm,cortex-a55"; 22 + reg = <0>; 23 + device_type = "cpu"; 24 + next-level-cache = <&L3_CA55>; 25 + enable-method = "psci"; 26 + }; 27 + 28 + cpu1: cpu@100 { 29 + compatible = "arm,cortex-a55"; 30 + reg = <0x100>; 31 + device_type = "cpu"; 32 + next-level-cache = <&L3_CA55>; 33 + enable-method = "psci"; 34 + }; 35 + 36 + cpu2: cpu@200 { 37 + compatible = "arm,cortex-a55"; 38 + reg = <0x200>; 39 + device_type = "cpu"; 40 + next-level-cache = <&L3_CA55>; 41 + enable-method = "psci"; 42 + }; 43 + 44 + cpu3: cpu@300 { 45 + compatible = "arm,cortex-a55"; 46 + reg = <0x300>; 47 + device_type = "cpu"; 48 + next-level-cache = <&L3_CA55>; 49 + enable-method = "psci"; 50 + }; 51 + 52 + L3_CA55: cache-controller-0 { 53 + compatible = "cache"; 54 + cache-unified; 55 + cache-size = <0x100000>; 56 + cache-level = <3>; 57 + }; 58 + }; 59 + 60 + extal_clk: extal { 61 + compatible = "fixed-clock"; 62 + #clock-cells = <0>; 63 + /* This value must be overridden by the board */ 64 + clock-frequency = <0>; 65 + }; 66 + 67 + psci { 68 + compatible = "arm,psci-1.0", "arm,psci-0.2"; 69 + method = "smc"; 70 + }; 71 + 72 + soc: soc { 73 + compatible = "simple-bus"; 74 + interrupt-parent = <&gic>; 75 + #address-cells = <2>; 76 + #size-cells = <2>; 77 + ranges; 78 + 79 + sci0: serial@80005000 { 80 + compatible = "renesas,r9a09g077-rsci"; 81 + reg = <0 0x80005000 0 0x400>; 82 + interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 83 + <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, 84 + <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, 85 + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; 86 + interrupt-names = "eri", "rxi", "txi", "tei"; 87 + clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 88 + clock-names = "operation", "bus"; 89 + power-domains = <&cpg>; 90 + status = "disabled"; 91 + }; 92 + 93 + sci1: serial@80005400 { 94 + compatible = "renesas,r9a09g077-rsci"; 95 + reg = <0 0x80005400 0 0x400>; 96 + interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 97 + <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, 98 + <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, 99 + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 100 + interrupt-names = "eri", "rxi", "txi", "tei"; 101 + clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 102 + clock-names = "operation", "bus"; 103 + power-domains = <&cpg>; 104 + status = "disabled"; 105 + }; 106 + 107 + sci2: serial@80005800 { 108 + compatible = "renesas,r9a09g077-rsci"; 109 + reg = <0 0x80005800 0 0x400>; 110 + interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 111 + <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, 112 + <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, 113 + <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 114 + interrupt-names = "eri", "rxi", "txi", "tei"; 115 + clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 116 + clock-names = "operation", "bus"; 117 + power-domains = <&cpg>; 118 + status = "disabled"; 119 + }; 120 + 121 + sci3: serial@80005c00 { 122 + compatible = "renesas,r9a09g077-rsci"; 123 + reg = <0 0x80005c00 0 0x400>; 124 + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 125 + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, 126 + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 127 + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 128 + interrupt-names = "eri", "rxi", "txi", "tei"; 129 + clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 130 + clock-names = "operation", "bus"; 131 + power-domains = <&cpg>; 132 + status = "disabled"; 133 + }; 134 + 135 + sci4: serial@80006000 { 136 + compatible = "renesas,r9a09g077-rsci"; 137 + reg = <0 0x80006000 0 0x400>; 138 + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 139 + <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>, 140 + <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>, 141 + <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 142 + interrupt-names = "eri", "rxi", "txi", "tei"; 143 + clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 144 + clock-names = "operation", "bus"; 145 + power-domains = <&cpg>; 146 + status = "disabled"; 147 + }; 148 + 149 + sci5: serial@81005000 { 150 + compatible = "renesas,r9a09g077-rsci"; 151 + reg = <0 0x81005000 0 0x400>; 152 + interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 153 + <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>, 154 + <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>, 155 + <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 156 + interrupt-names = "eri", "rxi", "txi", "tei"; 157 + clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 158 + clock-names = "operation", "bus"; 159 + power-domains = <&cpg>; 160 + status = "disabled"; 161 + }; 162 + 163 + i2c0: i2c@80088000 { 164 + compatible = "renesas,riic-r9a09g077"; 165 + reg = <0 0x80088000 0 0x400>; 166 + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 167 + <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>, 168 + <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>, 169 + <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>; 170 + interrupt-names = "eei", "rxi", "txi", "tei"; 171 + clocks = <&cpg CPG_MOD 100>; 172 + power-domains = <&cpg>; 173 + #address-cells = <1>; 174 + #size-cells = <0>; 175 + status = "disabled"; 176 + }; 177 + 178 + i2c1: i2c@80088400 { 179 + compatible = "renesas,riic-r9a09g077"; 180 + reg = <0 0x80088400 0 0x400>; 181 + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>, 182 + <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>, 183 + <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>, 184 + <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>; 185 + interrupt-names = "eei", "rxi", "txi", "tei"; 186 + clocks = <&cpg CPG_MOD 101>; 187 + power-domains = <&cpg>; 188 + #address-cells = <1>; 189 + #size-cells = <0>; 190 + status = "disabled"; 191 + }; 192 + 193 + i2c2: i2c@81008000 { 194 + compatible = "renesas,riic-r9a09g077"; 195 + reg = <0 0x81008000 0 0x400>; 196 + interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 197 + <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>, 198 + <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 199 + <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>; 200 + interrupt-names = "eei", "rxi", "txi", "tei"; 201 + clocks = <&cpg CPG_MOD 601>; 202 + power-domains = <&cpg>; 203 + #address-cells = <1>; 204 + #size-cells = <0>; 205 + status = "disabled"; 206 + }; 207 + 208 + cpg: clock-controller@80280000 { 209 + compatible = "renesas,r9a09g077-cpg-mssr"; 210 + reg = <0 0x80280000 0 0x1000>, 211 + <0 0x81280000 0 0x9000>; 212 + clocks = <&extal_clk>; 213 + clock-names = "extal"; 214 + #clock-cells = <2>; 215 + #reset-cells = <1>; 216 + #power-domain-cells = <0>; 217 + }; 218 + 219 + pinctrl: pinctrl@802c0000 { 220 + compatible = "renesas,r9a09g077-pinctrl"; 221 + reg = <0 0x802c0000 0 0x10000>, 222 + <0 0x812c0000 0 0x10000>, 223 + <0 0x802b0000 0 0x10000>; 224 + reg-names = "nsr", "srs", "srn"; 225 + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 226 + gpio-controller; 227 + #gpio-cells = <2>; 228 + gpio-ranges = <&pinctrl 0 0 288>; 229 + power-domains = <&cpg>; 230 + }; 231 + 232 + gic: interrupt-controller@83000000 { 233 + compatible = "arm,gic-v3"; 234 + reg = <0x0 0x83000000 0 0x40000>, 235 + <0x0 0x83040000 0 0x160000>; 236 + #interrupt-cells = <3>; 237 + #address-cells = <0>; 238 + interrupt-controller; 239 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 240 + }; 241 + 242 + sdhi0: mmc@92080000 { 243 + compatible = "renesas,sdhi-r9a09g077", 244 + "renesas,sdhi-r9a09g057"; 245 + reg = <0x0 0x92080000 0 0x10000>; 246 + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 247 + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 248 + clocks = <&cpg CPG_MOD 1212>, 249 + <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; 250 + clock-names = "aclk", "clkh"; 251 + power-domains = <&cpg>; 252 + status = "disabled"; 253 + 254 + sdhi0_vqmmc: vqmmc-regulator { 255 + regulator-name = "SDHI0-VQMMC"; 256 + regulator-min-microvolt = <1800000>; 257 + regulator-max-microvolt = <3300000>; 258 + status = "disabled"; 259 + }; 260 + }; 261 + 262 + sdhi1: mmc@92090000 { 263 + compatible = "renesas,sdhi-r9a09g077", 264 + "renesas,sdhi-r9a09g057"; 265 + reg = <0x0 0x92090000 0 0x10000>; 266 + interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 267 + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 268 + clocks = <&cpg CPG_MOD 1213>, 269 + <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; 270 + clock-names = "aclk", "clkh"; 271 + power-domains = <&cpg>; 272 + status = "disabled"; 273 + 274 + sdhi1_vqmmc: vqmmc-regulator { 275 + regulator-name = "SDHI1-VQMMC"; 276 + regulator-min-microvolt = <1800000>; 277 + regulator-max-microvolt = <3300000>; 278 + status = "disabled"; 279 + }; 280 + }; 281 + }; 282 + 283 + timer { 284 + compatible = "arm,armv8-timer"; 285 + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 286 + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 287 + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 288 + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 289 + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 290 + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 291 + }; 292 + };

+52

arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Device Tree Source for the RZ/T2H EVK board 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> 11 + 12 + #include "r9a09g077m44.dtsi" 13 + #include "rzt2h-n2h-evk-common.dtsi" 14 + 15 + / { 16 + model = "Renesas RZ/T2H EVK Board based on r9a09g077m44"; 17 + compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077"; 18 + }; 19 + 20 + &i2c0 { 21 + pinctrl-0 = <&i2c0_pins>; 22 + pinctrl-names = "default"; 23 + clock-frequency = <400000>; 24 + status = "okay"; 25 + }; 26 + 27 + &i2c1 { 28 + pinctrl-0 = <&i2c1_pins>; 29 + pinctrl-names = "default"; 30 + clock-frequency = <400000>; 31 + status = "okay"; 32 + }; 33 + 34 + &pinctrl { 35 + /* 36 + * I2C0 Pin Configuration: 37 + * ------------------------ 38 + * Signal | Pin | SW6 39 + * -------|---------|-------------- 40 + * SCL | P23_3 | 7: ON, 8: OFF 41 + * SDA | P23_4 | 9: ON, 10: OFF 42 + */ 43 + i2c0_pins: i2c0-pins { 44 + pinmux = <RZT2H_PORT_PINMUX(23, 3, 0x17)>, 45 + <RZT2H_PORT_PINMUX(23, 4, 0x17)>; 46 + }; 47 + 48 + i2c1_pins: i2c1-pins { 49 + pinmux = <RZT2H_PORT_PINMUX(5, 0, 0x17)>, /* SDA */ 50 + <RZT2H_PORT_PINMUX(4, 7, 0x17)>; /* SCL */ 51 + }; 52 + };

+13

arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Device Tree Source for the RZ/T2H 4-core SoC 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + /dts-v1/; 9 + #include "r9a09g077.dtsi" 10 + 11 + / { 12 + compatible = "renesas,r9a09g077m44", "renesas,r9a09g077"; 13 + };

+279

arch/arm64/boot/dts/renesas/r9a09g087.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Device Tree Source for the RZ/N2H SoC 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h> 9 + #include <dt-bindings/interrupt-controller/arm-gic.h> 10 + 11 + / { 12 + compatible = "renesas,r9a09g087"; 13 + #address-cells = <2>; 14 + #size-cells = <2>; 15 + 16 + cpus { 17 + #address-cells = <1>; 18 + #size-cells = <0>; 19 + 20 + cpu0: cpu@0 { 21 + compatible = "arm,cortex-a55"; 22 + reg = <0>; 23 + device_type = "cpu"; 24 + next-level-cache = <&L3_CA55>; 25 + enable-method = "psci"; 26 + }; 27 + 28 + cpu1: cpu@100 { 29 + compatible = "arm,cortex-a55"; 30 + reg = <0x100>; 31 + device_type = "cpu"; 32 + next-level-cache = <&L3_CA55>; 33 + enable-method = "psci"; 34 + }; 35 + 36 + cpu2: cpu@200 { 37 + compatible = "arm,cortex-a55"; 38 + reg = <0x200>; 39 + device_type = "cpu"; 40 + next-level-cache = <&L3_CA55>; 41 + enable-method = "psci"; 42 + }; 43 + 44 + cpu3: cpu@300 { 45 + compatible = "arm,cortex-a55"; 46 + reg = <0x300>; 47 + device_type = "cpu"; 48 + next-level-cache = <&L3_CA55>; 49 + enable-method = "psci"; 50 + }; 51 + 52 + L3_CA55: cache-controller-0 { 53 + compatible = "cache"; 54 + cache-unified; 55 + cache-size = <0x100000>; 56 + cache-level = <3>; 57 + }; 58 + }; 59 + 60 + extal_clk: extal { 61 + compatible = "fixed-clock"; 62 + #clock-cells = <0>; 63 + /* This value must be overridden by the board */ 64 + clock-frequency = <0>; 65 + }; 66 + 67 + psci { 68 + compatible = "arm,psci-1.0", "arm,psci-0.2"; 69 + method = "smc"; 70 + }; 71 + 72 + soc: soc { 73 + compatible = "simple-bus"; 74 + interrupt-parent = <&gic>; 75 + #address-cells = <2>; 76 + #size-cells = <2>; 77 + ranges; 78 + 79 + sci0: serial@80005000 { 80 + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 81 + reg = <0 0x80005000 0 0x400>; 82 + interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 83 + <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, 84 + <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, 85 + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; 86 + interrupt-names = "eri", "rxi", "txi", "tei"; 87 + clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 88 + clock-names = "operation", "bus"; 89 + power-domains = <&cpg>; 90 + status = "disabled"; 91 + }; 92 + 93 + sci1: serial@80005400 { 94 + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 95 + reg = <0 0x80005400 0 0x400>; 96 + interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 97 + <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, 98 + <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, 99 + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 100 + interrupt-names = "eri", "rxi", "txi", "tei"; 101 + clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 102 + clock-names = "operation", "bus"; 103 + power-domains = <&cpg>; 104 + status = "disabled"; 105 + }; 106 + 107 + sci2: serial@80005800 { 108 + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 109 + reg = <0 0x80005800 0 0x400>; 110 + interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 111 + <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, 112 + <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, 113 + <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 114 + interrupt-names = "eri", "rxi", "txi", "tei"; 115 + clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 116 + clock-names = "operation", "bus"; 117 + power-domains = <&cpg>; 118 + status = "disabled"; 119 + }; 120 + 121 + sci3: serial@80005c00 { 122 + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 123 + reg = <0 0x80005c00 0 0x400>; 124 + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 125 + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, 126 + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 127 + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 128 + interrupt-names = "eri", "rxi", "txi", "tei"; 129 + clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 130 + clock-names = "operation", "bus"; 131 + power-domains = <&cpg>; 132 + status = "disabled"; 133 + }; 134 + 135 + sci4: serial@80006000 { 136 + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 137 + reg = <0 0x80006000 0 0x400>; 138 + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 139 + <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>, 140 + <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>, 141 + <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 142 + interrupt-names = "eri", "rxi", "txi", "tei"; 143 + clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 144 + clock-names = "operation", "bus"; 145 + power-domains = <&cpg>; 146 + status = "disabled"; 147 + }; 148 + 149 + sci5: serial@81005000 { 150 + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 151 + reg = <0 0x81005000 0 0x400>; 152 + interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 153 + <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>, 154 + <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>, 155 + <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 156 + interrupt-names = "eri", "rxi", "txi", "tei"; 157 + clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 158 + clock-names = "operation", "bus"; 159 + power-domains = <&cpg>; 160 + status = "disabled"; 161 + }; 162 + 163 + i2c0: i2c@80088000 { 164 + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 165 + reg = <0 0x80088000 0 0x400>; 166 + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 167 + <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>, 168 + <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>, 169 + <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>; 170 + interrupt-names = "eei", "rxi", "txi", "tei"; 171 + clocks = <&cpg CPG_MOD 100>; 172 + power-domains = <&cpg>; 173 + #address-cells = <1>; 174 + #size-cells = <0>; 175 + status = "disabled"; 176 + }; 177 + 178 + i2c1: i2c@80088400 { 179 + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 180 + reg = <0 0x80088400 0 0x400>; 181 + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>, 182 + <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>, 183 + <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>, 184 + <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>; 185 + interrupt-names = "eei", "rxi", "txi", "tei"; 186 + clocks = <&cpg CPG_MOD 101>; 187 + power-domains = <&cpg>; 188 + #address-cells = <1>; 189 + #size-cells = <0>; 190 + status = "disabled"; 191 + }; 192 + 193 + i2c2: i2c@81008000 { 194 + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 195 + reg = <0 0x81008000 0 0x400>; 196 + interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 197 + <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>, 198 + <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 199 + <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>; 200 + interrupt-names = "eei", "rxi", "txi", "tei"; 201 + clocks = <&cpg CPG_MOD 601>; 202 + power-domains = <&cpg>; 203 + #address-cells = <1>; 204 + #size-cells = <0>; 205 + status = "disabled"; 206 + }; 207 + 208 + cpg: clock-controller@80280000 { 209 + compatible = "renesas,r9a09g087-cpg-mssr"; 210 + reg = <0 0x80280000 0 0x1000>, 211 + <0 0x81280000 0 0x9000>; 212 + clocks = <&extal_clk>; 213 + clock-names = "extal"; 214 + #clock-cells = <2>; 215 + #reset-cells = <1>; 216 + #power-domain-cells = <0>; 217 + }; 218 + 219 + gic: interrupt-controller@83000000 { 220 + compatible = "arm,gic-v3"; 221 + reg = <0x0 0x83000000 0 0x40000>, 222 + <0x0 0x83040000 0 0x160000>; 223 + #interrupt-cells = <3>; 224 + #address-cells = <0>; 225 + interrupt-controller; 226 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 227 + }; 228 + 229 + sdhi0: mmc@92080000 { 230 + compatible = "renesas,sdhi-r9a09g087", 231 + "renesas,sdhi-r9a09g057"; 232 + reg = <0x0 0x92080000 0 0x10000>; 233 + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 234 + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 235 + clocks = <&cpg CPG_MOD 1212>, 236 + <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; 237 + clock-names = "aclk", "clkh"; 238 + power-domains = <&cpg>; 239 + status = "disabled"; 240 + 241 + sdhi0_vqmmc: vqmmc-regulator { 242 + regulator-name = "SDHI0-VQMMC"; 243 + regulator-min-microvolt = <1800000>; 244 + regulator-max-microvolt = <3300000>; 245 + status = "disabled"; 246 + }; 247 + }; 248 + 249 + sdhi1: mmc@92090000 { 250 + compatible = "renesas,sdhi-r9a09g087", 251 + "renesas,sdhi-r9a09g057"; 252 + reg = <0x0 0x92090000 0 0x10000>; 253 + interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 254 + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 255 + clocks = <&cpg CPG_MOD 1213>, 256 + <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; 257 + clock-names = "aclk", "clkh"; 258 + power-domains = <&cpg>; 259 + status = "disabled"; 260 + 261 + sdhi1_vqmmc: vqmmc-regulator { 262 + regulator-name = "SDHI1-VQMMC"; 263 + regulator-min-microvolt = <1800000>; 264 + regulator-max-microvolt = <3300000>; 265 + status = "disabled"; 266 + }; 267 + }; 268 + }; 269 + 270 + timer { 271 + compatible = "arm,armv8-timer"; 272 + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 273 + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 274 + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 275 + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 276 + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 277 + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 278 + }; 279 + };

+16

arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Device Tree Source for the RZ/N2H EVK board 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "r9a09g087m44.dtsi" 11 + #include "rzt2h-n2h-evk-common.dtsi" 12 + 13 + / { 14 + model = "Renesas RZ/N2H EVK Board based on r9a09g087m44"; 15 + compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087"; 16 + };

+13

arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Device Tree Source for the RZ/N2H 4-core SoC 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + /dts-v1/; 9 + #include "r9a09g087.dtsi" 10 + 11 + / { 12 + compatible = "renesas,r9a09g087m44", "renesas,r9a09g087"; 13 + };

+4 -1

arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi

··· 48 48 #if (SW_SCIF_CAN || SW_RSPI_CAN) 49 49 &canfd { 50 50 pinctrl-0 = <&can1_pins>; 51 - /delete-node/ channel@0; 51 + 52 + channel0 { 53 + status = "disabled"; 54 + }; 52 55 }; 53 56 #else 54 57 &canfd {

+26

arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Common Device Tree Source for the RZ/T2H and RZ/N2H EVK boards. 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + / { 9 + aliases { 10 + i2c0 = &i2c0; 11 + i2c1 = &i2c1; 12 + serial0 = &sci0; 13 + }; 14 + 15 + chosen { 16 + stdout-path = "serial0:115200n8"; 17 + }; 18 + }; 19 + 20 + &extal_clk { 21 + clock-frequency = <25000000>; 22 + }; 23 + 24 + &sci0 { 25 + status = "okay"; 26 + };

+1

include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h

··· 25 25 #define R9A09G077_CLK_PCLKM 13 26 26 #define R9A09G077_CLK_PCLKL 14 27 27 #define R9A09G077_SDHI_CLKHS 15 28 + #define R9A09G077_USB_CLK 16 28 29 29 30 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */

+1

include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h

··· 25 25 #define R9A09G087_CLK_PCLKM 13 26 26 #define R9A09G087_CLK_PCLKL 14 27 27 #define R9A09G087_SDHI_CLKHS 15 28 + #define R9A09G087_USB_CLK 16 28 29 29 30 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */

+22

include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * This header provides constants for Renesas RZ/T2H family pinctrl bindings. 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + #ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ 9 + #define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ 10 + 11 + #define RZT2H_PINS_PER_PORT 8 12 + 13 + /* 14 + * Create the pin index from its bank and position numbers and store in 15 + * the upper 16 bits the alternate function identifier 16 + */ 17 + #define RZT2H_PORT_PINMUX(b, p, f) ((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16)) 18 + 19 + /* Convert a port and pin label to its global pin index */ 20 + #define RZT2H_GPIO(port, pin) ((port) * RZT2H_PINS_PER_PORT + (pin)) 21 + 22 + #endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ */