tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: dts: sunxi: Fix OPP arrays
Even though it translates to the same thing down to the binary level, we
should have an array of 2 number cells to describe each OPP, which in
turns create a validation warning.
Let's fix this.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20210901091852.479202-42-maxime@cerno.tech
+61
-71
+5
-6
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+5
-6
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
···
91
91
/*
92
92
* The A10-Lime is known to be unstable when running at 1008 MHz
93
93
*/
94
-
operating-points = <
95
-
/* kHz uV */
96
-
912000 1350000
97
-
864000 1300000
98
-
624000 1250000
99
-
>;
94
+
operating-points =
95
+
/* kHz uV */
96
+
<912000 1350000>,
97
+
<864000 1300000>,
98
+
<624000 1250000>;
100
99
};
101
100
102
101
&de {
+5
-6
arch/arm/boot/dts/sun4i-a10.dtsi
+5
-6
arch/arm/boot/dts/sun4i-a10.dtsi
···
115
115
reg = <0x0>;
116
116
clocks = <&ccu CLK_CPU>;
117
117
clock-latency = <244144>; /* 8 32k periods */
118
-
operating-points = <
118
+
operating-points =
119
119
/* kHz uV */
120
-
1008000 1400000
121
-
912000 1350000
122
-
864000 1300000
123
-
624000 1250000
124
-
>;
120
+
<1008000 1400000>,
121
+
<912000 1350000>,
122
+
<864000 1300000>,
123
+
<624000 1250000>;
125
124
#cooling-cells = <2>;
126
125
};
127
126
};
+7
-8
arch/arm/boot/dts/sun5i-a13.dtsi
+7
-8
arch/arm/boot/dts/sun5i-a13.dtsi
···
102
102
103
103
&cpu0 {
104
104
clock-latency = <244144>; /* 8 32k periods */
105
-
operating-points = <
105
+
operating-points =
106
106
/* kHz uV */
107
-
1008000 1400000
108
-
912000 1350000
109
-
864000 1300000
110
-
624000 1200000
111
-
576000 1200000
112
-
432000 1200000
113
-
>;
107
+
<1008000 1400000>,
108
+
<912000 1350000>,
109
+
<864000 1300000>,
110
+
<624000 1200000>,
111
+
<576000 1200000>,
112
+
<432000 1200000>;
114
113
#cooling-cells = <2>;
115
114
};
116
115
+20
-24
arch/arm/boot/dts/sun6i-a31.dtsi
+20
-24
arch/arm/boot/dts/sun6i-a31.dtsi
···
105
105
reg = <0>;
106
106
clocks = <&ccu CLK_CPU>;
107
107
clock-latency = <244144>; /* 8 32k periods */
108
-
operating-points = <
108
+
operating-points =
109
109
/* kHz uV */
110
-
1008000 1200000
111
-
864000 1200000
112
-
720000 1100000
113
-
480000 1000000
114
-
>;
110
+
<1008000 1200000>,
111
+
<864000 1200000>,
112
+
<720000 1100000>,
113
+
<480000 1000000>;
115
114
#cooling-cells = <2>;
116
115
};
117
116
···
120
121
reg = <1>;
121
122
clocks = <&ccu CLK_CPU>;
122
123
clock-latency = <244144>; /* 8 32k periods */
123
-
operating-points = <
124
+
operating-points =
124
125
/* kHz uV */
125
-
1008000 1200000
126
-
864000 1200000
127
-
720000 1100000
128
-
480000 1000000
129
-
>;
126
+
<1008000 1200000>,
127
+
<864000 1200000>,
128
+
<720000 1100000>,
129
+
<480000 1000000>;
130
130
#cooling-cells = <2>;
131
131
};
132
132
···
135
137
reg = <2>;
136
138
clocks = <&ccu CLK_CPU>;
137
139
clock-latency = <244144>; /* 8 32k periods */
138
-
operating-points = <
140
+
operating-points =
139
141
/* kHz uV */
140
-
1008000 1200000
141
-
864000 1200000
142
-
720000 1100000
143
-
480000 1000000
144
-
>;
142
+
<1008000 1200000>,
143
+
<864000 1200000>,
144
+
<720000 1100000>,
145
+
<480000 1000000>;
145
146
#cooling-cells = <2>;
146
147
};
147
148
···
150
153
reg = <3>;
151
154
clocks = <&ccu CLK_CPU>;
152
155
clock-latency = <244144>; /* 8 32k periods */
153
-
operating-points = <
156
+
operating-points =
154
157
/* kHz uV */
155
-
1008000 1200000
156
-
864000 1200000
157
-
720000 1100000
158
-
480000 1000000
159
-
>;
158
+
<1008000 1200000>,
159
+
<864000 1200000>,
160
+
<720000 1100000>,
161
+
<480000 1000000>;
160
162
#cooling-cells = <2>;
161
163
};
162
164
};
+8
-9
arch/arm/boot/dts/sun7i-a20-bananapi.dts
+8
-9
arch/arm/boot/dts/sun7i-a20-bananapi.dts
···
104
104
105
105
&cpu0 {
106
106
cpu-supply = <®_dcdc2>;
107
-
operating-points = <
107
+
operating-points =
108
108
/* kHz uV */
109
-
960000 1400000
110
-
912000 1400000
111
-
864000 1350000
112
-
720000 1250000
113
-
528000 1150000
114
-
312000 1100000
115
-
144000 1050000
116
-
>;
109
+
<960000 1400000>,
110
+
<912000 1400000>,
111
+
<864000 1350000>,
112
+
<720000 1250000>,
113
+
<528000 1150000>,
114
+
<312000 1100000>,
115
+
<144000 1050000>;
117
116
};
118
117
119
118
&de {
+16
-18
arch/arm/boot/dts/sun7i-a20.dtsi
+16
-18
arch/arm/boot/dts/sun7i-a20.dtsi
···
106
106
reg = <0>;
107
107
clocks = <&ccu CLK_CPU>;
108
108
clock-latency = <244144>; /* 8 32k periods */
109
-
operating-points = <
109
+
operating-points =
110
110
/* kHz uV */
111
-
960000 1400000
112
-
912000 1400000
113
-
864000 1300000
114
-
720000 1200000
115
-
528000 1100000
116
-
312000 1000000
117
-
144000 1000000
118
-
>;
111
+
<960000 1400000>,
112
+
<912000 1400000>,
113
+
<864000 1300000>,
114
+
<720000 1200000>,
115
+
<528000 1100000>,
116
+
<312000 1000000>,
117
+
<144000 1000000>;
119
118
#cooling-cells = <2>;
120
119
};
121
120
···
124
125
reg = <1>;
125
126
clocks = <&ccu CLK_CPU>;
126
127
clock-latency = <244144>; /* 8 32k periods */
127
-
operating-points = <
128
+
operating-points =
128
129
/* kHz uV */
129
-
960000 1400000
130
-
912000 1400000
131
-
864000 1300000
132
-
720000 1200000
133
-
528000 1100000
134
-
312000 1000000
135
-
144000 1000000
136
-
>;
130
+
<960000 1400000>,
131
+
<912000 1400000>,
132
+
<864000 1300000>,
133
+
<720000 1200000>,
134
+
<528000 1100000>,
135
+
<312000 1000000>,
136
+
<144000 1000000>;
137
137
#cooling-cells = <2>;
138
138
};
139
139
};