dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also
add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
("Register configuration") of the RZ/V2L Hardware User's Manual (Rev.
1.00, Nov. 2021).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220126211003.6675-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by

Geert Uytterhoeven 4 years ago 4decd2e5 e783362e

+229

1 changed file

expand all

include

dt-bindings

clock

r9a07g054-cpg.h

+229

include/dt-bindings/clock/r9a07g054-cpg.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + * 3 + * Copyright (C) 2022 Renesas Electronics Corp. 4 + */ 5 + #ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ 6 + #define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ 7 + 8 + #include <dt-bindings/clock/renesas-cpg-mssr.h> 9 + 10 + /* R9A07G054 CPG Core Clocks */ 11 + #define R9A07G054_CLK_I 0 12 + #define R9A07G054_CLK_I2 1 13 + #define R9A07G054_CLK_G 2 14 + #define R9A07G054_CLK_S0 3 15 + #define R9A07G054_CLK_S1 4 16 + #define R9A07G054_CLK_SPI0 5 17 + #define R9A07G054_CLK_SPI1 6 18 + #define R9A07G054_CLK_SD0 7 19 + #define R9A07G054_CLK_SD1 8 20 + #define R9A07G054_CLK_M0 9 21 + #define R9A07G054_CLK_M1 10 22 + #define R9A07G054_CLK_M2 11 23 + #define R9A07G054_CLK_M3 12 24 + #define R9A07G054_CLK_M4 13 25 + #define R9A07G054_CLK_HP 14 26 + #define R9A07G054_CLK_TSU 15 27 + #define R9A07G054_CLK_ZT 16 28 + #define R9A07G054_CLK_P0 17 29 + #define R9A07G054_CLK_P1 18 30 + #define R9A07G054_CLK_P2 19 31 + #define R9A07G054_CLK_AT 20 32 + #define R9A07G054_OSCCLK 21 33 + #define R9A07G054_CLK_P0_DIV2 22 34 + #define R9A07G054_CLK_DRP_M 23 35 + #define R9A07G054_CLK_DRP_D 24 36 + #define R9A07G054_CLK_DRP_A 25 37 + 38 + /* R9A07G054 Module Clocks */ 39 + #define R9A07G054_CA55_SCLK 0 40 + #define R9A07G054_CA55_PCLK 1 41 + #define R9A07G054_CA55_ATCLK 2 42 + #define R9A07G054_CA55_GICCLK 3 43 + #define R9A07G054_CA55_PERICLK 4 44 + #define R9A07G054_CA55_ACLK 5 45 + #define R9A07G054_CA55_TSCLK 6 46 + #define R9A07G054_GIC600_GICCLK 7 47 + #define R9A07G054_IA55_CLK 8 48 + #define R9A07G054_IA55_PCLK 9 49 + #define R9A07G054_MHU_PCLK 10 50 + #define R9A07G054_SYC_CNT_CLK 11 51 + #define R9A07G054_DMAC_ACLK 12 52 + #define R9A07G054_DMAC_PCLK 13 53 + #define R9A07G054_OSTM0_PCLK 14 54 + #define R9A07G054_OSTM1_PCLK 15 55 + #define R9A07G054_OSTM2_PCLK 16 56 + #define R9A07G054_MTU_X_MCK_MTU3 17 57 + #define R9A07G054_POE3_CLKM_POE 18 58 + #define R9A07G054_GPT_PCLK 19 59 + #define R9A07G054_POEG_A_CLKP 20 60 + #define R9A07G054_POEG_B_CLKP 21 61 + #define R9A07G054_POEG_C_CLKP 22 62 + #define R9A07G054_POEG_D_CLKP 23 63 + #define R9A07G054_WDT0_PCLK 24 64 + #define R9A07G054_WDT0_CLK 25 65 + #define R9A07G054_WDT1_PCLK 26 66 + #define R9A07G054_WDT1_CLK 27 67 + #define R9A07G054_WDT2_PCLK 28 68 + #define R9A07G054_WDT2_CLK 29 69 + #define R9A07G054_SPI_CLK2 30 70 + #define R9A07G054_SPI_CLK 31 71 + #define R9A07G054_SDHI0_IMCLK 32 72 + #define R9A07G054_SDHI0_IMCLK2 33 73 + #define R9A07G054_SDHI0_CLK_HS 34 74 + #define R9A07G054_SDHI0_ACLK 35 75 + #define R9A07G054_SDHI1_IMCLK 36 76 + #define R9A07G054_SDHI1_IMCLK2 37 77 + #define R9A07G054_SDHI1_CLK_HS 38 78 + #define R9A07G054_SDHI1_ACLK 39 79 + #define R9A07G054_GPU_CLK 40 80 + #define R9A07G054_GPU_AXI_CLK 41 81 + #define R9A07G054_GPU_ACE_CLK 42 82 + #define R9A07G054_ISU_ACLK 43 83 + #define R9A07G054_ISU_PCLK 44 84 + #define R9A07G054_H264_CLK_A 45 85 + #define R9A07G054_H264_CLK_P 46 86 + #define R9A07G054_CRU_SYSCLK 47 87 + #define R9A07G054_CRU_VCLK 48 88 + #define R9A07G054_CRU_PCLK 49 89 + #define R9A07G054_CRU_ACLK 50 90 + #define R9A07G054_MIPI_DSI_PLLCLK 51 91 + #define R9A07G054_MIPI_DSI_SYSCLK 52 92 + #define R9A07G054_MIPI_DSI_ACLK 53 93 + #define R9A07G054_MIPI_DSI_PCLK 54 94 + #define R9A07G054_MIPI_DSI_VCLK 55 95 + #define R9A07G054_MIPI_DSI_LPCLK 56 96 + #define R9A07G054_LCDC_CLK_A 57 97 + #define R9A07G054_LCDC_CLK_P 58 98 + #define R9A07G054_LCDC_CLK_D 59 99 + #define R9A07G054_SSI0_PCLK2 60 100 + #define R9A07G054_SSI0_PCLK_SFR 61 101 + #define R9A07G054_SSI1_PCLK2 62 102 + #define R9A07G054_SSI1_PCLK_SFR 63 103 + #define R9A07G054_SSI2_PCLK2 64 104 + #define R9A07G054_SSI2_PCLK_SFR 65 105 + #define R9A07G054_SSI3_PCLK2 66 106 + #define R9A07G054_SSI3_PCLK_SFR 67 107 + #define R9A07G054_SRC_CLKP 68 108 + #define R9A07G054_USB_U2H0_HCLK 69 109 + #define R9A07G054_USB_U2H1_HCLK 70 110 + #define R9A07G054_USB_U2P_EXR_CPUCLK 71 111 + #define R9A07G054_USB_PCLK 72 112 + #define R9A07G054_ETH0_CLK_AXI 73 113 + #define R9A07G054_ETH0_CLK_CHI 74 114 + #define R9A07G054_ETH1_CLK_AXI 75 115 + #define R9A07G054_ETH1_CLK_CHI 76 116 + #define R9A07G054_I2C0_PCLK 77 117 + #define R9A07G054_I2C1_PCLK 78 118 + #define R9A07G054_I2C2_PCLK 79 119 + #define R9A07G054_I2C3_PCLK 80 120 + #define R9A07G054_SCIF0_CLK_PCK 81 121 + #define R9A07G054_SCIF1_CLK_PCK 82 122 + #define R9A07G054_SCIF2_CLK_PCK 83 123 + #define R9A07G054_SCIF3_CLK_PCK 84 124 + #define R9A07G054_SCIF4_CLK_PCK 85 125 + #define R9A07G054_SCI0_CLKP 86 126 + #define R9A07G054_SCI1_CLKP 87 127 + #define R9A07G054_IRDA_CLKP 88 128 + #define R9A07G054_RSPI0_CLKB 89 129 + #define R9A07G054_RSPI1_CLKB 90 130 + #define R9A07G054_RSPI2_CLKB 91 131 + #define R9A07G054_CANFD_PCLK 92 132 + #define R9A07G054_GPIO_HCLK 93 133 + #define R9A07G054_ADC_ADCLK 94 134 + #define R9A07G054_ADC_PCLK 95 135 + #define R9A07G054_TSU_PCLK 96 136 + #define R9A07G054_STPAI_INITCLK 97 137 + #define R9A07G054_STPAI_ACLK 98 138 + #define R9A07G054_STPAI_MCLK 99 139 + #define R9A07G054_STPAI_DCLKIN 100 140 + #define R9A07G054_STPAI_ACLK_DRP 101 141 + 142 + /* R9A07G054 Resets */ 143 + #define R9A07G054_CA55_RST_1_0 0 144 + #define R9A07G054_CA55_RST_1_1 1 145 + #define R9A07G054_CA55_RST_3_0 2 146 + #define R9A07G054_CA55_RST_3_1 3 147 + #define R9A07G054_CA55_RST_4 4 148 + #define R9A07G054_CA55_RST_5 5 149 + #define R9A07G054_CA55_RST_6 6 150 + #define R9A07G054_CA55_RST_7 7 151 + #define R9A07G054_CA55_RST_8 8 152 + #define R9A07G054_CA55_RST_9 9 153 + #define R9A07G054_CA55_RST_10 10 154 + #define R9A07G054_CA55_RST_11 11 155 + #define R9A07G054_CA55_RST_12 12 156 + #define R9A07G054_GIC600_GICRESET_N 13 157 + #define R9A07G054_GIC600_DBG_GICRESET_N 14 158 + #define R9A07G054_IA55_RESETN 15 159 + #define R9A07G054_MHU_RESETN 16 160 + #define R9A07G054_DMAC_ARESETN 17 161 + #define R9A07G054_DMAC_RST_ASYNC 18 162 + #define R9A07G054_SYC_RESETN 19 163 + #define R9A07G054_OSTM0_PRESETZ 20 164 + #define R9A07G054_OSTM1_PRESETZ 21 165 + #define R9A07G054_OSTM2_PRESETZ 22 166 + #define R9A07G054_MTU_X_PRESET_MTU3 23 167 + #define R9A07G054_POE3_RST_M_REG 24 168 + #define R9A07G054_GPT_RST_C 25 169 + #define R9A07G054_POEG_A_RST 26 170 + #define R9A07G054_POEG_B_RST 27 171 + #define R9A07G054_POEG_C_RST 28 172 + #define R9A07G054_POEG_D_RST 29 173 + #define R9A07G054_WDT0_PRESETN 30 174 + #define R9A07G054_WDT1_PRESETN 31 175 + #define R9A07G054_WDT2_PRESETN 32 176 + #define R9A07G054_SPI_RST 33 177 + #define R9A07G054_SDHI0_IXRST 34 178 + #define R9A07G054_SDHI1_IXRST 35 179 + #define R9A07G054_GPU_RESETN 36 180 + #define R9A07G054_GPU_AXI_RESETN 37 181 + #define R9A07G054_GPU_ACE_RESETN 38 182 + #define R9A07G054_ISU_ARESETN 39 183 + #define R9A07G054_ISU_PRESETN 40 184 + #define R9A07G054_H264_X_RESET_VCP 41 185 + #define R9A07G054_H264_CP_PRESET_P 42 186 + #define R9A07G054_CRU_CMN_RSTB 43 187 + #define R9A07G054_CRU_PRESETN 44 188 + #define R9A07G054_CRU_ARESETN 45 189 + #define R9A07G054_MIPI_DSI_CMN_RSTB 46 190 + #define R9A07G054_MIPI_DSI_ARESET_N 47 191 + #define R9A07G054_MIPI_DSI_PRESET_N 48 192 + #define R9A07G054_LCDC_RESET_N 49 193 + #define R9A07G054_SSI0_RST_M2_REG 50 194 + #define R9A07G054_SSI1_RST_M2_REG 51 195 + #define R9A07G054_SSI2_RST_M2_REG 52 196 + #define R9A07G054_SSI3_RST_M2_REG 53 197 + #define R9A07G054_SRC_RST 54 198 + #define R9A07G054_USB_U2H0_HRESETN 55 199 + #define R9A07G054_USB_U2H1_HRESETN 56 200 + #define R9A07G054_USB_U2P_EXL_SYSRST 57 201 + #define R9A07G054_USB_PRESETN 58 202 + #define R9A07G054_ETH0_RST_HW_N 59 203 + #define R9A07G054_ETH1_RST_HW_N 60 204 + #define R9A07G054_I2C0_MRST 61 205 + #define R9A07G054_I2C1_MRST 62 206 + #define R9A07G054_I2C2_MRST 63 207 + #define R9A07G054_I2C3_MRST 64 208 + #define R9A07G054_SCIF0_RST_SYSTEM_N 65 209 + #define R9A07G054_SCIF1_RST_SYSTEM_N 66 210 + #define R9A07G054_SCIF2_RST_SYSTEM_N 67 211 + #define R9A07G054_SCIF3_RST_SYSTEM_N 68 212 + #define R9A07G054_SCIF4_RST_SYSTEM_N 69 213 + #define R9A07G054_SCI0_RST 70 214 + #define R9A07G054_SCI1_RST 71 215 + #define R9A07G054_IRDA_RST 72 216 + #define R9A07G054_RSPI0_RST 73 217 + #define R9A07G054_RSPI1_RST 74 218 + #define R9A07G054_RSPI2_RST 75 219 + #define R9A07G054_CANFD_RSTP_N 76 220 + #define R9A07G054_CANFD_RSTC_N 77 221 + #define R9A07G054_GPIO_RSTN 78 222 + #define R9A07G054_GPIO_PORT_RESETN 79 223 + #define R9A07G054_GPIO_SPARE_RESETN 80 224 + #define R9A07G054_ADC_PRESETN 81 225 + #define R9A07G054_ADC_ADRST_N 82 226 + #define R9A07G054_TSU_PRESETN 83 227 + #define R9A07G054_STPAI_ARESETN 84 228 + 229 + #endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */