tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: SPEAr: Add plgpio node in device tree dtsi files
This patch adds plgpio nodes in SPEAr DT files.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Viresh Kumar
and committed by
Linus Walleij
4ddb1c29
f4f8e563
+108
-2
+4
arch/arm/boot/dts/spear1310-evb.dts
+4
arch/arm/boot/dts/spear1310-evb.dts
+27
arch/arm/boot/dts/spear1310.dtsi
+27
arch/arm/boot/dts/spear1310.dtsi
···
70
70
status = "disabled";
71
71
};
72
72
73
+
pinmux: pinmux@e0700000 {
74
+
compatible = "st,spear1310-pinmux";
75
+
reg = <0xe0700000 0x1000>;
76
+
#gpio-range-cells = <2>;
77
+
};
78
+
73
79
spi1: spi@5d400000 {
74
80
compatible = "arm,pl022", "arm,primecell";
75
81
reg = <0x5d400000 0x1000>;
···
184
178
185
179
thermal@e07008c4 {
186
180
st,thermal-flags = <0x7000>;
181
+
};
182
+
183
+
gpiopinctrl: gpio@d8400000 {
184
+
compatible = "st,spear-plgpio";
185
+
reg = <0xd8400000 0x1000>;
186
+
interrupts = <0 100 0x4>;
187
+
#interrupt-cells = <1>;
188
+
interrupt-controller;
189
+
gpio-controller;
190
+
#gpio-cells = <2>;
191
+
gpio-ranges = <&pinmux 0 246>;
192
+
status = "disabled";
193
+
194
+
st-plgpio,ngpio = <246>;
195
+
st-plgpio,enb-reg = <0xd0>;
196
+
st-plgpio,wdata-reg = <0x90>;
197
+
st-plgpio,dir-reg = <0xb0>;
198
+
st-plgpio,ie-reg = <0x30>;
199
+
st-plgpio,rdata-reg = <0x70>;
200
+
st-plgpio,mis-reg = <0x10>;
201
+
st-plgpio,eit-reg = <0x50>;
187
202
};
188
203
};
189
204
};
+4
arch/arm/boot/dts/spear1340-evb.dts
+4
arch/arm/boot/dts/spear1340-evb.dts
+26
arch/arm/boot/dts/spear1340.dtsi
+26
arch/arm/boot/dts/spear1340.dtsi
···
24
24
status = "disabled";
25
25
};
26
26
27
+
pinmux: pinmux@e0700000 {
28
+
compatible = "st,spear1340-pinmux";
29
+
reg = <0xe0700000 0x1000>;
30
+
#gpio-range-cells = <2>;
31
+
};
32
+
27
33
spi1: spi@5d400000 {
28
34
compatible = "arm,pl022", "arm,primecell";
29
35
reg = <0x5d400000 0x1000>;
···
56
50
57
51
thermal@e07008c4 {
58
52
st,thermal-flags = <0x2a00>;
53
+
};
54
+
55
+
gpiopinctrl: gpio@e2800000 {
56
+
compatible = "st,spear-plgpio";
57
+
reg = <0xe2800000 0x1000>;
58
+
interrupts = <0 107 0x4>;
59
+
#interrupt-cells = <1>;
60
+
interrupt-controller;
61
+
gpio-controller;
62
+
#gpio-cells = <2>;
63
+
gpio-ranges = <&pinmux 0 252>;
64
+
status = "disabled";
65
+
66
+
st-plgpio,ngpio = <250>;
67
+
st-plgpio,wdata-reg = <0x40>;
68
+
st-plgpio,dir-reg = <0x00>;
69
+
st-plgpio,ie-reg = <0x80>;
70
+
st-plgpio,rdata-reg = <0x20>;
71
+
st-plgpio,mis-reg = <0xa0>;
72
+
st-plgpio,eit-reg = <0x60>;
59
73
};
60
74
};
61
75
};
+21
-1
arch/arm/boot/dts/spear310.dtsi
+21
-1
arch/arm/boot/dts/spear310.dtsi
···
22
22
0xb0000000 0xb0000000 0x10000000
23
23
0xd0000000 0xd0000000 0x30000000>;
24
24
25
-
pinmux@b4000000 {
25
+
pinmux: pinmux@b4000000 {
26
26
compatible = "st,spear310-pinmux";
27
27
reg = <0xb4000000 0x1000>;
28
+
#gpio-range-cells = <2>;
28
29
};
29
30
30
31
fsmc: flash@44000000 {
···
75
74
compatible = "arm,pl011", "arm,primecell";
76
75
reg = <0xb2200000 0x1000>;
77
76
status = "disabled";
77
+
};
78
+
79
+
gpiopinctrl: gpio@b4000000 {
80
+
compatible = "st,spear-plgpio";
81
+
reg = <0xb4000000 0x1000>;
82
+
#interrupt-cells = <1>;
83
+
interrupt-controller;
84
+
gpio-controller;
85
+
#gpio-cells = <2>;
86
+
gpio-ranges = <&pinmux 0 102>;
87
+
status = "disabled";
88
+
89
+
st-plgpio,ngpio = <102>;
90
+
st-plgpio,enb-reg = <0x10>;
91
+
st-plgpio,wdata-reg = <0x20>;
92
+
st-plgpio,dir-reg = <0x30>;
93
+
st-plgpio,ie-reg = <0x50>;
94
+
st-plgpio,rdata-reg = <0x40>;
95
+
st-plgpio,mis-reg = <0x60>;
78
96
};
79
97
};
80
98
};
+4
arch/arm/boot/dts/spear320-evb.dts
+4
arch/arm/boot/dts/spear320-evb.dts
+22
-1
arch/arm/boot/dts/spear320.dtsi
+22
-1
arch/arm/boot/dts/spear320.dtsi
···
21
21
ranges = <0x40000000 0x40000000 0x80000000
22
22
0xd0000000 0xd0000000 0x30000000>;
23
23
24
-
pinmux@b3000000 {
24
+
pinmux: pinmux@b3000000 {
25
25
compatible = "st,spear320-pinmux";
26
26
reg = <0xb3000000 0x1000>;
27
+
#gpio-range-cells = <2>;
27
28
};
28
29
29
30
clcd@90000000 {
···
90
89
compatible = "arm,pl011", "arm,primecell";
91
90
reg = <0xa4000000 0x1000>;
92
91
status = "disabled";
92
+
};
93
+
94
+
gpiopinctrl: gpio@b3000000 {
95
+
compatible = "st,spear-plgpio";
96
+
reg = <0xb3000000 0x1000>;
97
+
#interrupt-cells = <1>;
98
+
interrupt-controller;
99
+
gpio-controller;
100
+
#gpio-cells = <2>;
101
+
gpio-ranges = <&pinmux 0 102>;
102
+
status = "disabled";
103
+
104
+
st-plgpio,ngpio = <102>;
105
+
st-plgpio,enb-reg = <0x24>;
106
+
st-plgpio,wdata-reg = <0x34>;
107
+
st-plgpio,dir-reg = <0x44>;
108
+
st-plgpio,ie-reg = <0x64>;
109
+
st-plgpio,rdata-reg = <0x54>;
110
+
st-plgpio,mis-reg = <0x84>;
111
+
st-plgpio,eit-reg = <0x94>;
93
112
};
94
113
};
95
114
};