tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
irqchip: or1k-pic: Migrate from arch/openrisc/
In addition to consolidating the or1k-pic with other interrupt
controllers, this makes OpenRISC less tied to its on-cpu
interrupt controller.
All or1k-pic specific parts are moved out of irq.c and into
drivers/irqchip/irq-or1k-pic.c
In that transition, the functionality have been divided into
three chip variants.
One that handles level triggered interrupts, one that handles edge
triggered interrupts and one that handles the interrupt
controller that is present in the or1200 OpenRISC cpu
implementation.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Link: https://lkml.kernel.org/r/1401136302-27654-1-git-send-email-stefan.kristiansson@saunalahti.fi
Acked-by: Jonas Bonn <jonas@southpole.se>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
authored by
Stefan Kristiansson
and committed by
Jason Cooper
4db8e6d2
1b0a76c1
+230
-136
+23
Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt
+23
Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt
···
1
+
OpenRISC 1000 Programmable Interrupt Controller
2
+
3
+
Required properties:
4
+
5
+
- compatible : should be "opencores,or1k-pic-level" for variants with
6
+
level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
7
+
edge triggered interrupt lines or "opencores,or1200-pic" for machines
8
+
with the non-spec compliant or1200 type implementation.
9
+
10
+
"opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
11
+
but this is only for backwards compatibility.
12
+
13
+
- interrupt-controller : Identifies the node as an interrupt controller
14
+
- #interrupt-cells : Specifies the number of cells needed to encode an
15
+
interrupt source. The value shall be 1.
16
+
17
+
Example:
18
+
19
+
intc: interrupt-controller {
20
+
compatible = "opencores,or1k-pic-level";
21
+
interrupt-controller;
22
+
#interrupt-cells = <1>;
23
+
};
+1
arch/openrisc/Kconfig
+1
arch/openrisc/Kconfig
+3
arch/openrisc/include/asm/irq.h
+3
arch/openrisc/include/asm/irq.h
+16
-136
arch/openrisc/kernel/irq.c
+16
-136
arch/openrisc/kernel/irq.c
···
16
16
17
17
#include <linux/interrupt.h>
18
18
#include <linux/init.h>
19
-
#include <linux/of.h>
20
19
#include <linux/ftrace.h>
21
20
#include <linux/irq.h>
21
+
#include <linux/irqchip.h>
22
22
#include <linux/export.h>
23
-
#include <linux/irqdomain.h>
24
23
#include <linux/irqflags.h>
25
24
26
25
/* read interrupt enabled status */
···
36
37
}
37
38
EXPORT_SYMBOL(arch_local_irq_restore);
38
39
39
-
40
-
/* OR1K PIC implementation */
41
-
42
-
/* We're a couple of cycles faster than the generic implementations with
43
-
* these 'fast' versions.
44
-
*/
45
-
46
-
static void or1k_pic_mask(struct irq_data *data)
47
-
{
48
-
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
49
-
}
50
-
51
-
static void or1k_pic_unmask(struct irq_data *data)
52
-
{
53
-
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));
54
-
}
55
-
56
-
static void or1k_pic_ack(struct irq_data *data)
57
-
{
58
-
/* EDGE-triggered interrupts need to be ack'ed in order to clear
59
-
* the latch.
60
-
* LEVEL-triggered interrupts do not need to be ack'ed; however,
61
-
* ack'ing the interrupt has no ill-effect and is quicker than
62
-
* trying to figure out what type it is...
63
-
*/
64
-
65
-
/* The OpenRISC 1000 spec says to write a 1 to the bit to ack the
66
-
* interrupt, but the OR1200 does this backwards and requires a 0
67
-
* to be written...
68
-
*/
69
-
70
-
#ifdef CONFIG_OR1K_1200
71
-
/* There are two oddities with the OR1200 PIC implementation:
72
-
* i) LEVEL-triggered interrupts are latched and need to be cleared
73
-
* ii) the interrupt latch is cleared by writing a 0 to the bit,
74
-
* as opposed to a 1 as mandated by the spec
75
-
*/
76
-
77
-
mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
78
-
#else
79
-
WARN(1, "Interrupt handling possibly broken\n");
80
-
mtspr(SPR_PICSR, (1UL << data->hwirq));
81
-
#endif
82
-
}
83
-
84
-
static void or1k_pic_mask_ack(struct irq_data *data)
85
-
{
86
-
/* Comments for pic_ack apply here, too */
87
-
88
-
#ifdef CONFIG_OR1K_1200
89
-
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
90
-
mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
91
-
#else
92
-
WARN(1, "Interrupt handling possibly broken\n");
93
-
mtspr(SPR_PICMR, (1UL << data->hwirq));
94
-
mtspr(SPR_PICSR, (1UL << data->hwirq));
95
-
#endif
96
-
}
97
-
98
-
#if 0
99
-
static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type)
100
-
{
101
-
/* There's nothing to do in the PIC configuration when changing
102
-
* flow type. Level and edge-triggered interrupts are both
103
-
* supported, but it's PIC-implementation specific which type
104
-
* is handled. */
105
-
106
-
return irq_setup_alt_chip(data, flow_type);
107
-
}
108
-
#endif
109
-
110
-
static struct irq_chip or1k_dev = {
111
-
.name = "or1k-PIC",
112
-
.irq_unmask = or1k_pic_unmask,
113
-
.irq_mask = or1k_pic_mask,
114
-
.irq_ack = or1k_pic_ack,
115
-
.irq_mask_ack = or1k_pic_mask_ack,
116
-
};
117
-
118
-
static struct irq_domain *root_domain;
119
-
120
-
static inline int pic_get_irq(int first)
121
-
{
122
-
int hwirq;
123
-
124
-
hwirq = ffs(mfspr(SPR_PICSR) >> first);
125
-
if (!hwirq)
126
-
return NO_IRQ;
127
-
else
128
-
hwirq = hwirq + first -1;
129
-
130
-
return irq_find_mapping(root_domain, hwirq);
131
-
}
132
-
133
-
134
-
static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
135
-
{
136
-
irq_set_chip_and_handler_name(irq, &or1k_dev,
137
-
handle_level_irq, "level");
138
-
irq_set_status_flags(irq, IRQ_LEVEL | IRQ_NOPROBE);
139
-
140
-
return 0;
141
-
}
142
-
143
-
static const struct irq_domain_ops or1k_irq_domain_ops = {
144
-
.xlate = irq_domain_xlate_onecell,
145
-
.map = or1k_map,
146
-
};
147
-
148
-
/*
149
-
* This sets up the IRQ domain for the PIC built in to the OpenRISC
150
-
* 1000 CPU. This is the "root" domain as these are the interrupts
151
-
* that directly trigger an exception in the CPU.
152
-
*/
153
-
static void __init or1k_irq_init(void)
154
-
{
155
-
struct device_node *intc = NULL;
156
-
157
-
/* The interrupt controller device node is mandatory */
158
-
intc = of_find_compatible_node(NULL, NULL, "opencores,or1k-pic");
159
-
BUG_ON(!intc);
160
-
161
-
/* Disable all interrupts until explicitly requested */
162
-
mtspr(SPR_PICMR, (0UL));
163
-
164
-
root_domain = irq_domain_add_linear(intc, 32,
165
-
&or1k_irq_domain_ops, NULL);
166
-
}
167
-
168
40
void __init init_IRQ(void)
169
41
{
170
-
or1k_irq_init();
42
+
irqchip_init();
171
43
}
172
44
173
-
void __irq_entry do_IRQ(struct pt_regs *regs)
45
+
static void (*handle_arch_irq)(struct pt_regs *);
46
+
47
+
void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
174
48
{
175
-
int irq = -1;
49
+
handle_arch_irq = handle_irq;
50
+
}
51
+
52
+
void handle_IRQ(unsigned int irq, struct pt_regs *regs)
53
+
{
176
54
struct pt_regs *old_regs = set_irq_regs(regs);
177
55
178
56
irq_enter();
179
57
180
-
while ((irq = pic_get_irq(irq + 1)) != NO_IRQ)
181
-
generic_handle_irq(irq);
58
+
generic_handle_irq(irq);
182
59
183
60
irq_exit();
184
61
set_irq_regs(old_regs);
62
+
}
63
+
64
+
void __irq_entry do_IRQ(struct pt_regs *regs)
65
+
{
66
+
handle_arch_irq(regs);
185
67
}
+4
drivers/irqchip/Kconfig
+4
drivers/irqchip/Kconfig
+1
drivers/irqchip/Makefile
+1
drivers/irqchip/Makefile
···
11
11
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
12
12
obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o
13
13
obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
14
+
obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
14
15
obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
15
16
obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
16
17
obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
+182
drivers/irqchip/irq-or1k-pic.c
+182
drivers/irqchip/irq-or1k-pic.c
···
1
+
/*
2
+
* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
3
+
* Copyright (C) 2014 Stefan Kristansson <stefan.kristiansson@saunalahti.fi>
4
+
*
5
+
* This program is free software; you can redistribute it and/or
6
+
* modify it under the terms of the GNU General Public License
7
+
* as published by the Free Software Foundation; either version
8
+
* 2 of the License, or (at your option) any later version.
9
+
*/
10
+
11
+
#include <linux/irq.h>
12
+
#include <linux/of.h>
13
+
#include <linux/of_irq.h>
14
+
#include <linux/of_address.h>
15
+
16
+
#include "irqchip.h"
17
+
18
+
/* OR1K PIC implementation */
19
+
20
+
struct or1k_pic_dev {
21
+
struct irq_chip chip;
22
+
irq_flow_handler_t handle;
23
+
unsigned long flags;
24
+
};
25
+
26
+
/*
27
+
* We're a couple of cycles faster than the generic implementations with
28
+
* these 'fast' versions.
29
+
*/
30
+
31
+
static void or1k_pic_mask(struct irq_data *data)
32
+
{
33
+
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
34
+
}
35
+
36
+
static void or1k_pic_unmask(struct irq_data *data)
37
+
{
38
+
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));
39
+
}
40
+
41
+
static void or1k_pic_ack(struct irq_data *data)
42
+
{
43
+
mtspr(SPR_PICSR, (1UL << data->hwirq));
44
+
}
45
+
46
+
static void or1k_pic_mask_ack(struct irq_data *data)
47
+
{
48
+
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
49
+
mtspr(SPR_PICSR, (1UL << data->hwirq));
50
+
}
51
+
52
+
/*
53
+
* There are two oddities with the OR1200 PIC implementation:
54
+
* i) LEVEL-triggered interrupts are latched and need to be cleared
55
+
* ii) the interrupt latch is cleared by writing a 0 to the bit,
56
+
* as opposed to a 1 as mandated by the spec
57
+
*/
58
+
static void or1k_pic_or1200_ack(struct irq_data *data)
59
+
{
60
+
mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
61
+
}
62
+
63
+
static void or1k_pic_or1200_mask_ack(struct irq_data *data)
64
+
{
65
+
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
66
+
mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
67
+
}
68
+
69
+
static struct or1k_pic_dev or1k_pic_level = {
70
+
.chip = {
71
+
.name = "or1k-PIC-level",
72
+
.irq_unmask = or1k_pic_unmask,
73
+
.irq_mask = or1k_pic_mask,
74
+
.irq_mask_ack = or1k_pic_mask,
75
+
},
76
+
.handle = handle_level_irq,
77
+
.flags = IRQ_LEVEL | IRQ_NOPROBE,
78
+
};
79
+
80
+
static struct or1k_pic_dev or1k_pic_edge = {
81
+
.chip = {
82
+
.name = "or1k-PIC-edge",
83
+
.irq_unmask = or1k_pic_unmask,
84
+
.irq_mask = or1k_pic_mask,
85
+
.irq_ack = or1k_pic_ack,
86
+
.irq_mask_ack = or1k_pic_mask_ack,
87
+
},
88
+
.handle = handle_edge_irq,
89
+
.flags = IRQ_LEVEL | IRQ_NOPROBE,
90
+
};
91
+
92
+
static struct or1k_pic_dev or1k_pic_or1200 = {
93
+
.chip = {
94
+
.name = "or1200-PIC",
95
+
.irq_unmask = or1k_pic_unmask,
96
+
.irq_mask = or1k_pic_mask,
97
+
.irq_ack = or1k_pic_or1200_ack,
98
+
.irq_mask_ack = or1k_pic_or1200_mask_ack,
99
+
},
100
+
.handle = handle_level_irq,
101
+
.flags = IRQ_LEVEL | IRQ_NOPROBE,
102
+
};
103
+
104
+
static struct irq_domain *root_domain;
105
+
106
+
static inline int pic_get_irq(int first)
107
+
{
108
+
int hwirq;
109
+
110
+
hwirq = ffs(mfspr(SPR_PICSR) >> first);
111
+
if (!hwirq)
112
+
return NO_IRQ;
113
+
else
114
+
hwirq = hwirq + first - 1;
115
+
116
+
return irq_find_mapping(root_domain, hwirq);
117
+
}
118
+
119
+
static void or1k_pic_handle_irq(struct pt_regs *regs)
120
+
{
121
+
int irq = -1;
122
+
123
+
while ((irq = pic_get_irq(irq + 1)) != NO_IRQ)
124
+
handle_IRQ(irq, regs);
125
+
}
126
+
127
+
static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
128
+
{
129
+
struct or1k_pic_dev *pic = d->host_data;
130
+
131
+
irq_set_chip_and_handler(irq, &pic->chip, pic->handle);
132
+
irq_set_status_flags(irq, pic->flags);
133
+
134
+
return 0;
135
+
}
136
+
137
+
static const struct irq_domain_ops or1k_irq_domain_ops = {
138
+
.xlate = irq_domain_xlate_onecell,
139
+
.map = or1k_map,
140
+
};
141
+
142
+
/*
143
+
* This sets up the IRQ domain for the PIC built in to the OpenRISC
144
+
* 1000 CPU. This is the "root" domain as these are the interrupts
145
+
* that directly trigger an exception in the CPU.
146
+
*/
147
+
static int __init or1k_pic_init(struct device_node *node,
148
+
struct or1k_pic_dev *pic)
149
+
{
150
+
/* Disable all interrupts until explicitly requested */
151
+
mtspr(SPR_PICMR, (0UL));
152
+
153
+
root_domain = irq_domain_add_linear(node, 32, &or1k_irq_domain_ops,
154
+
pic);
155
+
156
+
set_handle_irq(or1k_pic_handle_irq);
157
+
158
+
return 0;
159
+
}
160
+
161
+
static int __init or1k_pic_or1200_init(struct device_node *node,
162
+
struct device_node *parent)
163
+
{
164
+
return or1k_pic_init(node, &or1k_pic_or1200);
165
+
}
166
+
IRQCHIP_DECLARE(or1k_pic_or1200, "opencores,or1200-pic", or1k_pic_or1200_init);
167
+
IRQCHIP_DECLARE(or1k_pic, "opencores,or1k-pic", or1k_pic_or1200_init);
168
+
169
+
static int __init or1k_pic_level_init(struct device_node *node,
170
+
struct device_node *parent)
171
+
{
172
+
return or1k_pic_init(node, &or1k_pic_level);
173
+
}
174
+
IRQCHIP_DECLARE(or1k_pic_level, "opencores,or1k-pic-level",
175
+
or1k_pic_level_init);
176
+
177
+
static int __init or1k_pic_edge_init(struct device_node *node,
178
+
struct device_node *parent)
179
+
{
180
+
return or1k_pic_init(node, &or1k_pic_edge);
181
+
}
182
+
IRQCHIP_DECLARE(or1k_pic_edge, "opencores,or1k-pic-edge", or1k_pic_edge_init);