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dt-bindings: microchip-otpc: document Microchip OTPC

Document Microchip OTP controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220706100627.6534-2-srinivas.kandagatla@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Claudiu Beznea and committed by
Greg Kroah-Hartman
4d5e3b06 b7e241bb

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Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Microchip SAMA7G5 OTP Controller (OTPC) 8 + 9 + maintainers: 10 + - Claudiu Beznea <claudiu.beznea@microchip.com> 11 + 12 + description: | 13 + OTP controller drives a NVMEM memory where system specific data 14 + (e.g. calibration data for analog cells, hardware configuration 15 + settings, chip identifiers) or user specific data could be stored. 16 + 17 + allOf: 18 + - $ref: "nvmem.yaml#" 19 + 20 + properties: 21 + compatible: 22 + items: 23 + - const: microchip,sama7g5-otpc 24 + - const: syscon 25 + 26 + reg: 27 + maxItems: 1 28 + 29 + required: 30 + - compatible 31 + - reg 32 + 33 + unevaluatedProperties: false 34 + 35 + examples: 36 + - | 37 + #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h> 38 + 39 + otpc: efuse@e8c00000 { 40 + compatible = "microchip,sama7g5-otpc", "syscon"; 41 + reg = <0xe8c00000 0xec>; 42 + #address-cells = <1>; 43 + #size-cells = <1>; 44 + 45 + temperature_calib: calib@1 { 46 + reg = <OTP_PKT(1) 76>; 47 + }; 48 + }; 49 + 50 + ...
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include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 + 3 + #ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H 4 + #define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H 5 + 6 + /* 7 + * Need to have it as a multiple of 4 as NVMEM memory is registered with 8 + * stride = 4. 9 + */ 10 + #define OTP_PKT(id) ((id) * 4) 11 + 12 + #endif