video: da8xx-fb: preserve display width when changing HSYNC

When looking at this driver for a client, I noticed the code that
configures the HSYNC pulse clobbers the display width in the same
register. It only preserves the MS part of the width in bit 3 and zeros
the LS part of the width in bits 9 to 4. This doesn't matter during
initialization as the width is configured afterwards, but subsequent use
of the FBIPUT_HSYNC ioctl would clobber the width.

Preserve bits 9 to 0 of LCD_RASTER_TIMING_0_REG when configuring the
horizontal sync.

Signed-off-by: Ian Abbott <[e-mail]>
Signed-off-by: Tomi Valkeinen <[e-mail]>

drivers/video/fbdev/da8xx-fb.c

···
 {
 	u32 reg;
 
-	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
+	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
 	reg |= (((back_porch-1) & 0xff) << 24)
 	    | (((front_porch-1) & 0xff) << 16)
 	    | (((pulse_width-1) & 0x3f) << 10);