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dt-bindings: timer: Convert ARM timer bindings to json-schema
Convert ARM timers to DT schema format using json-schema.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
+269
-139
-112
Documentation/devicetree/bindings/timer/arm,arch_timer.txt
-112
Documentation/devicetree/bindings/timer/arm,arch_timer.txt
···
1
-
* ARM architected timer
2
-
3
-
ARM cores may have a per-core architected timer, which provides per-cpu timers,
4
-
or a memory mapped architected timer, which provides up to 8 frames with a
5
-
physical and optional virtual timer per frame.
6
-
7
-
The per-core architected timer is attached to a GIC to deliver its
8
-
per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
9
-
to deliver its interrupts via SPIs.
10
-
11
-
** CP15 Timer node properties:
12
-
13
-
- compatible : Should at least contain one of
14
-
"arm,armv7-timer"
15
-
"arm,armv8-timer"
16
-
17
-
- interrupts : Interrupt list for secure, non-secure, virtual and
18
-
hypervisor timers, in that order.
19
-
20
-
- clock-frequency : The frequency of the main counter, in Hz. Should be present
21
-
only where necessary to work around broken firmware which does not configure
22
-
CNTFRQ on all CPUs to a uniform correct value. Use of this property is
23
-
strongly discouraged; fix your firmware unless absolutely impossible.
24
-
25
-
- always-on : a boolean property. If present, the timer is powered through an
26
-
always-on power domain, therefore it never loses context.
27
-
28
-
- fsl,erratum-a008585 : A boolean property. Indicates the presence of
29
-
QorIQ erratum A-008585, which says that reading the counter is
30
-
unreliable unless the same value is returned by back-to-back reads.
31
-
This also affects writes to the tval register, due to the implicit
32
-
counter read.
33
-
34
-
- hisilicon,erratum-161010101 : A boolean property. Indicates the
35
-
presence of Hisilicon erratum 161010101, which says that reading the
36
-
counters is unreliable in some cases, and reads may return a value 32
37
-
beyond the correct value. This also affects writes to the tval
38
-
registers, due to the implicit counter read.
39
-
40
-
** Optional properties:
41
-
42
-
- arm,cpu-registers-not-fw-configured : Firmware does not initialize
43
-
any of the generic timer CPU registers, which contain their
44
-
architecturally-defined reset values. Only supported for 32-bit
45
-
systems which follow the ARMv7 architected reset values.
46
-
47
-
- arm,no-tick-in-suspend : The main counter does not tick when the system is in
48
-
low-power system suspend on some SoCs. This behavior does not match the
49
-
Architecture Reference Manual's specification that the system counter "must
50
-
be implemented in an always-on power domain."
51
-
52
-
53
-
Example:
54
-
55
-
timer {
56
-
compatible = "arm,cortex-a15-timer",
57
-
"arm,armv7-timer";
58
-
interrupts = <1 13 0xf08>,
59
-
<1 14 0xf08>,
60
-
<1 11 0xf08>,
61
-
<1 10 0xf08>;
62
-
clock-frequency = <100000000>;
63
-
};
64
-
65
-
** Memory mapped timer node properties:
66
-
67
-
- compatible : Should at least contain "arm,armv7-timer-mem".
68
-
69
-
- clock-frequency : The frequency of the main counter, in Hz. Should be present
70
-
only when firmware has not configured the MMIO CNTFRQ registers.
71
-
72
-
- reg : The control frame base address.
73
-
74
-
Note that #address-cells, #size-cells, and ranges shall be present to ensure
75
-
the CPU can address a frame's registers.
76
-
77
-
A timer node has up to 8 frame sub-nodes, each with the following properties:
78
-
79
-
- frame-number: 0 to 7.
80
-
81
-
- interrupts : Interrupt list for physical and virtual timers in that order.
82
-
The virtual timer interrupt is optional.
83
-
84
-
- reg : The first and second view base addresses in that order. The second view
85
-
base address is optional.
86
-
87
-
- status : "disabled" indicates the frame is not available for use. Optional.
88
-
89
-
Example:
90
-
91
-
timer@f0000000 {
92
-
compatible = "arm,armv7-timer-mem";
93
-
#address-cells = <1>;
94
-
#size-cells = <1>;
95
-
ranges;
96
-
reg = <0xf0000000 0x1000>;
97
-
clock-frequency = <50000000>;
98
-
99
-
frame@f0001000 {
100
-
frame-number = <0>
101
-
interrupts = <0 13 0x8>,
102
-
<0 14 0x8>;
103
-
reg = <0xf0001000 0x1000>,
104
-
<0xf0002000 0x1000>;
105
-
};
106
-
107
-
frame@f0003000 {
108
-
frame-number = <1>
109
-
interrupts = <0 15 0x8>;
110
-
reg = <0xf0003000 0x1000>;
111
-
};
112
-
};
+103
Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
+103
Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ARM architected timer
8
+
9
+
maintainers:
10
+
- Marc Zyngier <marc.zyngier@arm.com>
11
+
- Mark Rutland <mark.rutland@arm.com>
12
+
description: |+
13
+
ARM cores may have a per-core architected timer, which provides per-cpu timers,
14
+
or a memory mapped architected timer, which provides up to 8 frames with a
15
+
physical and optional virtual timer per frame.
16
+
17
+
The per-core architected timer is attached to a GIC to deliver its
18
+
per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
19
+
to deliver its interrupts via SPIs.
20
+
21
+
properties:
22
+
compatible:
23
+
oneOf:
24
+
- items:
25
+
- enum:
26
+
- arm,cortex-a15-timer
27
+
- enum:
28
+
- arm,armv7-timer
29
+
- items:
30
+
- enum:
31
+
- arm,armv7-timer
32
+
- items:
33
+
- enum:
34
+
- arm,armv8-timer
35
+
36
+
interrupts:
37
+
items:
38
+
- description: secure timer irq
39
+
- description: non-secure timer irq
40
+
- description: virtual timer irq
41
+
- description: hypervisor timer irq
42
+
43
+
clock-frequency:
44
+
description: The frequency of the main counter, in Hz. Should be present
45
+
only where necessary to work around broken firmware which does not configure
46
+
CNTFRQ on all CPUs to a uniform correct value. Use of this property is
47
+
strongly discouraged; fix your firmware unless absolutely impossible.
48
+
49
+
always-on:
50
+
type: boolean
51
+
description: If present, the timer is powered through an always-on power
52
+
domain, therefore it never loses context.
53
+
54
+
fsl,erratum-a008585:
55
+
type: boolean
56
+
description: Indicates the presence of QorIQ erratum A-008585, which says
57
+
that reading the counter is unreliable unless the same value is returned
58
+
by back-to-back reads. This also affects writes to the tval register, due
59
+
to the implicit counter read.
60
+
61
+
hisilicon,erratum-161010101:
62
+
type: boolean
63
+
description: Indicates the presence of Hisilicon erratum 161010101, which
64
+
says that reading the counters is unreliable in some cases, and reads may
65
+
return a value 32 beyond the correct value. This also affects writes to
66
+
the tval registers, due to the implicit counter read.
67
+
68
+
arm,cpu-registers-not-fw-configured:
69
+
type: boolean
70
+
description: Firmware does not initialize any of the generic timer CPU
71
+
registers, which contain their architecturally-defined reset values. Only
72
+
supported for 32-bit systems which follow the ARMv7 architected reset
73
+
values.
74
+
75
+
arm,no-tick-in-suspend:
76
+
type: boolean
77
+
description: The main counter does not tick when the system is in
78
+
low-power system suspend on some SoCs. This behavior does not match the
79
+
Architecture Reference Manual's specification that the system counter "must
80
+
be implemented in an always-on power domain."
81
+
82
+
required:
83
+
- compatible
84
+
85
+
oneOf:
86
+
- required:
87
+
- interrupts
88
+
- required:
89
+
- interrupts-extended
90
+
91
+
examples:
92
+
- |
93
+
timer {
94
+
compatible = "arm,cortex-a15-timer",
95
+
"arm,armv7-timer";
96
+
interrupts = <1 13 0xf08>,
97
+
<1 14 0xf08>,
98
+
<1 11 0xf08>,
99
+
<1 10 0xf08>;
100
+
clock-frequency = <100000000>;
101
+
};
102
+
103
+
...
+120
Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
+120
Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ARM memory mapped architected timer
8
+
9
+
maintainers:
10
+
- Marc Zyngier <marc.zyngier@arm.com>
11
+
- Mark Rutland <mark.rutland@arm.com>
12
+
13
+
description: |+
14
+
ARM cores may have a memory mapped architected timer, which provides up to 8
15
+
frames with a physical and optional virtual timer per frame.
16
+
17
+
The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
18
+
19
+
properties:
20
+
compatible:
21
+
items:
22
+
- enum:
23
+
- arm,armv7-timer-mem
24
+
25
+
reg:
26
+
maxItems: 1
27
+
description: The control frame base address
28
+
29
+
'#address-cells':
30
+
enum: [1, 2]
31
+
32
+
'#size-cells':
33
+
const: 1
34
+
35
+
clock-frequency:
36
+
description: The frequency of the main counter, in Hz. Should be present
37
+
only where necessary to work around broken firmware which does not configure
38
+
CNTFRQ on all CPUs to a uniform correct value. Use of this property is
39
+
strongly discouraged; fix your firmware unless absolutely impossible.
40
+
41
+
always-on:
42
+
type: boolean
43
+
description: If present, the timer is powered through an always-on power
44
+
domain, therefore it never loses context.
45
+
46
+
arm,cpu-registers-not-fw-configured:
47
+
type: boolean
48
+
description: Firmware does not initialize any of the generic timer CPU
49
+
registers, which contain their architecturally-defined reset values. Only
50
+
supported for 32-bit systems which follow the ARMv7 architected reset
51
+
values.
52
+
53
+
arm,no-tick-in-suspend:
54
+
type: boolean
55
+
description: The main counter does not tick when the system is in
56
+
low-power system suspend on some SoCs. This behavior does not match the
57
+
Architecture Reference Manual's specification that the system counter "must
58
+
be implemented in an always-on power domain."
59
+
60
+
patternProperties:
61
+
'^frame@[0-9a-z]*$':
62
+
description: A timer node has up to 8 frame sub-nodes, each with the following properties.
63
+
properties:
64
+
frame-number:
65
+
allOf:
66
+
- $ref: "/schemas/types.yaml#/definitions/uint32"
67
+
- minimum: 0
68
+
maximum: 7
69
+
70
+
interrupts:
71
+
minItems: 1
72
+
maxItems: 2
73
+
items:
74
+
- description: physical timer irq
75
+
- description: virtual timer irq
76
+
77
+
reg :
78
+
minItems: 1
79
+
maxItems: 2
80
+
items:
81
+
- description: 1st view base address
82
+
- description: 2nd optional view base address
83
+
84
+
required:
85
+
- frame-number
86
+
- interrupts
87
+
- reg
88
+
89
+
required:
90
+
- compatible
91
+
- reg
92
+
- '#address-cells'
93
+
- '#size-cells'
94
+
95
+
examples:
96
+
- |
97
+
timer@f0000000 {
98
+
compatible = "arm,armv7-timer-mem";
99
+
#address-cells = <1>;
100
+
#size-cells = <1>;
101
+
ranges;
102
+
reg = <0xf0000000 0x1000>;
103
+
clock-frequency = <50000000>;
104
+
105
+
frame@f0001000 {
106
+
frame-number = <0>;
107
+
interrupts = <0 13 0x8>,
108
+
<0 14 0x8>;
109
+
reg = <0xf0001000 0x1000>,
110
+
<0xf0002000 0x1000>;
111
+
};
112
+
113
+
frame@f0003000 {
114
+
frame-number = <1>;
115
+
interrupts = <0 15 0x8>;
116
+
reg = <0xf0003000 0x1000>;
117
+
};
118
+
};
119
+
120
+
...
-27
Documentation/devicetree/bindings/timer/arm,global_timer.txt
-27
Documentation/devicetree/bindings/timer/arm,global_timer.txt
···
1
-
2
-
* ARM Global Timer
3
-
Cortex-A9 are often associated with a per-core Global timer.
4
-
5
-
** Timer node required properties:
6
-
7
-
- compatible : should contain
8
-
* "arm,cortex-a5-global-timer" for Cortex-A5 global timers.
9
-
* "arm,cortex-a9-global-timer" for Cortex-A9 global
10
-
timers or any compatible implementation. Note: driver
11
-
supports versions r2p0 and above.
12
-
13
-
- interrupts : One interrupt to each core
14
-
15
-
- reg : Specify the base address and the size of the GT timer
16
-
register window.
17
-
18
-
- clocks : Should be phandle to a clock.
19
-
20
-
Example:
21
-
22
-
timer@2c000600 {
23
-
compatible = "arm,cortex-a9-global-timer";
24
-
reg = <0x2c000600 0x20>;
25
-
interrupts = <1 13 0xf01>;
26
-
clocks = <&arm_periph_clk>;
27
-
};
+46
Documentation/devicetree/bindings/timer/arm,global_timer.yaml
+46
Documentation/devicetree/bindings/timer/arm,global_timer.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/timer/arm,global_timer.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: ARM Global Timer
8
+
9
+
maintainers:
10
+
- Stuart Menefy <stuart.menefy@st.com>
11
+
12
+
description:
13
+
Cortex-A9 are often associated with a per-core Global timer.
14
+
15
+
properties:
16
+
compatible:
17
+
items:
18
+
- enum:
19
+
- arm,cortex-a5-global-timer
20
+
- arm,cortex-a9-global-timer
21
+
22
+
description: driver supports versions r2p0 and above.
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
interrupts:
28
+
maxItems: 1
29
+
30
+
clocks:
31
+
maxItems: 1
32
+
33
+
required:
34
+
- compatible
35
+
- reg
36
+
- clocks
37
+
38
+
examples:
39
+
- |
40
+
timer@2c000600 {
41
+
compatible = "arm,cortex-a9-global-timer";
42
+
reg = <0x2c000600 0x20>;
43
+
interrupts = <1 13 0xf01>;
44
+
clocks = <&arm_periph_clk>;
45
+
};
46
+
...