regulator: mt6359: Add support for MT6359P regulator

+373 -6

drivers/regulator/mt6359-regulator.c

··· 4 4 5 5 #include <linux/platform_device.h> 6 6 #include <linux/mfd/mt6359/registers.h> 7 + #include <linux/mfd/mt6359p/registers.h> 7 8 #include <linux/mfd/mt6397/core.h> 8 9 #include <linux/module.h> 9 10 #include <linux/of_device.h> ··· 148 147 .qi = BIT(0), \ 149 148 } 150 149 150 + #define MT6359P_LDO1(match, _name, _ops, _volt_table, \ 151 + _enable_reg, _enable_mask, _status_reg, \ 152 + _vsel_reg, _vsel_mask) \ 153 + [MT6359_ID_##_name] = { \ 154 + .desc = { \ 155 + .name = #_name, \ 156 + .of_match = of_match_ptr(match), \ 157 + .regulators_node = of_match_ptr("regulators"), \ 158 + .ops = &_ops, \ 159 + .type = REGULATOR_VOLTAGE, \ 160 + .id = MT6359_ID_##_name, \ 161 + .owner = THIS_MODULE, \ 162 + .n_voltages = ARRAY_SIZE(_volt_table), \ 163 + .volt_table = _volt_table, \ 164 + .vsel_reg = _vsel_reg, \ 165 + .vsel_mask = _vsel_mask, \ 166 + .enable_reg = _enable_reg, \ 167 + .enable_mask = BIT(_enable_mask), \ 168 + }, \ 169 + .status_reg = _status_reg, \ 170 + .qi = BIT(0), \ 171 + } 172 + 151 173 static const struct linear_range mt_volt_range1[] = { 152 174 REGULATOR_LINEAR_RANGE(800000, 0, 0x70, 12500), 153 175 }; ··· 197 173 198 174 static const struct linear_range mt_volt_range7[] = { 199 175 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250), 176 + }; 177 + 178 + static const struct linear_range mt_volt_range8[] = { 179 + REGULATOR_LINEAR_RANGE(506250, 0, 0x7f, 6250), 200 180 }; 201 181 202 182 static const u32 vsim1_voltages[] = { ··· 240 212 0, 0, 1500000, 0, 0, 0, 0, 1600000, 0, 0, 0, 0, 1700000, 241 213 }; 242 214 215 + static const u32 vrfck_voltages_1[] = { 216 + 1240000, 1600000, 217 + }; 218 + 243 219 static const u32 vio28_voltages[] = { 244 220 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000, 245 221 }; 246 222 247 223 static const u32 vemc_voltages[] = { 248 224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2900000, 3000000, 0, 3300000, 225 + }; 226 + 227 + static const u32 vemc_voltages_1[] = { 228 + 0, 0, 0, 0, 0, 0, 0, 0, 2500000, 2800000, 2900000, 3000000, 3100000, 229 + 3300000, 249 230 }; 250 231 251 232 static const u32 va12_voltages[] = { ··· 393 356 return ret; 394 357 } 395 358 359 + static int mt6359p_vemc_set_voltage_sel(struct regulator_dev *rdev, 360 + u32 sel) 361 + { 362 + struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); 363 + int ret; 364 + u32 val = 0; 365 + 366 + sel <<= ffs(info->desc.vsel_mask) - 1; 367 + ret = regmap_write(rdev->regmap, MT6359P_TMA_KEY_ADDR, TMA_KEY); 368 + if (ret) 369 + return ret; 370 + 371 + ret = regmap_read(rdev->regmap, MT6359P_VM_MODE_ADDR, &val); 372 + if (ret) 373 + return ret; 374 + 375 + switch (val) { 376 + case 0: 377 + /* If HW trapping is 0, use VEMC_VOSEL_0 */ 378 + ret = regmap_update_bits(rdev->regmap, 379 + info->desc.vsel_reg, 380 + info->desc.vsel_mask, sel); 381 + break; 382 + case 1: 383 + /* If HW trapping is 1, use VEMC_VOSEL_1 */ 384 + ret = regmap_update_bits(rdev->regmap, 385 + info->desc.vsel_reg + 0x2, 386 + info->desc.vsel_mask, sel); 387 + break; 388 + default: 389 + return -EINVAL; 390 + } 391 + 392 + if (ret) 393 + return ret; 394 + 395 + ret = regmap_write(rdev->regmap, MT6359P_TMA_KEY_ADDR, 0); 396 + return ret; 397 + } 398 + 399 + static int mt6359p_vemc_get_voltage_sel(struct regulator_dev *rdev) 400 + { 401 + struct mt6359_regulator_info *info = rdev_get_drvdata(rdev); 402 + int ret; 403 + u32 val = 0; 404 + 405 + ret = regmap_read(rdev->regmap, MT6359P_VM_MODE_ADDR, &val); 406 + if (ret) 407 + return ret; 408 + switch (val) { 409 + case 0: 410 + /* If HW trapping is 0, use VEMC_VOSEL_0 */ 411 + ret = regmap_read(rdev->regmap, 412 + info->desc.vsel_reg, &val); 413 + break; 414 + case 1: 415 + /* If HW trapping is 1, use VEMC_VOSEL_1 */ 416 + ret = regmap_read(rdev->regmap, 417 + info->desc.vsel_reg + 0x2, &val); 418 + break; 419 + default: 420 + return -EINVAL; 421 + } 422 + if (ret) 423 + return ret; 424 + 425 + val &= info->desc.vsel_mask; 426 + val >>= ffs(info->desc.vsel_mask) - 1; 427 + 428 + return val; 429 + } 430 + 396 431 static const struct regulator_ops mt6359_volt_range_ops = { 397 432 .list_voltage = regulator_list_voltage_linear_range, 398 433 .map_voltage = regulator_map_voltage_linear_range, ··· 492 383 }; 493 384 494 385 static const struct regulator_ops mt6359_volt_fixed_ops = { 386 + .enable = regulator_enable_regmap, 387 + .disable = regulator_disable_regmap, 388 + .is_enabled = regulator_is_enabled_regmap, 389 + .get_status = mt6359_get_status, 390 + }; 391 + 392 + static const struct regulator_ops mt6359p_vemc_ops = { 393 + .list_voltage = regulator_list_voltage_table, 394 + .map_voltage = regulator_map_voltage_iterate, 395 + .set_voltage_sel = mt6359p_vemc_set_voltage_sel, 396 + .get_voltage_sel = mt6359p_vemc_get_voltage_sel, 397 + .set_voltage_time_sel = regulator_set_voltage_time_sel, 495 398 .enable = regulator_enable_regmap, 496 399 .disable = regulator_disable_regmap, 497 400 .is_enabled = regulator_is_enabled_regmap, ··· 747 626 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT), 748 627 }; 749 628 629 + static struct mt6359_regulator_info mt6359p_regulators[] = { 630 + MT6359_BUCK("buck_vs1", VS1, 800000, 2200000, 12500, 0, 631 + mt_volt_range1, MT6359_RG_BUCK_VS1_EN_ADDR, 632 + MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR, 633 + MT6359_RG_BUCK_VS1_VOSEL_MASK << 634 + MT6359_RG_BUCK_VS1_VOSEL_SHIFT, 635 + MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT, 636 + MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT), 637 + MT6359_BUCK("buck_vgpu11", VGPU11, 400000, 1193750, 6250, 0, 638 + mt_volt_range2, MT6359_RG_BUCK_VGPU11_EN_ADDR, 639 + MT6359_DA_VGPU11_EN_ADDR, MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR, 640 + MT6359_RG_BUCK_VGPU11_VOSEL_MASK << 641 + MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT, 642 + MT6359_RG_BUCK_VGPU11_LP_ADDR, 643 + MT6359_RG_BUCK_VGPU11_LP_SHIFT, 644 + MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), 645 + MT6359_BUCK("buck_vmodem", VMODEM, 400000, 1100000, 6250, 0, 646 + mt_volt_range3, MT6359_RG_BUCK_VMODEM_EN_ADDR, 647 + MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR, 648 + MT6359_RG_BUCK_VMODEM_VOSEL_MASK << 649 + MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT, 650 + MT6359_RG_BUCK_VMODEM_LP_ADDR, 651 + MT6359_RG_BUCK_VMODEM_LP_SHIFT, 652 + MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT), 653 + MT6359_BUCK("buck_vpu", VPU, 400000, 1193750, 6250, 0, 654 + mt_volt_range2, MT6359_RG_BUCK_VPU_EN_ADDR, 655 + MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR, 656 + MT6359_RG_BUCK_VPU_VOSEL_MASK << 657 + MT6359_RG_BUCK_VPU_VOSEL_SHIFT, 658 + MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT, 659 + MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT), 660 + MT6359_BUCK("buck_vcore", VCORE, 506250, 1300000, 6250, 0, 661 + mt_volt_range8, MT6359_RG_BUCK_VCORE_EN_ADDR, 662 + MT6359_DA_VCORE_EN_ADDR, MT6359P_RG_BUCK_VCORE_VOSEL_ADDR, 663 + MT6359_RG_BUCK_VCORE_VOSEL_MASK << 664 + MT6359_RG_BUCK_VCORE_VOSEL_SHIFT, 665 + MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT, 666 + MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT), 667 + MT6359_BUCK("buck_vs2", VS2, 800000, 1600000, 12500, 0, 668 + mt_volt_range4, MT6359_RG_BUCK_VS2_EN_ADDR, 669 + MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR, 670 + MT6359_RG_BUCK_VS2_VOSEL_MASK << 671 + MT6359_RG_BUCK_VS2_VOSEL_SHIFT, 672 + MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT, 673 + MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT), 674 + MT6359_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, 0, 675 + mt_volt_range5, MT6359_RG_BUCK_VPA_EN_ADDR, 676 + MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR, 677 + MT6359_RG_BUCK_VPA_VOSEL_MASK << 678 + MT6359_RG_BUCK_VPA_VOSEL_SHIFT, 679 + MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT, 680 + MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT), 681 + MT6359_BUCK("buck_vproc2", VPROC2, 400000, 1193750, 6250, 0, 682 + mt_volt_range2, MT6359_RG_BUCK_VPROC2_EN_ADDR, 683 + MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR, 684 + MT6359_RG_BUCK_VPROC2_VOSEL_MASK << 685 + MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT, 686 + MT6359_RG_BUCK_VPROC2_LP_ADDR, 687 + MT6359_RG_BUCK_VPROC2_LP_SHIFT, 688 + MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT), 689 + MT6359_BUCK("buck_vproc1", VPROC1, 400000, 1193750, 6250, 0, 690 + mt_volt_range2, MT6359_RG_BUCK_VPROC1_EN_ADDR, 691 + MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR, 692 + MT6359_RG_BUCK_VPROC1_VOSEL_MASK << 693 + MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT, 694 + MT6359_RG_BUCK_VPROC1_LP_ADDR, 695 + MT6359_RG_BUCK_VPROC1_LP_SHIFT, 696 + MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT), 697 + MT6359_BUCK("buck_vgpu11_sshub", VGPU11_SSHUB, 400000, 1193750, 6250, 0, 698 + mt_volt_range2, MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR, 699 + MT6359_DA_VGPU11_EN_ADDR, 700 + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR, 701 + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK << 702 + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT, 703 + MT6359_RG_BUCK_VGPU11_LP_ADDR, 704 + MT6359_RG_BUCK_VGPU11_LP_SHIFT, 705 + MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), 706 + MT6359_REG_FIXED("ldo_vaud18", VAUD18, MT6359P_RG_LDO_VAUD18_EN_ADDR, 707 + MT6359P_DA_VAUD18_B_EN_ADDR, 1800000), 708 + MT6359_LDO("ldo_vsim1", VSIM1, vsim1_voltages, 709 + MT6359P_RG_LDO_VSIM1_EN_ADDR, MT6359P_RG_LDO_VSIM1_EN_SHIFT, 710 + MT6359P_DA_VSIM1_B_EN_ADDR, MT6359P_RG_VSIM1_VOSEL_ADDR, 711 + MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT, 712 + 480), 713 + MT6359_LDO("ldo_vibr", VIBR, vibr_voltages, 714 + MT6359P_RG_LDO_VIBR_EN_ADDR, MT6359P_RG_LDO_VIBR_EN_SHIFT, 715 + MT6359P_DA_VIBR_B_EN_ADDR, MT6359P_RG_VIBR_VOSEL_ADDR, 716 + MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT, 717 + 240), 718 + MT6359_LDO("ldo_vrf12", VRF12, vrf12_voltages, 719 + MT6359P_RG_LDO_VRF12_EN_ADDR, MT6359P_RG_LDO_VRF12_EN_SHIFT, 720 + MT6359P_DA_VRF12_B_EN_ADDR, MT6359P_RG_VRF12_VOSEL_ADDR, 721 + MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT, 722 + 480), 723 + MT6359_REG_FIXED("ldo_vusb", VUSB, MT6359P_RG_LDO_VUSB_EN_0_ADDR, 724 + MT6359P_DA_VUSB_B_EN_ADDR, 3000000), 725 + MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1293750, 6250, 726 + 0, mt_volt_range6, MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR, 727 + MT6359P_DA_VSRAM_PROC2_B_EN_ADDR, 728 + MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR, 729 + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK << 730 + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT), 731 + MT6359_LDO("ldo_vio18", VIO18, volt18_voltages, 732 + MT6359P_RG_LDO_VIO18_EN_ADDR, MT6359P_RG_LDO_VIO18_EN_SHIFT, 733 + MT6359P_DA_VIO18_B_EN_ADDR, MT6359P_RG_VIO18_VOSEL_ADDR, 734 + MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT, 735 + 960), 736 + MT6359_LDO("ldo_vcamio", VCAMIO, volt18_voltages, 737 + MT6359P_RG_LDO_VCAMIO_EN_ADDR, 738 + MT6359P_RG_LDO_VCAMIO_EN_SHIFT, 739 + MT6359P_DA_VCAMIO_B_EN_ADDR, MT6359P_RG_VCAMIO_VOSEL_ADDR, 740 + MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT, 741 + 1290), 742 + MT6359_REG_FIXED("ldo_vcn18", VCN18, MT6359P_RG_LDO_VCN18_EN_ADDR, 743 + MT6359P_DA_VCN18_B_EN_ADDR, 1800000), 744 + MT6359_REG_FIXED("ldo_vfe28", VFE28, MT6359P_RG_LDO_VFE28_EN_ADDR, 745 + MT6359P_DA_VFE28_B_EN_ADDR, 2800000), 746 + MT6359_LDO("ldo_vcn13", VCN13, vcn13_voltages, 747 + MT6359P_RG_LDO_VCN13_EN_ADDR, MT6359P_RG_LDO_VCN13_EN_SHIFT, 748 + MT6359P_DA_VCN13_B_EN_ADDR, MT6359P_RG_VCN13_VOSEL_ADDR, 749 + MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT, 750 + 240), 751 + MT6359_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages, 752 + MT6359P_RG_LDO_VCN33_1_EN_0_ADDR, 753 + MT6359_RG_LDO_VCN33_1_EN_0_SHIFT, 754 + MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, 755 + MT6359_RG_VCN33_1_VOSEL_MASK << 756 + MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), 757 + MT6359_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages, 758 + MT6359P_RG_LDO_VCN33_1_EN_1_ADDR, 759 + MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT, 760 + MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, 761 + MT6359_RG_VCN33_1_VOSEL_MASK << 762 + MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), 763 + MT6359_REG_FIXED("ldo_vaux18", VAUX18, MT6359P_RG_LDO_VAUX18_EN_ADDR, 764 + MT6359P_DA_VAUX18_B_EN_ADDR, 1800000), 765 + MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 766 + 6250, 0, mt_volt_range6, 767 + MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR, 768 + MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, 769 + MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR, 770 + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK << 771 + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT), 772 + MT6359_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, 773 + MT6359P_RG_LDO_VEFUSE_EN_ADDR, 774 + MT6359P_RG_LDO_VEFUSE_EN_SHIFT, 775 + MT6359P_DA_VEFUSE_B_EN_ADDR, MT6359P_RG_VEFUSE_VOSEL_ADDR, 776 + MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT, 777 + 240), 778 + MT6359_LDO("ldo_vxo22", VXO22, vxo22_voltages, 779 + MT6359P_RG_LDO_VXO22_EN_ADDR, MT6359P_RG_LDO_VXO22_EN_SHIFT, 780 + MT6359P_DA_VXO22_B_EN_ADDR, MT6359P_RG_VXO22_VOSEL_ADDR, 781 + MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT, 782 + 480), 783 + MT6359_LDO("ldo_vrfck_1", VRFCK, vrfck_voltages_1, 784 + MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT, 785 + MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR, 786 + MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT, 787 + 480), 788 + MT6359_REG_FIXED("ldo_vbif28", VBIF28, MT6359P_RG_LDO_VBIF28_EN_ADDR, 789 + MT6359P_DA_VBIF28_B_EN_ADDR, 2800000), 790 + MT6359_LDO("ldo_vio28", VIO28, vio28_voltages, 791 + MT6359P_RG_LDO_VIO28_EN_ADDR, MT6359P_RG_LDO_VIO28_EN_SHIFT, 792 + MT6359P_DA_VIO28_B_EN_ADDR, MT6359P_RG_VIO28_VOSEL_ADDR, 793 + MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT, 794 + 1920), 795 + MT6359P_LDO1("ldo_vemc_1", VEMC, mt6359p_vemc_ops, vemc_voltages_1, 796 + MT6359P_RG_LDO_VEMC_EN_ADDR, MT6359P_RG_LDO_VEMC_EN_SHIFT, 797 + MT6359P_DA_VEMC_B_EN_ADDR, 798 + MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR, 799 + MT6359P_RG_LDO_VEMC_VOSEL_0_MASK << 800 + MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT), 801 + MT6359_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages, 802 + MT6359P_RG_LDO_VCN33_2_EN_0_ADDR, 803 + MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT, 804 + MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, 805 + MT6359_RG_VCN33_2_VOSEL_MASK << 806 + MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), 807 + MT6359_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages, 808 + MT6359P_RG_LDO_VCN33_2_EN_1_ADDR, 809 + MT6359_RG_LDO_VCN33_2_EN_1_SHIFT, 810 + MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, 811 + MT6359_RG_VCN33_2_VOSEL_MASK << 812 + MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), 813 + MT6359_LDO("ldo_va12", VA12, va12_voltages, 814 + MT6359P_RG_LDO_VA12_EN_ADDR, MT6359P_RG_LDO_VA12_EN_SHIFT, 815 + MT6359P_DA_VA12_B_EN_ADDR, MT6359P_RG_VA12_VOSEL_ADDR, 816 + MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT, 817 + 960), 818 + MT6359_LDO("ldo_va09", VA09, va09_voltages, 819 + MT6359P_RG_LDO_VA09_EN_ADDR, MT6359P_RG_LDO_VA09_EN_SHIFT, 820 + MT6359P_DA_VA09_B_EN_ADDR, MT6359P_RG_VA09_VOSEL_ADDR, 821 + MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT, 822 + 960), 823 + MT6359_LDO("ldo_vrf18", VRF18, vrf18_voltages, 824 + MT6359P_RG_LDO_VRF18_EN_ADDR, MT6359P_RG_LDO_VRF18_EN_SHIFT, 825 + MT6359P_DA_VRF18_B_EN_ADDR, MT6359P_RG_VRF18_VOSEL_ADDR, 826 + MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT, 827 + 240), 828 + MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1293750, 6250, 829 + 0, mt_volt_range7, MT6359P_RG_LDO_VSRAM_MD_EN_ADDR, 830 + MT6359P_DA_VSRAM_MD_B_EN_ADDR, 831 + MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR, 832 + MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK << 833 + MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT), 834 + MT6359_LDO("ldo_vufs", VUFS, volt18_voltages, 835 + MT6359P_RG_LDO_VUFS_EN_ADDR, MT6359P_RG_LDO_VUFS_EN_SHIFT, 836 + MT6359P_DA_VUFS_B_EN_ADDR, MT6359P_RG_VUFS_VOSEL_ADDR, 837 + MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT, 838 + 1920), 839 + MT6359_LDO("ldo_vm18", VM18, volt18_voltages, 840 + MT6359P_RG_LDO_VM18_EN_ADDR, MT6359P_RG_LDO_VM18_EN_SHIFT, 841 + MT6359P_DA_VM18_B_EN_ADDR, MT6359P_RG_VM18_VOSEL_ADDR, 842 + MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT, 843 + 1920), 844 + MT6359_LDO("ldo_vbbck", VBBCK, vbbck_voltages, 845 + MT6359P_RG_LDO_VBBCK_EN_ADDR, MT6359P_RG_LDO_VBBCK_EN_SHIFT, 846 + MT6359P_DA_VBBCK_B_EN_ADDR, MT6359P_RG_VBBCK_VOSEL_ADDR, 847 + MT6359P_RG_VBBCK_VOSEL_MASK << MT6359P_RG_VBBCK_VOSEL_SHIFT, 848 + 480), 849 + MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1293750, 6250, 850 + 0, mt_volt_range6, MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR, 851 + MT6359P_DA_VSRAM_PROC1_B_EN_ADDR, 852 + MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR, 853 + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK << 854 + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT), 855 + MT6359_LDO("ldo_vsim2", VSIM2, vsim2_voltages, 856 + MT6359P_RG_LDO_VSIM2_EN_ADDR, MT6359P_RG_LDO_VSIM2_EN_SHIFT, 857 + MT6359P_DA_VSIM2_B_EN_ADDR, MT6359P_RG_VSIM2_VOSEL_ADDR, 858 + MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT, 859 + 480), 860 + MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 861 + 500000, 1293750, 6250, 0, mt_volt_range6, 862 + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR, 863 + MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, 864 + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR, 865 + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK << 866 + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT), 867 + }; 868 + 750 869 static int mt6359_regulator_probe(struct platform_device *pdev) 751 870 { 752 871 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 753 872 struct regulator_config config = {}; 754 873 struct regulator_dev *rdev; 755 - int i; 874 + struct mt6359_regulator_info *mt6359_info; 875 + int i, hw_ver; 876 + 877 + regmap_read(mt6397->regmap, MT6359P_HWCID, &hw_ver); 878 + if (hw_ver >= MT6359P_CHIP_VER) 879 + mt6359_info = mt6359p_regulators; 880 + else 881 + mt6359_info = mt6359_regulators; 756 882 757 883 config.dev = mt6397->dev; 758 884 config.regmap = mt6397->regmap; 759 - for (i = 0; i < MT6359_MAX_REGULATOR; i++) { 760 - config.driver_data = &mt6359_regulators[i]; 761 - rdev = devm_regulator_register(&pdev->dev, &mt6359_regulators[i].desc, &config); 885 + for (i = 0; i < MT6359_MAX_REGULATOR; i++, mt6359_info++) { 886 + config.driver_data = mt6359_info; 887 + rdev = devm_regulator_register(&pdev->dev, &mt6359_info->desc, &config); 762 888 if (IS_ERR(rdev)) { 763 - dev_err(&pdev->dev, "failed to register %s\n", 764 - mt6359_regulators[i].desc.name); 889 + dev_err(&pdev->dev, "failed to register %s\n", mt6359_info->desc.name); 765 890 return PTR_ERR(rdev); 766 891 } 767 892 }

+249

include/linux/mfd/mt6359p/registers.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2021 MediaTek Inc. 4 + */ 5 + 6 + #ifndef __MFD_MT6359P_REGISTERS_H__ 7 + #define __MFD_MT6359P_REGISTERS_H__ 8 + 9 + #define MT6359P_CHIP_VER 0x5930 10 + 11 + /* PMIC Registers */ 12 + #define MT6359P_HWCID 0x8 13 + #define MT6359P_TOP_TRAP 0x50 14 + #define MT6359P_TOP_TMA_KEY 0x3a8 15 + #define MT6359P_BUCK_VCORE_ELR_NUM 0x152a 16 + #define MT6359P_BUCK_VCORE_ELR0 0x152c 17 + #define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa 18 + #define MT6359P_BUCK_VGPU11_ELR0 0x15b4 19 + #define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44 20 + #define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46 21 + #define MT6359P_LDO_VSRAM_OTHERS_ELR 0x1b48 22 + #define MT6359P_LDO_VSRAM_MD_ELR 0x1b4a 23 + #define MT6359P_LDO_VEMC_ELR_0 0x1b4c 24 + #define MT6359P_LDO_VFE28_CON0 0x1b88 25 + #define MT6359P_LDO_VFE28_MON 0x1b8c 26 + #define MT6359P_LDO_VXO22_CON0 0x1b9a 27 + #define MT6359P_LDO_VXO22_MON 0x1b9e 28 + #define MT6359P_LDO_VRF18_CON0 0x1bac 29 + #define MT6359P_LDO_VRF18_MON 0x1bb0 30 + #define MT6359P_LDO_VRF12_CON0 0x1bbe 31 + #define MT6359P_LDO_VRF12_MON 0x1bc2 32 + #define MT6359P_LDO_VEFUSE_CON0 0x1bd0 33 + #define MT6359P_LDO_VEFUSE_MON 0x1bd4 34 + #define MT6359P_LDO_VCN33_1_CON0 0x1be2 35 + #define MT6359P_LDO_VCN33_1_MON 0x1be6 36 + #define MT6359P_LDO_VCN33_1_MULTI_SW 0x1bf4 37 + #define MT6359P_LDO_VCN33_2_CON0 0x1c08 38 + #define MT6359P_LDO_VCN33_2_MON 0x1c0c 39 + #define MT6359P_LDO_VCN33_2_MULTI_SW 0x1c1a 40 + #define MT6359P_LDO_VCN13_CON0 0x1c1c 41 + #define MT6359P_LDO_VCN13_MON 0x1c20 42 + #define MT6359P_LDO_VCN18_CON0 0x1c2e 43 + #define MT6359P_LDO_VCN18_MON 0x1c32 44 + #define MT6359P_LDO_VA09_CON0 0x1c40 45 + #define MT6359P_LDO_VA09_MON 0x1c44 46 + #define MT6359P_LDO_VCAMIO_CON0 0x1c52 47 + #define MT6359P_LDO_VCAMIO_MON 0x1c56 48 + #define MT6359P_LDO_VA12_CON0 0x1c64 49 + #define MT6359P_LDO_VA12_MON 0x1c68 50 + #define MT6359P_LDO_VAUX18_CON0 0x1c88 51 + #define MT6359P_LDO_VAUX18_MON 0x1c8c 52 + #define MT6359P_LDO_VAUD18_CON0 0x1c9a 53 + #define MT6359P_LDO_VAUD18_MON 0x1c9e 54 + #define MT6359P_LDO_VIO18_CON0 0x1cac 55 + #define MT6359P_LDO_VIO18_MON 0x1cb0 56 + #define MT6359P_LDO_VEMC_CON0 0x1cbe 57 + #define MT6359P_LDO_VEMC_MON 0x1cc2 58 + #define MT6359P_LDO_VSIM1_CON0 0x1cd0 59 + #define MT6359P_LDO_VSIM1_MON 0x1cd4 60 + #define MT6359P_LDO_VSIM2_CON0 0x1ce2 61 + #define MT6359P_LDO_VSIM2_MON 0x1ce6 62 + #define MT6359P_LDO_VUSB_CON0 0x1d08 63 + #define MT6359P_LDO_VUSB_MON 0x1d0c 64 + #define MT6359P_LDO_VUSB_MULTI_SW 0x1d1a 65 + #define MT6359P_LDO_VRFCK_CON0 0x1d1c 66 + #define MT6359P_LDO_VRFCK_MON 0x1d20 67 + #define MT6359P_LDO_VBBCK_CON0 0x1d2e 68 + #define MT6359P_LDO_VBBCK_MON 0x1d32 69 + #define MT6359P_LDO_VBIF28_CON0 0x1d40 70 + #define MT6359P_LDO_VBIF28_MON 0x1d44 71 + #define MT6359P_LDO_VIBR_CON0 0x1d52 72 + #define MT6359P_LDO_VIBR_MON 0x1d56 73 + #define MT6359P_LDO_VIO28_CON0 0x1d64 74 + #define MT6359P_LDO_VIO28_MON 0x1d68 75 + #define MT6359P_LDO_VM18_CON0 0x1d88 76 + #define MT6359P_LDO_VM18_MON 0x1d8c 77 + #define MT6359P_LDO_VUFS_CON0 0x1d9a 78 + #define MT6359P_LDO_VUFS_MON 0x1d9e 79 + #define MT6359P_LDO_VSRAM_PROC1_CON0 0x1e88 80 + #define MT6359P_LDO_VSRAM_PROC1_MON 0x1e8c 81 + #define MT6359P_LDO_VSRAM_PROC1_VOSEL1 0x1e90 82 + #define MT6359P_LDO_VSRAM_PROC2_CON0 0x1ea8 83 + #define MT6359P_LDO_VSRAM_PROC2_MON 0x1eac 84 + #define MT6359P_LDO_VSRAM_PROC2_VOSEL1 0x1eb0 85 + #define MT6359P_LDO_VSRAM_OTHERS_CON0 0x1f08 86 + #define MT6359P_LDO_VSRAM_OTHERS_MON 0x1f0c 87 + #define MT6359P_LDO_VSRAM_OTHERS_VOSEL1 0x1f10 88 + #define MT6359P_LDO_VSRAM_OTHERS_SSHUB 0x1f28 89 + #define MT6359P_LDO_VSRAM_MD_CON0 0x1f2e 90 + #define MT6359P_LDO_VSRAM_MD_MON 0x1f32 91 + #define MT6359P_LDO_VSRAM_MD_VOSEL1 0x1f36 92 + #define MT6359P_VFE28_ANA_CON0 0x1f88 93 + #define MT6359P_VAUX18_ANA_CON0 0x1f8c 94 + #define MT6359P_VUSB_ANA_CON0 0x1f90 95 + #define MT6359P_VBIF28_ANA_CON0 0x1f94 96 + #define MT6359P_VCN33_1_ANA_CON0 0x1f98 97 + #define MT6359P_VCN33_2_ANA_CON0 0x1f9c 98 + #define MT6359P_VEMC_ANA_CON0 0x1fa0 99 + #define MT6359P_VSIM1_ANA_CON0 0x1fa2 100 + #define MT6359P_VSIM2_ANA_CON0 0x1fa6 101 + #define MT6359P_VIO28_ANA_CON0 0x1faa 102 + #define MT6359P_VIBR_ANA_CON0 0x1fae 103 + #define MT6359P_VFE28_ELR_4 0x1fc0 104 + #define MT6359P_VRF18_ANA_CON0 0x2008 105 + #define MT6359P_VEFUSE_ANA_CON0 0x200c 106 + #define MT6359P_VCN18_ANA_CON0 0x2010 107 + #define MT6359P_VCAMIO_ANA_CON0 0x2014 108 + #define MT6359P_VAUD18_ANA_CON0 0x2018 109 + #define MT6359P_VIO18_ANA_CON0 0x201c 110 + #define MT6359P_VM18_ANA_CON0 0x2020 111 + #define MT6359P_VUFS_ANA_CON0 0x2024 112 + #define MT6359P_VRF12_ANA_CON0 0x202a 113 + #define MT6359P_VCN13_ANA_CON0 0x202e 114 + #define MT6359P_VA09_ANA_CON0 0x2032 115 + #define MT6359P_VRF18_ELR_3 0x204e 116 + #define MT6359P_VXO22_ANA_CON0 0x2088 117 + #define MT6359P_VRFCK_ANA_CON0 0x208c 118 + #define MT6359P_VBBCK_ANA_CON0 0x2096 119 + 120 + #define MT6359P_RG_BUCK_VCORE_VOSEL_ADDR MT6359P_BUCK_VCORE_ELR0 121 + #define MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 122 + #define MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR MT6359P_BUCK_VGPU11_ELR0 123 + #define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 124 + #define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK 0x7F 125 + #define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT 4 126 + #define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_ELR 127 + #define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_ELR 128 + #define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_ELR 129 + #define MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_ELR 130 + #define MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR MT6359P_LDO_VEMC_ELR_0 131 + #define MT6359P_RG_LDO_VEMC_VOSEL_0_MASK 0xF 132 + #define MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT 0 133 + #define MT6359P_RG_LDO_VFE28_EN_ADDR MT6359P_LDO_VFE28_CON0 134 + #define MT6359P_DA_VFE28_B_EN_ADDR MT6359P_LDO_VFE28_MON 135 + #define MT6359P_RG_LDO_VXO22_EN_ADDR MT6359P_LDO_VXO22_CON0 136 + #define MT6359P_RG_LDO_VXO22_EN_SHIFT 0 137 + #define MT6359P_DA_VXO22_B_EN_ADDR MT6359P_LDO_VXO22_MON 138 + #define MT6359P_RG_LDO_VRF18_EN_ADDR MT6359P_LDO_VRF18_CON0 139 + #define MT6359P_RG_LDO_VRF18_EN_SHIFT 0 140 + #define MT6359P_DA_VRF18_B_EN_ADDR MT6359P_LDO_VRF18_MON 141 + #define MT6359P_RG_LDO_VRF12_EN_ADDR MT6359P_LDO_VRF12_CON0 142 + #define MT6359P_RG_LDO_VRF12_EN_SHIFT 0 143 + #define MT6359P_DA_VRF12_B_EN_ADDR MT6359P_LDO_VRF12_MON 144 + #define MT6359P_RG_LDO_VEFUSE_EN_ADDR MT6359P_LDO_VEFUSE_CON0 145 + #define MT6359P_RG_LDO_VEFUSE_EN_SHIFT 0 146 + #define MT6359P_DA_VEFUSE_B_EN_ADDR MT6359P_LDO_VEFUSE_MON 147 + #define MT6359P_RG_LDO_VCN33_1_EN_0_ADDR MT6359P_LDO_VCN33_1_CON0 148 + #define MT6359P_DA_VCN33_1_B_EN_ADDR MT6359P_LDO_VCN33_1_MON 149 + #define MT6359P_RG_LDO_VCN33_1_EN_1_ADDR MT6359P_LDO_VCN33_1_MULTI_SW 150 + #define MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT 15 151 + #define MT6359P_RG_LDO_VCN33_2_EN_0_ADDR MT6359P_LDO_VCN33_2_CON0 152 + #define MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT 0 153 + #define MT6359P_DA_VCN33_2_B_EN_ADDR MT6359P_LDO_VCN33_2_MON 154 + #define MT6359P_RG_LDO_VCN33_2_EN_1_ADDR MT6359P_LDO_VCN33_2_MULTI_SW 155 + #define MT6359P_RG_LDO_VCN13_EN_ADDR MT6359P_LDO_VCN13_CON0 156 + #define MT6359P_RG_LDO_VCN13_EN_SHIFT 0 157 + #define MT6359P_DA_VCN13_B_EN_ADDR MT6359P_LDO_VCN13_MON 158 + #define MT6359P_RG_LDO_VCN18_EN_ADDR MT6359P_LDO_VCN18_CON0 159 + #define MT6359P_DA_VCN18_B_EN_ADDR MT6359P_LDO_VCN18_MON 160 + #define MT6359P_RG_LDO_VA09_EN_ADDR MT6359P_LDO_VA09_CON0 161 + #define MT6359P_RG_LDO_VA09_EN_SHIFT 0 162 + #define MT6359P_DA_VA09_B_EN_ADDR MT6359P_LDO_VA09_MON 163 + #define MT6359P_RG_LDO_VCAMIO_EN_ADDR MT6359P_LDO_VCAMIO_CON0 164 + #define MT6359P_RG_LDO_VCAMIO_EN_SHIFT 0 165 + #define MT6359P_DA_VCAMIO_B_EN_ADDR MT6359P_LDO_VCAMIO_MON 166 + #define MT6359P_RG_LDO_VA12_EN_ADDR MT6359P_LDO_VA12_CON0 167 + #define MT6359P_RG_LDO_VA12_EN_SHIFT 0 168 + #define MT6359P_DA_VA12_B_EN_ADDR MT6359P_LDO_VA12_MON 169 + #define MT6359P_RG_LDO_VAUX18_EN_ADDR MT6359P_LDO_VAUX18_CON0 170 + #define MT6359P_DA_VAUX18_B_EN_ADDR MT6359P_LDO_VAUX18_MON 171 + #define MT6359P_RG_LDO_VAUD18_EN_ADDR MT6359P_LDO_VAUD18_CON0 172 + #define MT6359P_DA_VAUD18_B_EN_ADDR MT6359P_LDO_VAUD18_MON 173 + #define MT6359P_RG_LDO_VIO18_EN_ADDR MT6359P_LDO_VIO18_CON0 174 + #define MT6359P_RG_LDO_VIO18_EN_SHIFT 0 175 + #define MT6359P_DA_VIO18_B_EN_ADDR MT6359P_LDO_VIO18_MON 176 + #define MT6359P_RG_LDO_VEMC_EN_ADDR MT6359P_LDO_VEMC_CON0 177 + #define MT6359P_RG_LDO_VEMC_EN_SHIFT 0 178 + #define MT6359P_DA_VEMC_B_EN_ADDR MT6359P_LDO_VEMC_MON 179 + #define MT6359P_RG_LDO_VSIM1_EN_ADDR MT6359P_LDO_VSIM1_CON0 180 + #define MT6359P_RG_LDO_VSIM1_EN_SHIFT 0 181 + #define MT6359P_DA_VSIM1_B_EN_ADDR MT6359P_LDO_VSIM1_MON 182 + #define MT6359P_RG_LDO_VSIM2_EN_ADDR MT6359P_LDO_VSIM2_CON0 183 + #define MT6359P_RG_LDO_VSIM2_EN_SHIFT 0 184 + #define MT6359P_DA_VSIM2_B_EN_ADDR MT6359P_LDO_VSIM2_MON 185 + #define MT6359P_RG_LDO_VUSB_EN_0_ADDR MT6359P_LDO_VUSB_CON0 186 + #define MT6359P_DA_VUSB_B_EN_ADDR MT6359P_LDO_VUSB_MON 187 + #define MT6359P_RG_LDO_VUSB_EN_1_ADDR MT6359P_LDO_VUSB_MULTI_SW 188 + #define MT6359P_RG_LDO_VRFCK_EN_ADDR MT6359P_LDO_VRFCK_CON0 189 + #define MT6359P_RG_LDO_VRFCK_EN_SHIFT 0 190 + #define MT6359P_DA_VRFCK_B_EN_ADDR MT6359P_LDO_VRFCK_MON 191 + #define MT6359P_RG_LDO_VBBCK_EN_ADDR MT6359P_LDO_VBBCK_CON0 192 + #define MT6359P_RG_LDO_VBBCK_EN_SHIFT 0 193 + #define MT6359P_DA_VBBCK_B_EN_ADDR MT6359P_LDO_VBBCK_MON 194 + #define MT6359P_RG_LDO_VBIF28_EN_ADDR MT6359P_LDO_VBIF28_CON0 195 + #define MT6359P_DA_VBIF28_B_EN_ADDR MT6359P_LDO_VBIF28_MON 196 + #define MT6359P_RG_LDO_VIBR_EN_ADDR MT6359P_LDO_VIBR_CON0 197 + #define MT6359P_RG_LDO_VIBR_EN_SHIFT 0 198 + #define MT6359P_DA_VIBR_B_EN_ADDR MT6359P_LDO_VIBR_MON 199 + #define MT6359P_RG_LDO_VIO28_EN_ADDR MT6359P_LDO_VIO28_CON0 200 + #define MT6359P_RG_LDO_VIO28_EN_SHIFT 0 201 + #define MT6359P_DA_VIO28_B_EN_ADDR MT6359P_LDO_VIO28_MON 202 + #define MT6359P_RG_LDO_VM18_EN_ADDR MT6359P_LDO_VM18_CON0 203 + #define MT6359P_RG_LDO_VM18_EN_SHIFT 0 204 + #define MT6359P_DA_VM18_B_EN_ADDR MT6359P_LDO_VM18_MON 205 + #define MT6359P_RG_LDO_VUFS_EN_ADDR MT6359P_LDO_VUFS_CON0 206 + #define MT6359P_RG_LDO_VUFS_EN_SHIFT 0 207 + #define MT6359P_DA_VUFS_B_EN_ADDR MT6359P_LDO_VUFS_MON 208 + #define MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359P_LDO_VSRAM_PROC1_CON0 209 + #define MT6359P_DA_VSRAM_PROC1_B_EN_ADDR MT6359P_LDO_VSRAM_PROC1_MON 210 + #define MT6359P_DA_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_VOSEL1 211 + #define MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359P_LDO_VSRAM_PROC2_CON0 212 + #define MT6359P_DA_VSRAM_PROC2_B_EN_ADDR MT6359P_LDO_VSRAM_PROC2_MON 213 + #define MT6359P_DA_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_VOSEL1 214 + #define MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_CON0 215 + #define MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_MON 216 + #define MT6359P_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_VOSEL1 217 + #define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB 218 + #define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB 219 + #define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR MT6359P_LDO_VSRAM_MD_CON0 220 + #define MT6359P_DA_VSRAM_MD_B_EN_ADDR MT6359P_LDO_VSRAM_MD_MON 221 + #define MT6359P_DA_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_VOSEL1 222 + #define MT6359P_RG_VCN33_1_VOSEL_ADDR MT6359P_VCN33_1_ANA_CON0 223 + #define MT6359P_RG_VCN33_2_VOSEL_ADDR MT6359P_VCN33_2_ANA_CON0 224 + #define MT6359P_RG_VEMC_VOSEL_ADDR MT6359P_VEMC_ANA_CON0 225 + #define MT6359P_RG_VSIM1_VOSEL_ADDR MT6359P_VSIM1_ANA_CON0 226 + #define MT6359P_RG_VSIM2_VOSEL_ADDR MT6359P_VSIM2_ANA_CON0 227 + #define MT6359P_RG_VIO28_VOSEL_ADDR MT6359P_VIO28_ANA_CON0 228 + #define MT6359P_RG_VIBR_VOSEL_ADDR MT6359P_VIBR_ANA_CON0 229 + #define MT6359P_RG_VRF18_VOSEL_ADDR MT6359P_VRF18_ANA_CON0 230 + #define MT6359P_RG_VEFUSE_VOSEL_ADDR MT6359P_VEFUSE_ANA_CON0 231 + #define MT6359P_RG_VCAMIO_VOSEL_ADDR MT6359P_VCAMIO_ANA_CON0 232 + #define MT6359P_RG_VIO18_VOSEL_ADDR MT6359P_VIO18_ANA_CON0 233 + #define MT6359P_RG_VM18_VOSEL_ADDR MT6359P_VM18_ANA_CON0 234 + #define MT6359P_RG_VUFS_VOSEL_ADDR MT6359P_VUFS_ANA_CON0 235 + #define MT6359P_RG_VRF12_VOSEL_ADDR MT6359P_VRF12_ANA_CON0 236 + #define MT6359P_RG_VCN13_VOSEL_ADDR MT6359P_VCN13_ANA_CON0 237 + #define MT6359P_RG_VA09_VOSEL_ADDR MT6359P_VRF18_ELR_3 238 + #define MT6359P_RG_VA12_VOSEL_ADDR MT6359P_VFE28_ELR_4 239 + #define MT6359P_RG_VXO22_VOSEL_ADDR MT6359P_VXO22_ANA_CON0 240 + #define MT6359P_RG_VRFCK_VOSEL_ADDR MT6359P_VRFCK_ANA_CON0 241 + #define MT6359P_RG_VBBCK_VOSEL_ADDR MT6359P_VBBCK_ANA_CON0 242 + #define MT6359P_RG_VBBCK_VOSEL_MASK 0xF 243 + #define MT6359P_RG_VBBCK_VOSEL_SHIFT 4 244 + #define MT6359P_VM_MODE_ADDR MT6359P_TOP_TRAP 245 + #define MT6359P_TMA_KEY_ADDR MT6359P_TOP_TMA_KEY 246 + 247 + #define TMA_KEY 0x9CA6 248 + 249 + #endif /* __MFD_MT6359P_REGISTERS_H__ */

+1

include/linux/regulator/mt6359-regulator.h

··· 17 17 MT6359_ID_VPROC2, 18 18 MT6359_ID_VPROC1, 19 19 MT6359_ID_VCORE_SSHUB, 20 + MT6359_ID_VGPU11_SSHUB = MT6359_ID_VCORE_SSHUB, 20 21 MT6359_ID_VAUD18 = 10, 21 22 MT6359_ID_VSIM1, 22 23 MT6359_ID_VIBR,