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dt-bindings: display: vop2: Add rk3588 support
The vop2 on rk3588 is similar to which on rk356x
but with 4 video ports and need to reference
more grf modules.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211115850.1785311-1-andyshrk@163.com
authored by
Andy Yan
and committed by
Heiko Stuebner
4ccdc92c
c408af1a
+81
-19
+81
-19
Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
+81
-19
Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
···
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description:
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VOP2 (Video Output Processor v2) is the display controller for the Rockchip
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series of SoCs which transfers the image data from a video memory
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buffer to an external LCD interface.
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series of SoCs which transfers the image data from a video memory buffer to
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an external LCD interface.
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maintainers:
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- Sandy Huang <hjc@rock-chips.com>
···
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enum:
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- rockchip,rk3566-vop
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- rockchip,rk3568-vop
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- rockchip,rk3588-vop
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reg:
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items:
···
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Must contain one entry corresponding to the base address and length
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of the register space.
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- description:
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Can optionally contain a second entry corresponding to
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the CRTC gamma LUT address.
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Can optionally contain a second entry corresponding to the CRTC gamma
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LUT address.
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reg-names:
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items:
···
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The VOP interrupt is shared by several interrupt sources, such as
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frame start (VSYNC), line flag and other status interrupts.
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# See compatible-specific constraints below.
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clocks:
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minItems: 5
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items:
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- description: Clock for ddr buffer transfer.
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- description: Clock for the ahb bus to R/W the phy regs.
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- description: Clock for ddr buffer transfer via axi.
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- description: Clock for the ahb bus to R/W the regs.
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- description: Pixel clock for video port 0.
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- description: Pixel clock for video port 1.
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- description: Pixel clock for video port 2.
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- description: Pixel clock for video port 3.
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- description: Peripheral(vop grf/dsi) clock.
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clock-names:
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minItems: 5
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items:
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- const: aclk
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- const: hclk
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- const: dclk_vp0
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- const: dclk_vp1
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- const: dclk_vp2
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- const: dclk_vp3
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- const: pclk_vop
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to GRF regs used for misc control
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Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI,
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also used for query vop memory bisr enable status, etc.
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rockchip,vo1-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi
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on rk3588.
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rockchip,vop-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to VOP GRF regs used for control data path between vopr and hdmi/edp.
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rockchip,pmu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to PMU GRF used for query vop memory bisr status on rk3588.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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patternProperties:
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"^port@[0-3]$":
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Output endpoint of VP0
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description: Output endpoint of VP0/1/2/3.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Output endpoint of VP1
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required:
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- port@0
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Output endpoint of VP2
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unevaluatedProperties: false
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iommus:
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maxItems: 1
···
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- clocks
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- clock-names
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- ports
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: rockchip,rk3588-vop
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then:
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properties:
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clocks:
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minItems: 7
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clock-names:
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minItems: 7
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ports:
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required:
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- port@0
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- port@1
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- port@2
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- port@3
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required:
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- rockchip,grf
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- rockchip,vo1-grf
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- rockchip,vop-grf
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- rockchip,pmu
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else:
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properties:
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rockchip,vo1-grf: false
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rockchip,vop-grf: false
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rockchip,pmu: false
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clocks:
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maxItems: 5
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clock-names:
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maxItems: 5
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ports:
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required:
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- port@0
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- port@1
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- port@2
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additionalProperties: false
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