tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: replace DRM prefix with PCI device info for gfx/mmhub

Prefix RAS message printing in gfx/mmhub with PCI device info,
which assists the debug in multiple GPU case.

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Dennis Li and committed by
Alex Deucher 4cc1178e f9b93c9b

+31 -16
+23 -12
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
··· 732 732 sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, 733 733 SEC_COUNT); 734 734 if (sec_count) { 735 - DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 735 + dev_info(adev->dev, 736 + "Instance[%d]: SubBlock %s, SEC %d\n", i, 736 737 vml2_walker_mems[i], sec_count); 737 738 err_data->ce_count += sec_count; 738 739 } ··· 741 740 ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, 742 741 DED_COUNT); 743 742 if (ded_count) { 744 - DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, 743 + dev_info(adev->dev, 744 + "Instance[%d]: SubBlock %s, DED %d\n", i, 745 745 vml2_walker_mems[i], ded_count); 746 746 err_data->ue_count += ded_count; 747 747 } ··· 754 752 755 753 sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT); 756 754 if (sec_count) { 757 - DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 755 + dev_info(adev->dev, 756 + "Instance[%d]: SubBlock %s, SEC %d\n", i, 758 757 utcl2_router_mems[i], sec_count); 759 758 err_data->ce_count += sec_count; 760 759 } 761 760 762 761 ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT); 763 762 if (ded_count) { 764 - DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, 763 + dev_info(adev->dev, 764 + "Instance[%d]: SubBlock %s, DED %d\n", i, 765 765 utcl2_router_mems[i], ded_count); 766 766 err_data->ue_count += ded_count; 767 767 } ··· 776 772 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, 777 773 SEC_COUNT); 778 774 if (sec_count) { 779 - DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 775 + dev_info(adev->dev, 776 + "Instance[%d]: SubBlock %s, SEC %d\n", i, 780 777 atc_l2_cache_2m_mems[i], sec_count); 781 778 err_data->ce_count += sec_count; 782 779 } ··· 785 780 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, 786 781 DED_COUNT); 787 782 if (ded_count) { 788 - DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, 783 + dev_info(adev->dev, 784 + "Instance[%d]: SubBlock %s, DED %d\n", i, 789 785 atc_l2_cache_2m_mems[i], ded_count); 790 786 err_data->ue_count += ded_count; 791 787 } ··· 799 793 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, 800 794 SEC_COUNT); 801 795 if (sec_count) { 802 - DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 796 + dev_info(adev->dev, 797 + "Instance[%d]: SubBlock %s, SEC %d\n", i, 803 798 atc_l2_cache_4k_mems[i], sec_count); 804 799 err_data->ce_count += sec_count; 805 800 } ··· 808 801 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, 809 802 DED_COUNT); 810 803 if (ded_count) { 811 - DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, 804 + dev_info(adev->dev, 805 + "Instance[%d]: SubBlock %s, DED %d\n", i, 812 806 atc_l2_cache_4k_mems[i], ded_count); 813 807 err_data->ue_count += ded_count; 814 808 } ··· 824 816 return 0; 825 817 } 826 818 827 - static int gfx_v9_4_ras_error_count(const struct soc15_reg_entry *reg, 819 + static int gfx_v9_4_ras_error_count(struct amdgpu_device *adev, 820 + const struct soc15_reg_entry *reg, 828 821 uint32_t se_id, uint32_t inst_id, 829 822 uint32_t value, uint32_t *sec_count, 830 823 uint32_t *ded_count) ··· 842 833 sec_cnt = (value & gfx_v9_4_ras_fields[i].sec_count_mask) >> 843 834 gfx_v9_4_ras_fields[i].sec_count_shift; 844 835 if (sec_cnt) { 845 - DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n", 836 + dev_info(adev->dev, 837 + "GFX SubBlock %s, Instance[%d][%d], SEC %d\n", 846 838 gfx_v9_4_ras_fields[i].name, se_id, inst_id, 847 839 sec_cnt); 848 840 *sec_count += sec_cnt; ··· 852 842 ded_cnt = (value & gfx_v9_4_ras_fields[i].ded_count_mask) >> 853 843 gfx_v9_4_ras_fields[i].ded_count_shift; 854 844 if (ded_cnt) { 855 - DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n", 845 + dev_info(adev->dev, 846 + "GFX SubBlock %s, Instance[%d][%d], DED %d\n", 856 847 gfx_v9_4_ras_fields[i].name, se_id, inst_id, 857 848 ded_cnt); 858 849 *ded_count += ded_cnt; ··· 887 876 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( 888 877 gfx_v9_4_edc_counter_regs[i])); 889 878 if (reg_value) 890 - gfx_v9_4_ras_error_count( 879 + gfx_v9_4_ras_error_count(adev, 891 880 &gfx_v9_4_edc_counter_regs[i], 892 881 j, k, reg_value, &sec_count, 893 882 &ded_count);
+8 -4
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
··· 690 690 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 0, 0, 0}, 691 691 }; 692 692 693 - static int mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry *reg, 693 + static int mmhub_v1_0_get_ras_error_count(struct amdgpu_device *adev, 694 + const struct soc15_reg_entry *reg, 694 695 uint32_t value, uint32_t *sec_count, uint32_t *ded_count) 695 696 { 696 697 uint32_t i; ··· 705 704 mmhub_v1_0_ras_fields[i].sec_count_mask) >> 706 705 mmhub_v1_0_ras_fields[i].sec_count_shift; 707 706 if (sec_cnt) { 708 - DRM_INFO("MMHUB SubBlock %s, SEC %d\n", 707 + dev_info(adev->dev, 708 + "MMHUB SubBlock %s, SEC %d\n", 709 709 mmhub_v1_0_ras_fields[i].name, 710 710 sec_cnt); 711 711 *sec_count += sec_cnt; ··· 716 714 mmhub_v1_0_ras_fields[i].ded_count_mask) >> 717 715 mmhub_v1_0_ras_fields[i].ded_count_shift; 718 716 if (ded_cnt) { 719 - DRM_INFO("MMHUB SubBlock %s, DED %d\n", 717 + dev_info(adev->dev, 718 + "MMHUB SubBlock %s, DED %d\n", 720 719 mmhub_v1_0_ras_fields[i].name, 721 720 ded_cnt); 722 721 *ded_count += ded_cnt; ··· 742 739 reg_value = 743 740 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); 744 741 if (reg_value) 745 - mmhub_v1_0_get_ras_error_count(&mmhub_v1_0_edc_cnt_regs[i], 742 + mmhub_v1_0_get_ras_error_count(adev, 743 + &mmhub_v1_0_edc_cnt_regs[i], 746 744 reg_value, &sec_count, &ded_count); 747 745 } 748 746