tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: OMAP: Make plat/fpga.h local to arch/arm/plat-omap
There's no need to have this file in plat/fpga.h. We can
make it local to plat-omap replacing fpga_read/write
functions directly with readb/writeb as that's how
they are already defined in fpga.h.
Note that 2420 based H4 is also using the fpga, so let's
keep the led support around in plat-omap until we flip
over mach-omap2 to device tree.
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: linux-fbdev@vger.kernel.org
Cc: Felipe Balbi <balbi@ti.com>
Cc: linux-usb@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
+216
-220
+3
-3
arch/arm/mach-omap1/board-fsample.c
+3
-3
arch/arm/mach-omap1/board-fsample.c
···
30
30
#include <plat/tc.h>
31
31
#include <mach/mux.h>
32
32
#include <mach/flash.h>
33
-
#include <plat/fpga.h>
33
+
#include <../plat-omap/fpga.h>
34
34
#include <linux/platform_data/keypad-omap.h>
35
35
36
36
#include <mach/hardware.h>
···
123
123
124
124
static void __init fsample_init_smc91x(void)
125
125
{
126
-
fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
126
+
__raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
127
127
mdelay(50);
128
-
fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
128
+
__raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
129
129
H2P2_DBG_FPGA_LAN_RESET);
130
130
mdelay(50);
131
131
}
+14
-12
arch/arm/mach-omap1/board-innovator.c
+14
-12
arch/arm/mach-omap1/board-innovator.c
···
33
33
34
34
#include <mach/mux.h>
35
35
#include <mach/flash.h>
36
-
#include <plat/fpga.h>
36
+
#include <../plat-omap/fpga.h>
37
37
#include <plat/tc.h>
38
38
#include <linux/platform_data/keypad-omap.h>
39
39
···
215
215
216
216
static int innovator_get_pendown_state(void)
217
217
{
218
-
return !(fpga_read(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5));
218
+
return !(__raw_readb(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5));
219
219
}
220
220
221
221
static const struct ads7846_platform_data innovator1510_ts_info = {
···
279
279
static void __init innovator_init_smc91x(void)
280
280
{
281
281
if (cpu_is_omap1510()) {
282
-
fpga_write(fpga_read(OMAP1510_FPGA_RST) & ~1,
282
+
__raw_writeb(__raw_readb(OMAP1510_FPGA_RST) & ~1,
283
283
OMAP1510_FPGA_RST);
284
284
udelay(750);
285
285
} else {
···
335
335
int vdd)
336
336
{
337
337
if (power_on)
338
-
fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
338
+
__raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) | (1 << 3),
339
339
OMAP1510_FPGA_POWER);
340
340
else
341
-
fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
341
+
__raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) & ~(1 << 3),
342
342
OMAP1510_FPGA_POWER);
343
343
344
344
return 0;
···
390
390
omap_cfg_reg(UART3_TX);
391
391
omap_cfg_reg(UART3_RX);
392
392
393
-
reg = fpga_read(OMAP1510_FPGA_POWER);
393
+
reg = __raw_readb(OMAP1510_FPGA_POWER);
394
394
reg |= OMAP1510_FPGA_PCR_COM1_EN;
395
-
fpga_write(reg, OMAP1510_FPGA_POWER);
395
+
__raw_writeb(reg, OMAP1510_FPGA_POWER);
396
396
udelay(10);
397
397
398
-
reg = fpga_read(OMAP1510_FPGA_POWER);
398
+
reg = __raw_readb(OMAP1510_FPGA_POWER);
399
399
reg |= OMAP1510_FPGA_PCR_COM2_EN;
400
-
fpga_write(reg, OMAP1510_FPGA_POWER);
400
+
__raw_writeb(reg, OMAP1510_FPGA_POWER);
401
401
udelay(10);
402
402
403
403
platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices));
···
437
437
*/
438
438
static void __init innovator_map_io(void)
439
439
{
440
+
#ifdef CONFIG_ARCH_OMAP15XX
440
441
omap15xx_map_io();
441
442
442
443
iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
···
445
444
446
445
/* Dump the Innovator FPGA rev early - useful info for support. */
447
446
pr_debug("Innovator FPGA Rev %d.%d Board Rev %d\n",
448
-
fpga_read(OMAP1510_FPGA_REV_HIGH),
449
-
fpga_read(OMAP1510_FPGA_REV_LOW),
450
-
fpga_read(OMAP1510_FPGA_BOARD_REV));
447
+
__raw_readb(OMAP1510_FPGA_REV_HIGH),
448
+
__raw_readb(OMAP1510_FPGA_REV_LOW),
449
+
__raw_readb(OMAP1510_FPGA_BOARD_REV));
450
+
#endif
451
451
}
452
452
453
453
MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
+3
-3
arch/arm/mach-omap1/board-perseus2.c
+3
-3
arch/arm/mach-omap1/board-perseus2.c
···
30
30
31
31
#include <plat/tc.h>
32
32
#include <mach/mux.h>
33
-
#include <plat/fpga.h>
33
+
#include <../plat-omap/fpga.h>
34
34
#include <mach/flash.h>
35
35
36
36
#include <mach/hardware.h>
···
231
231
232
232
static void __init perseus2_init_smc91x(void)
233
233
{
234
-
fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
234
+
__raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
235
235
mdelay(50);
236
-
fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
236
+
__raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
237
237
H2P2_DBG_FPGA_LAN_RESET);
238
238
mdelay(50);
239
239
}
+1
arch/arm/mach-omap1/common.h
+1
arch/arm/mach-omap1/common.h
+1
-1
arch/arm/mach-omap1/fpga.c
+1
-1
arch/arm/mach-omap1/fpga.c
+113
arch/arm/mach-omap1/include/mach/omap1510.h
+113
arch/arm/mach-omap1/include/mach/omap1510.h
···
45
45
46
46
#define OMAP1510_DSP_MMU_BASE (0xfffed200)
47
47
48
+
/*
49
+
* ---------------------------------------------------------------------------
50
+
* OMAP-1510 FPGA
51
+
* ---------------------------------------------------------------------------
52
+
*/
53
+
#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */
54
+
#define OMAP1510_FPGA_SIZE SZ_4K
55
+
#define OMAP1510_FPGA_START 0x08000000 /* PA */
56
+
57
+
/* Revision */
58
+
#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
59
+
#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
60
+
#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2)
61
+
#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3)
62
+
#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4)
63
+
#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5)
64
+
65
+
/* Interrupt status */
66
+
#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6)
67
+
#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7)
68
+
69
+
/* Interrupt mask */
70
+
#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8)
71
+
#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9)
72
+
73
+
/* Reset registers */
74
+
#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa)
75
+
#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb)
76
+
77
+
#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc)
78
+
#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe)
79
+
#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf)
80
+
#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14)
81
+
#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15)
82
+
#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16)
83
+
#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18)
84
+
#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c)
85
+
#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100)
86
+
#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101)
87
+
#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102)
88
+
89
+
#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204)
90
+
91
+
#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205)
92
+
#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206)
93
+
#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207)
94
+
#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208)
95
+
#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209)
96
+
#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a)
97
+
#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b)
98
+
#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d)
99
+
#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e)
100
+
#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210)
101
+
102
+
#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
103
+
104
+
/*
105
+
* Power up Giga UART driver, turn on HID clock.
106
+
* Turn off BT power, since we're not using it and it
107
+
* draws power.
108
+
*/
109
+
#define OMAP1510_FPGA_RESET_VALUE 0x42
110
+
111
+
#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
112
+
#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
113
+
#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
114
+
#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
115
+
#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
116
+
#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
117
+
#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
118
+
#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
119
+
120
+
/*
121
+
* Innovator/OMAP1510 FPGA HID register bit definitions
122
+
*/
123
+
#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
124
+
#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
125
+
#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
126
+
#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
127
+
#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
128
+
#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
129
+
#define OMAP1510_FPGA_HID_rsrvd (1<<6)
130
+
#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
131
+
132
+
/* The FPGA IRQ is cascaded through GPIO_13 */
133
+
#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
134
+
135
+
/* IRQ Numbers for interrupts muxed through the FPGA */
136
+
#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
137
+
#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
138
+
#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
139
+
#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
140
+
#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
141
+
#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
142
+
#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
143
+
#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
144
+
#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
145
+
#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
146
+
#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
147
+
#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
148
+
#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
149
+
#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
150
+
#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
151
+
#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
152
+
#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
153
+
#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
154
+
#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
155
+
#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
156
+
#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
157
+
#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
158
+
#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
159
+
#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
160
+
48
161
#endif /* __ASM_ARCH_OMAP15XX_H */
49
162
-1
arch/arm/mach-omap1/serial.c
-1
arch/arm/mach-omap1/serial.c
+1
-1
arch/arm/plat-omap/debug-leds.c
+1
-1
arch/arm/plat-omap/debug-leds.c
+74
arch/arm/plat-omap/fpga.h
+74
arch/arm/plat-omap/fpga.h
···
1
+
/*
2
+
* arch/arm/plat-omap/include/mach/fpga.h
3
+
*
4
+
* Interrupt handler for OMAP-1510 FPGA
5
+
*
6
+
* Copyright (C) 2001 RidgeRun, Inc.
7
+
* Author: Greg Lonnon <glonnon@ridgerun.com>
8
+
*
9
+
* Copyright (C) 2002 MontaVista Software, Inc.
10
+
*
11
+
* Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
12
+
* Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
13
+
*
14
+
* This program is free software; you can redistribute it and/or modify
15
+
* it under the terms of the GNU General Public License version 2 as
16
+
* published by the Free Software Foundation.
17
+
*/
18
+
19
+
#ifndef __ASM_ARCH_OMAP_FPGA_H
20
+
#define __ASM_ARCH_OMAP_FPGA_H
21
+
22
+
/*
23
+
* ---------------------------------------------------------------------------
24
+
* H2/P2 Debug board FPGA
25
+
* ---------------------------------------------------------------------------
26
+
*/
27
+
/* maps in the FPGA registers and the ETHR registers */
28
+
#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
29
+
#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
30
+
#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
31
+
32
+
#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
33
+
#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
34
+
#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
35
+
#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
36
+
#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
37
+
#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
38
+
#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
39
+
#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
40
+
41
+
/* NOTE: most boards don't have a static mapping for the FPGA ... */
42
+
struct h2p2_dbg_fpga {
43
+
/* offset 0x00 */
44
+
u16 smc91x[8];
45
+
/* offset 0x10 */
46
+
u16 fpga_rev;
47
+
u16 board_rev;
48
+
u16 gpio_outputs;
49
+
u16 leds;
50
+
/* offset 0x18 */
51
+
u16 misc_inputs;
52
+
u16 lan_status;
53
+
u16 lan_reset;
54
+
u16 reserved0;
55
+
/* offset 0x20 */
56
+
u16 ps2_data;
57
+
u16 ps2_ctrl;
58
+
/* plus also 4 rs232 ports ... */
59
+
};
60
+
61
+
/* LEDs definition on debug board (16 LEDs, all physically green) */
62
+
#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
63
+
#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
64
+
#define H2P2_DBG_FPGA_LED_RED (1 << 13)
65
+
#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
66
+
/* cpu0 load-meter LEDs */
67
+
#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
68
+
#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
69
+
#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
70
+
71
+
#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
72
+
#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
73
+
74
+
#endif
-193
arch/arm/plat-omap/include/plat/fpga.h
-193
arch/arm/plat-omap/include/plat/fpga.h
···
1
-
/*
2
-
* arch/arm/plat-omap/include/mach/fpga.h
3
-
*
4
-
* Interrupt handler for OMAP-1510 FPGA
5
-
*
6
-
* Copyright (C) 2001 RidgeRun, Inc.
7
-
* Author: Greg Lonnon <glonnon@ridgerun.com>
8
-
*
9
-
* Copyright (C) 2002 MontaVista Software, Inc.
10
-
*
11
-
* Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
12
-
* Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
13
-
*
14
-
* This program is free software; you can redistribute it and/or modify
15
-
* it under the terms of the GNU General Public License version 2 as
16
-
* published by the Free Software Foundation.
17
-
*/
18
-
19
-
#ifndef __ASM_ARCH_OMAP_FPGA_H
20
-
#define __ASM_ARCH_OMAP_FPGA_H
21
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22
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extern void omap1510_fpga_init_irq(void);
23
-
24
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#define fpga_read(reg) __raw_readb(reg)
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#define fpga_write(val, reg) __raw_writeb(val, reg)
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-
27
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/*
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* ---------------------------------------------------------------------------
29
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* H2/P2 Debug board FPGA
30
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* ---------------------------------------------------------------------------
31
-
*/
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/* maps in the FPGA registers and the ETHR registers */
33
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#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
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#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
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#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
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#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
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#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
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#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
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#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
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#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
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#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
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#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
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#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
45
-
46
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/* NOTE: most boards don't have a static mapping for the FPGA ... */
47
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struct h2p2_dbg_fpga {
48
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/* offset 0x00 */
49
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u16 smc91x[8];
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/* offset 0x10 */
51
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u16 fpga_rev;
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u16 board_rev;
53
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u16 gpio_outputs;
54
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u16 leds;
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/* offset 0x18 */
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u16 misc_inputs;
57
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u16 lan_status;
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u16 lan_reset;
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u16 reserved0;
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/* offset 0x20 */
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u16 ps2_data;
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u16 ps2_ctrl;
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/* plus also 4 rs232 ports ... */
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};
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-
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/* LEDs definition on debug board (16 LEDs, all physically green) */
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#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
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#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
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#define H2P2_DBG_FPGA_LED_RED (1 << 13)
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#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
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/* cpu0 load-meter LEDs */
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#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
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#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
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#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
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-
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#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
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#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
78
-
79
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/*
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* ---------------------------------------------------------------------------
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* OMAP-1510 FPGA
82
-
* ---------------------------------------------------------------------------
83
-
*/
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#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */
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#define OMAP1510_FPGA_SIZE SZ_4K
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#define OMAP1510_FPGA_START 0x08000000 /* PA */
87
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88
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/* Revision */
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#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
90
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#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
91
-
92
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#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2)
93
-
#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3)
94
-
#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4)
95
-
#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5)
96
-
97
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/* Interrupt status */
98
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#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6)
99
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#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7)
100
-
101
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/* Interrupt mask */
102
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#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8)
103
-
#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9)
104
-
105
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/* Reset registers */
106
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#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa)
107
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#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb)
108
-
109
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#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc)
110
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#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe)
111
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#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf)
112
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#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14)
113
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#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15)
114
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#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16)
115
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#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18)
116
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#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100)
117
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#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101)
118
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#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102)
119
-
120
-
#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204)
121
-
122
-
#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205)
123
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#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206)
124
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#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207)
125
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#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208)
126
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#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209)
127
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#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a)
128
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#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b)
129
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#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c)
130
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#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d)
131
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#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e)
132
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#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210)
133
-
134
-
#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
135
-
136
-
/*
137
-
* Power up Giga UART driver, turn on HID clock.
138
-
* Turn off BT power, since we're not using it and it
139
-
* draws power.
140
-
*/
141
-
#define OMAP1510_FPGA_RESET_VALUE 0x42
142
-
143
-
#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
144
-
#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
145
-
#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
146
-
#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
147
-
#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
148
-
#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
149
-
#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
150
-
#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
151
-
152
-
/*
153
-
* Innovator/OMAP1510 FPGA HID register bit definitions
154
-
*/
155
-
#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
156
-
#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
157
-
#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
158
-
#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
159
-
#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
160
-
#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
161
-
#define OMAP1510_FPGA_HID_rsrvd (1<<6)
162
-
#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
163
-
164
-
/* The FPGA IRQ is cascaded through GPIO_13 */
165
-
#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
166
-
167
-
/* IRQ Numbers for interrupts muxed through the FPGA */
168
-
#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
169
-
#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
170
-
#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
171
-
#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
172
-
#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
173
-
#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
174
-
#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
175
-
#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
176
-
#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
177
-
#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
178
-
#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
179
-
#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
180
-
#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
181
-
#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
182
-
#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
183
-
#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
184
-
#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
185
-
#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
186
-
#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
187
-
#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
188
-
#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
189
-
#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
190
-
#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
191
-
#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
192
-
193
-
#endif
+2
-3
drivers/usb/host/ohci-omap.c
+2
-3
drivers/usb/host/ohci-omap.c
···
25
25
#include <asm/mach-types.h>
26
26
27
27
#include <mach/mux.h>
28
-
#include <plat/fpga.h>
29
28
30
29
#include <mach/hardware.h>
31
30
#include <mach/irqs.h>
···
92
93
{
93
94
if (on) {
94
95
if (machine_is_omap_innovator() && cpu_is_omap1510())
95
-
fpga_write(fpga_read(INNOVATOR_FPGA_CAM_USB_CONTROL)
96
+
__raw_writeb(__raw_readb(INNOVATOR_FPGA_CAM_USB_CONTROL)
96
97
| ((1 << 5/*usb1*/) | (1 << 3/*usb2*/)),
97
98
INNOVATOR_FPGA_CAM_USB_CONTROL);
98
99
else if (machine_is_omap_osk())
99
100
tps65010_set_gpio_out_value(GPIO1, LOW);
100
101
} else {
101
102
if (machine_is_omap_innovator() && cpu_is_omap1510())
102
-
fpga_write(fpga_read(INNOVATOR_FPGA_CAM_USB_CONTROL)
103
+
__raw_writeb(__raw_readb(INNOVATOR_FPGA_CAM_USB_CONTROL)
103
104
& ~((1 << 5/*usb1*/) | (1 << 3/*usb2*/)),
104
105
INNOVATOR_FPGA_CAM_USB_CONTROL);
105
106
else if (machine_is_omap_osk())
+4
-3
drivers/video/omap/lcd_inn1510.c
+4
-3
drivers/video/omap/lcd_inn1510.c
···
23
23
#include <linux/platform_device.h>
24
24
#include <linux/io.h>
25
25
26
-
#include <plat/fpga.h>
26
+
#include <mach/hardware.h>
27
+
27
28
#include "omapfb.h"
28
29
29
30
static int innovator1510_panel_init(struct lcd_panel *panel,
···
39
38
40
39
static int innovator1510_panel_enable(struct lcd_panel *panel)
41
40
{
42
-
fpga_write(0x7, OMAP1510_FPGA_LCD_PANEL_CONTROL);
41
+
__raw_writeb(0x7, OMAP1510_FPGA_LCD_PANEL_CONTROL);
43
42
return 0;
44
43
}
45
44
46
45
static void innovator1510_panel_disable(struct lcd_panel *panel)
47
46
{
48
-
fpga_write(0x0, OMAP1510_FPGA_LCD_PANEL_CONTROL);
47
+
__raw_writeb(0x0, OMAP1510_FPGA_LCD_PANEL_CONTROL);
49
48
}
50
49
51
50
static unsigned long innovator1510_panel_get_caps(struct lcd_panel *panel)