tjh.dev / kernel
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Merge branch 'pci-mrrs-consts'

Heiner Kallweit says:

====================
PCI: add two more values for PCIe Max_Read_Request_Size and initially use them in r8169 network driver

In r8169 network driver I stumbled across a magic number translating
to PCI MRRS size 4K. The PCI core is still missing constants for
values 2K and 4K (as defined in PCI standard).

So let's add these two constants and use the 4K constant in r8169.

Second patch depends on the first one, therefore both patches
preferrably should go through either PCI or netdev tree.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

David S. Miller 4c85d2d4 5da8baa3

+21 -20
+19 -20
drivers/net/ethernet/realtek/r8169.c
··· 84 84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 85 85 static const int multicast_filter_limit = 32; 86 86 87 - #define MAX_READ_REQUEST_SHIFT 12 88 87 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 89 88 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 90 89 ··· 5124 5125 { 5125 5126 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 5126 5127 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 5127 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5128 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5128 5129 } 5129 5130 5130 5131 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) ··· 5150 5151 RTL_W8(tp, MaxTxPacketSize, 0x0c); 5151 5152 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 5152 5153 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 5153 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5154 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5154 5155 } 5155 5156 5156 5157 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) ··· 5162 5163 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) 5163 5164 { 5164 5165 rtl_tx_performance_tweak(tp, 5165 - (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); 5166 + PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN); 5166 5167 } 5167 5168 5168 5169 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) ··· 5735 5736 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 5736 5737 5737 5738 if (tp->dev->mtu <= ETH_DATA_LEN) { 5738 - rtl_tx_performance_tweak(tp, (0x5 << MAX_READ_REQUEST_SHIFT) | 5739 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B | 5739 5740 PCI_EXP_DEVCTL_NOSNOOP_EN); 5740 5741 } 5741 5742 } ··· 5756 5757 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5757 5758 5758 5759 if (tp->dev->mtu <= ETH_DATA_LEN) 5759 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5760 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5760 5761 5761 5762 rtl_disable_clock_request(tp); 5762 5763 ··· 5787 5788 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5788 5789 5789 5790 if (tp->dev->mtu <= ETH_DATA_LEN) 5790 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5791 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5791 5792 5792 5793 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 5793 5794 } ··· 5804 5805 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5805 5806 5806 5807 if (tp->dev->mtu <= ETH_DATA_LEN) 5807 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5808 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5808 5809 5809 5810 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 5810 5811 } ··· 5861 5862 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5862 5863 5863 5864 if (tp->dev->mtu <= ETH_DATA_LEN) 5864 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5865 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5865 5866 5866 5867 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 5867 5868 } ··· 5871 5872 rtl_csi_access_enable_1(tp); 5872 5873 5873 5874 if (tp->dev->mtu <= ETH_DATA_LEN) 5874 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5875 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5875 5876 5876 5877 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5877 5878 ··· 5888 5889 5889 5890 rtl_csi_access_enable_1(tp); 5890 5891 5891 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5892 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5892 5893 5893 5894 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5894 5895 ··· 5920 5921 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); 5921 5922 5922 5923 if (tp->dev->mtu <= ETH_DATA_LEN) 5923 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5924 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5924 5925 5925 5926 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5926 5927 ··· 5945 5946 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); 5946 5947 5947 5948 if (tp->dev->mtu <= ETH_DATA_LEN) 5948 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5949 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5949 5950 5950 5951 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); 5951 5952 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); ··· 5975 5976 { 5976 5977 rtl_csi_access_enable_2(tp); 5977 5978 5978 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 5979 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5979 5980 5980 5981 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); 5981 5982 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); ··· 6046 6047 6047 6048 rtl_csi_access_enable_1(tp); 6048 6049 6049 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 6050 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 6050 6051 6051 6052 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); 6052 6053 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); ··· 6146 6147 6147 6148 rtl_csi_access_enable_1(tp); 6148 6149 6149 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 6150 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 6150 6151 6151 6152 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); 6152 6153 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); ··· 6228 6229 6229 6230 rtl_csi_access_enable_1(tp); 6230 6231 6231 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 6232 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 6232 6233 6233 6234 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); 6234 6235 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); ··· 6494 6495 6495 6496 RTL_W8(tp, DBG_REG, FIX_NAK_1); 6496 6497 6497 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 6498 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 6498 6499 6499 6500 RTL_W8(tp, Config1, 6500 6501 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); ··· 6511 6512 { 6512 6513 rtl_csi_access_enable_2(tp); 6513 6514 6514 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 6515 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 6515 6516 6516 6517 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 6517 6518 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); ··· 6574 6575 6575 6576 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402)); 6576 6577 6577 - rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT); 6578 + rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 6578 6579 6579 6580 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC); 6580 6581 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
+2
include/uapi/linux/pci_regs.h
··· 506 506 #define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */ 507 507 #define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */ 508 508 #define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */ 509 + #define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */ 510 + #define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */ 509 511 #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ 510 512 #define PCI_EXP_DEVSTA 10 /* Device Status */ 511 513 #define PCI_EXP_DEVSTA_CED 0x0001 /* Correctable Error Detected */