arch/*/io.h: Add ioremap_uc() to all architectures

This adds ioremap_uc() only for architectures that do not
include asm-generic.h/io.h as that already provides a default
definition for them for both cases where you have CONFIG_MMU
and you do not, and because of this, the number of architectures
this patch address is less than the architectures that the
ioremap_wt() patch addressed, "arch/*/io.h: Add ioremap_wt() to
all architectures").

In order to reduce the number of architectures we have to
modify by adding new architecture IO APIs we'll have to review
the architectures in this patch, see why they can't add
asm-generic.h/io.h or issues that would be created by doing
so and then spread a consistent inclusion of this header
towards the end of their own header. For instance arch/metag
includes the asm-generic/io.h *before* the ioremap*()
definitions, this should be the other way around but only
once we have guard wrappers for the non-MMU case also for
asm-generic/io.h.

Reported-by: Stephen Rothwell <[e-mail]>
Signed-off-by: Luis R. Rodriguez <[e-mail]>
Cc: Abhilash Kesavan <[e-mail]>
Cc: Benjamin Herrenschmidt <[e-mail]>
Cc: Borislav Petkov <[e-mail]>
Cc: Chris Metcalf <[e-mail]>
Cc: David Howells <[e-mail]>
Cc: Fengguang Wu <[e-mail]>
Cc: Geert Uytterhoeven <[e-mail]>
Cc: Greg Kroah-Hartman <[e-mail]>
Cc: Greg Ungerer <[e-mail]>
Cc: Guenter Roeck <[e-mail]>
Cc: Haavard Skinnemoen <[e-mail]>
Cc: Hans-Christian Egtvedt <[e-mail]>
Cc: Koichi Yasutake <[e-mail]>
Cc: Kyle McMartin <[e-mail]>
Cc: Linus Torvalds <[e-mail]>
Cc: Michael Ellerman <[e-mail]>
Cc: Paul Mackerras <[e-mail]>
Cc: Peter Hurley <[e-mail]>
Cc: Peter Zijlstra <[e-mail]>
Cc: Rob Herring <[e-mail]>
Cc: Thomas Gleixner <[e-mail]>
Cc: Toshi Kani <[e-mail]>
Cc: Will Deacon <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
Link: http://lkml.kernel.org/r/[e-mail]
Signed-off-by: Ingo Molnar <[e-mail]>

arch/avr32/include/asm/io.h

···
 
 #define ioremap_wc ioremap_nocache
 #define ioremap_wt ioremap_nocache
+#define ioremap_uc ioremap_nocache
 
 #define cached(addr) P1SEGADDR(addr)
 #define uncached(addr) P2SEGADDR(addr)

arch/frv/include/asm/io.h

···
 }
 
 #define ioremap_wc ioremap_nocache
+#define ioremap_uc ioremap_nocache
 
 extern void iounmap(void volatile __iomem *addr);
 

arch/m32r/include/asm/io.h

···
 #define ioremap_nocache(off,size) ioremap(off,size)
 #define ioremap_wc ioremap_nocache
 #define ioremap_wt ioremap_nocache
+#define ioremap_uc ioremap_nocache
 
 /*
  * IO bus memory addresses are also 1:1 with the physical address

arch/m68k/include/asm/io_mm.h

···
 {
 	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
 }
+#define ioremap_uc ioremap_nocache
 static inline void __iomem *ioremap_wt(unsigned long physaddr,
 					 unsigned long size)
 {

arch/mn10300/include/asm/io.h

···
 
 #define ioremap_wc ioremap_nocache
 #define ioremap_wt ioremap_nocache
+#define ioremap_uc ioremap_nocache
 
 static inline void iounmap(void __iomem *addr)
 {

arch/powerpc/include/asm/io.h

···
 				  unsigned long flags);
 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
 #define ioremap_nocache(addr, size)	ioremap((addr), (size))
+#define ioremap_uc(addr, size)		ioremap((addr), (size))
 
 extern void iounmap(volatile void __iomem *addr);
 

arch/sh/include/asm/io.h

···
 #endif
 
 #define ioremap_nocache	ioremap
+#define ioremap_uc	ioremap
 #define iounmap		__iounmap
 
 /*

arch/tile/include/asm/io.h

···
 #define ioremap_nocache(physaddr, size)		ioremap(physaddr, size)
 #define ioremap_wc(physaddr, size)		ioremap(physaddr, size)
 #define ioremap_wt(physaddr, size)		ioremap(physaddr, size)
+#define ioremap_uc(physaddr, size)		ioremap(physaddr, size)
 #define ioremap_fullcache(physaddr, size)	ioremap(physaddr, size)
 
 #define mmiowb()