Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'for-linus' of git://github.com/openrisc/linux

Pull OpenRISC updates from Stafford Horne:
"One change to simplify Litex CSR (MMIO register) access by limiting
them to 32-bit offsets.

Now that this is agreed on among Litex hardware and kernel developers
it will allow us to start upstreaming other Litex peripheral drivers"

* tag 'for-linus' of git://github.com/openrisc/linux:
drivers/soc/litex: remove 8-bit subregister option

+16 -102
-12
drivers/soc/litex/Kconfig
··· 17 17 All drivers that use functions from litex.h must depend on 18 18 LITEX. 19 19 20 - config LITEX_SUBREG_SIZE 21 - int "Size of a LiteX CSR subregister, in bytes" 22 - depends on LITEX 23 - range 1 4 24 - default 4 25 - help 26 - LiteX MMIO registers (referred to as Configuration and Status 27 - registers, or CSRs) are spread across adjacent 8- or 32-bit 28 - subregisters, located at 32-bit aligned MMIO addresses. Use 29 - this to select the appropriate size (1 or 4 bytes) matching 30 - your particular LiteX build. 31 - 32 20 endmenu
+1 -2
drivers/soc/litex/litex_soc_ctrl.c
··· 62 62 /* restore original value of the SCRATCH register */ 63 63 litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_VALUE); 64 64 65 - pr_info("LiteX SoC Controller driver initialized: subreg:%d, align:%d", 66 - LITEX_SUBREG_SIZE, LITEX_SUBREG_ALIGN); 65 + pr_info("LiteX SoC Controller driver initialized"); 67 66 68 67 return 0; 69 68 }
+15 -88
include/linux/litex.h
··· 11 11 12 12 #include <linux/io.h> 13 13 14 - /* LiteX SoCs support 8- or 32-bit CSR Bus data width (i.e., subreg. size) */ 15 - #if defined(CONFIG_LITEX_SUBREG_SIZE) && \ 16 - (CONFIG_LITEX_SUBREG_SIZE == 1 || CONFIG_LITEX_SUBREG_SIZE == 4) 17 - #define LITEX_SUBREG_SIZE CONFIG_LITEX_SUBREG_SIZE 18 - #else 19 - #error LiteX subregister size (LITEX_SUBREG_SIZE) must be 4 or 1! 20 - #endif 21 - #define LITEX_SUBREG_SIZE_BIT (LITEX_SUBREG_SIZE * 8) 22 - 23 - /* LiteX subregisters of any width are always aligned on a 4-byte boundary */ 24 - #define LITEX_SUBREG_ALIGN 0x4 25 - 26 14 static inline void _write_litex_subregister(u32 val, void __iomem *addr) 27 15 { 28 16 writel((u32 __force)cpu_to_le32(val), addr); ··· 30 42 * 32-bit wide logical CSR will be laid out as four 32-bit physical 31 43 * subregisters, each one containing one byte of meaningful data. 32 44 * 45 + * For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which 46 + * means that only larger-than-32-bit CSRs will be split across multiple 47 + * subregisters (e.g., a 64-bit CSR will be spread across two consecutive 48 + * 32-bit subregisters). 49 + * 33 50 * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus 34 51 */ 35 52 36 - /* number of LiteX subregisters needed to store a register of given reg_size */ 37 - #define _litex_num_subregs(reg_size) \ 38 - (((reg_size) - 1) / LITEX_SUBREG_SIZE + 1) 39 - 40 - /* 41 - * since the number of 4-byte aligned subregisters required to store a single 42 - * LiteX CSR (MMIO) register varies with LITEX_SUBREG_SIZE, the offset of the 43 - * next adjacent LiteX CSR register w.r.t. the offset of the current one also 44 - * depends on how many subregisters the latter is spread across 45 - */ 46 - #define _next_reg_off(off, size) \ 47 - ((off) + _litex_num_subregs(size) * LITEX_SUBREG_ALIGN) 48 - 49 - /* 50 - * The purpose of `_litex_[set|get]_reg()` is to implement the logic of 51 - * writing to/reading from the LiteX CSR in a single place that can be then 52 - * reused by all LiteX drivers via the `litex_[write|read][8|16|32|64]()` 53 - * accessors for the appropriate data width. 54 - * NOTE: direct use of `_litex_[set|get]_reg()` by LiteX drivers is strongly 55 - * discouraged, as they perform no error checking on the requested data width! 56 - */ 57 - 58 - /** 59 - * _litex_set_reg() - Writes a value to the LiteX CSR (Control&Status Register) 60 - * @reg: Address of the CSR 61 - * @reg_size: The width of the CSR expressed in the number of bytes 62 - * @val: Value to be written to the CSR 63 - * 64 - * This function splits a single (possibly multi-byte) LiteX CSR write into 65 - * a series of subregister writes with a proper offset. 66 - * NOTE: caller is responsible for ensuring (0 < reg_size <= sizeof(u64)). 67 - */ 68 - static inline void _litex_set_reg(void __iomem *reg, size_t reg_size, u64 val) 69 - { 70 - u8 shift = _litex_num_subregs(reg_size) * LITEX_SUBREG_SIZE_BIT; 71 - 72 - while (shift > 0) { 73 - shift -= LITEX_SUBREG_SIZE_BIT; 74 - _write_litex_subregister(val >> shift, reg); 75 - reg += LITEX_SUBREG_ALIGN; 76 - } 77 - } 78 - 79 - /** 80 - * _litex_get_reg() - Reads a value of the LiteX CSR (Control&Status Register) 81 - * @reg: Address of the CSR 82 - * @reg_size: The width of the CSR expressed in the number of bytes 83 - * 84 - * Return: Value read from the CSR 85 - * 86 - * This function generates a series of subregister reads with a proper offset 87 - * and joins their results into a single (possibly multi-byte) LiteX CSR value. 88 - * NOTE: caller is responsible for ensuring (0 < reg_size <= sizeof(u64)). 89 - */ 90 - static inline u64 _litex_get_reg(void __iomem *reg, size_t reg_size) 91 - { 92 - u64 r; 93 - u8 i; 94 - 95 - r = _read_litex_subregister(reg); 96 - for (i = 1; i < _litex_num_subregs(reg_size); i++) { 97 - r <<= LITEX_SUBREG_SIZE_BIT; 98 - reg += LITEX_SUBREG_ALIGN; 99 - r |= _read_litex_subregister(reg); 100 - } 101 - return r; 102 - } 103 - 104 53 static inline void litex_write8(void __iomem *reg, u8 val) 105 54 { 106 - _litex_set_reg(reg, sizeof(u8), val); 55 + _write_litex_subregister(val, reg); 107 56 } 108 57 109 58 static inline void litex_write16(void __iomem *reg, u16 val) 110 59 { 111 - _litex_set_reg(reg, sizeof(u16), val); 60 + _write_litex_subregister(val, reg); 112 61 } 113 62 114 63 static inline void litex_write32(void __iomem *reg, u32 val) 115 64 { 116 - _litex_set_reg(reg, sizeof(u32), val); 65 + _write_litex_subregister(val, reg); 117 66 } 118 67 119 68 static inline void litex_write64(void __iomem *reg, u64 val) 120 69 { 121 - _litex_set_reg(reg, sizeof(u64), val); 70 + _write_litex_subregister(val >> 32, reg); 71 + _write_litex_subregister(val, reg + 4); 122 72 } 123 73 124 74 static inline u8 litex_read8(void __iomem *reg) 125 75 { 126 - return _litex_get_reg(reg, sizeof(u8)); 76 + return _read_litex_subregister(reg); 127 77 } 128 78 129 79 static inline u16 litex_read16(void __iomem *reg) 130 80 { 131 - return _litex_get_reg(reg, sizeof(u16)); 81 + return _read_litex_subregister(reg); 132 82 } 133 83 134 84 static inline u32 litex_read32(void __iomem *reg) 135 85 { 136 - return _litex_get_reg(reg, sizeof(u32)); 86 + return _read_litex_subregister(reg); 137 87 } 138 88 139 89 static inline u64 litex_read64(void __iomem *reg) 140 90 { 141 - return _litex_get_reg(reg, sizeof(u64)); 91 + return ((u64)_read_litex_subregister(reg) << 32) | 92 + _read_litex_subregister(reg + 4); 142 93 } 143 94 144 95 #endif /* _LINUX_LITEX_H */