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dt-bindings: clock: convert lpc1850-ccu.txt to yaml format
Convert lpc1850-ccu.txt to yaml format.
Additional changes:
- remove label in examples.
- remove clock consumer in examples.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250602141937.942091-1-Frank.Li@nxp.com
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Frank Li
and committed by
Stephen Boyd
4c559366
2e090ae6
+104
-77
-77
Documentation/devicetree/bindings/clock/lpc1850-ccu.txt
-77
Documentation/devicetree/bindings/clock/lpc1850-ccu.txt
···
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* NXP LPC1850 Clock Control Unit (CCU)
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Each CGU base clock has several clock branches which can be turned on
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or off independently by the Clock Control Units CCU1 or CCU2. The
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branch clocks are distributed between CCU1 and CCU2.
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- Above text taken from NXP LPC1850 User Manual.
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible:
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Should be "nxp,lpc1850-ccu"
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- reg:
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Shall define the base and range of the address space
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containing clock control registers
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- #clock-cells:
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Shall have value <1>. The permitted clock-specifier values
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are the branch clock names defined in table below.
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- clocks:
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Shall contain a list of phandles for the base clocks routed
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from the CGU to the specific CCU. See mapping of base clocks
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and CCU in table below.
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- clock-names:
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Shall contain a list of names for the base clock routed
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from the CGU to the specific CCU. Valid CCU clock names:
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"base_usb0_clk", "base_periph_clk", "base_usb1_clk",
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"base_cpu_clk", "base_spifi_clk", "base_spi_clk",
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"base_apb1_clk", "base_apb3_clk", "base_adchs_clk",
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"base_sdio_clk", "base_ssp0_clk", "base_ssp1_clk",
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"base_uart0_clk", "base_uart1_clk", "base_uart2_clk",
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"base_uart3_clk", "base_audio_clk"
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Which branch clocks that are available on the CCU depends on the
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specific LPC part. Check the user manual for your specific part.
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A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
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Example board file:
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soc {
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ccu1: clock-controller@40051000 {
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compatible = "nxp,lpc1850-ccu";
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reg = <0x40051000 0x1000>;
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#clock-cells = <1>;
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clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
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<&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
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<&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
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<&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
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clock-names = "base_apb3_clk", "base_apb1_clk",
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"base_spifi_clk", "base_cpu_clk",
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"base_periph_clk", "base_usb0_clk",
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"base_usb1_clk", "base_spi_clk";
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};
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ccu2: clock-controller@40052000 {
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compatible = "nxp,lpc1850-ccu";
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reg = <0x40052000 0x1000>;
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#clock-cells = <1>;
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clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
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<&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
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<&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
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<&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
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clock-names = "base_audio_clk", "base_uart3_clk",
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"base_uart2_clk", "base_uart1_clk",
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"base_uart0_clk", "base_ssp1_clk",
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"base_ssp0_clk", "base_sdio_clk";
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};
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/* A user of CCU branch clocks */
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uart1: serial@40082000 {
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...
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clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
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...
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};
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};
+104
Documentation/devicetree/bindings/clock/nxp,lpc1850-ccu.yaml
+104
Documentation/devicetree/bindings/clock/nxp,lpc1850-ccu.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/nxp,lpc1850-ccu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP LPC1850 Clock Control Unit (CCU)
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description:
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Each CGU base clock has several clock branches which can be turned on
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or off independently by the Clock Control Units CCU1 or CCU2. The
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branch clocks are distributed between CCU1 and CCU2.
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Above text taken from NXP LPC1850 User Manual
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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properties:
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compatible:
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const: nxp,lpc1850-ccu
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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minItems: 1
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maxItems: 8
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clock-names:
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minItems: 1
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maxItems: 8
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items:
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enum:
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- base_usb0_clk
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- base_periph_clk
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- base_usb1_clk
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- base_cpu_clk
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- base_spifi_clk
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- base_spi_clk
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- base_apb1_clk
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- base_apb3_clk
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- base_adchs_clk
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- base_sdio_clk
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- base_ssp0_clk
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- base_ssp1_clk
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- base_uart0_clk
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- base_uart1_clk
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- base_uart2_clk
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- base_uart3_clk
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- base_audio_clk
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description:
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Which branch clocks that are available on the CCU depends on the
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specific LPC part. Check the user manual for your specific part.
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A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
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required:
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- compatible
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- reg
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- '#clock-cells'
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/lpc18xx-cgu.h>
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clock-controller@40051000 {
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compatible = "nxp,lpc1850-ccu";
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reg = <0x40051000 0x1000>;
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#clock-cells = <1>;
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clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
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<&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
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<&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
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<&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
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clock-names = "base_apb3_clk", "base_apb1_clk",
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"base_spifi_clk", "base_cpu_clk",
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"base_periph_clk", "base_usb0_clk",
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"base_usb1_clk", "base_spi_clk";
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};
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- |
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#include <dt-bindings/clock/lpc18xx-cgu.h>
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clock-controller@40052000 {
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compatible = "nxp,lpc1850-ccu";
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reg = <0x40052000 0x1000>;
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#clock-cells = <1>;
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clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
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<&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
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<&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
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<&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
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clock-names = "base_audio_clk", "base_uart3_clk",
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"base_uart2_clk", "base_uart1_clk",
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"base_uart0_clk", "base_ssp1_clk",
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"base_ssp0_clk", "base_sdio_clk";
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};
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