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kernel os linux

dt-bindings: mfd: syscon: Add more simple compatibles

Add another batch of various "simple" syscon compatibles which were
undocumented or still documented with old text bindings. Remove the old
text binding docs for the ones which were documented.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> # mtd
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240603131230.136196-2-robh@kernel.org
Signed-off-by: Lee Jones <lee@kernel.org>

authored by

Rob Herring (Arm) and committed by
Lee Jones
4c4ade1a 9cc3b409

+29 -221
-20
Documentation/devicetree/bindings/arm/amlogic/analog-top.txt
··· 1 - Amlogic Meson8 and Meson8b "analog top" registers: 2 - -------------------------------------------------- 3 - 4 - The analog top registers contain information about the so-called 5 - "metal revision" (which encodes the "minor version") of the SoC. 6 - 7 - Required properties: 8 - - reg: the register range of the analog top registers 9 - - compatible: depending on the SoC this should be one of: 10 - - "amlogic,meson8-analog-top" 11 - - "amlogic,meson8b-analog-top" 12 - along with "syscon" 13 - 14 - 15 - Example: 16 - 17 - analog_top: analog-top@81a8 { 18 - compatible = "amlogic,meson8-analog-top", "syscon"; 19 - reg = <0x81a8 0x14>; 20 - };
-17
Documentation/devicetree/bindings/arm/amlogic/assist.txt
··· 1 - Amlogic Meson6/Meson8/Meson8b assist registers: 2 - ----------------------------------------------- 3 - 4 - The assist registers contain basic information about the SoC, 5 - for example the encoded SoC part number. 6 - 7 - Required properties: 8 - - reg: the register range of the assist registers 9 - - compatible: should be "amlogic,meson-mx-assist" along with "syscon" 10 - 11 - 12 - Example: 13 - 14 - assist: assist@7c00 { 15 - compatible = "amlogic,meson-mx-assist", "syscon"; 16 - reg = <0x7c00 0x200>; 17 - };
-17
Documentation/devicetree/bindings/arm/amlogic/bootrom.txt
··· 1 - Amlogic Meson6/Meson8/Meson8b bootrom: 2 - -------------------------------------- 3 - 4 - The bootrom register area can be used to access SoC specific 5 - information, such as the "misc version". 6 - 7 - Required properties: 8 - - reg: the register range of the bootrom registers 9 - - compatible: should be "amlogic,meson-mx-bootrom" along with "syscon" 10 - 11 - 12 - Example: 13 - 14 - bootrom: bootrom@d9040000 { 15 - compatible = "amlogic,meson-mx-bootrom", "syscon"; 16 - reg = <0xd9040000 0x10000>; 17 - };
-18
Documentation/devicetree/bindings/arm/amlogic/pmu.txt
··· 1 - Amlogic Meson8 and Meson8b power-management-unit: 2 - ------------------------------------------------- 3 - 4 - The pmu is used to turn off and on different power domains of the SoCs 5 - This includes the power to the CPU cores. 6 - 7 - Required node properties: 8 - - compatible value : depending on the SoC this should be one of: 9 - "amlogic,meson8-pmu" 10 - "amlogic,meson8b-pmu" 11 - - reg : physical base address and the size of the registers window 12 - 13 - Example: 14 - 15 - pmu@c81000e4 { 16 - compatible = "amlogic,meson8b-pmu", "syscon"; 17 - reg = <0xc81000e0 0x18>; 18 - };
-29
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
··· 41 41 reg = <0xffffe800 0x200>; 42 42 }; 43 43 44 - RAMC PHY Controller required properties: 45 - - compatible: Should be "microchip,sama7g5-ddr3phy", "syscon" 46 - - reg: Should contain registers location and length 47 - 48 - Example: 49 - 50 - ddr3phy: ddr3phy@e3804000 { 51 - compatible = "microchip,sama7g5-ddr3phy", "syscon"; 52 - reg = <0xe3804000 0x1000>; 53 - }; 54 - 55 - Special Function Registers (SFR) 56 - 57 - Special Function Registers (SFR) manage specific aspects of the integrated 58 - memory, bridge implementations, processor and other functionality not controlled 59 - elsewhere. 60 - 61 - required properties: 62 - - compatible: Should be "atmel,<chip>-sfr", "syscon" or 63 - "atmel,<chip>-sfrbu", "syscon" 64 - <chip> can be "sama5d3", "sama5d4" or "sama5d2". 65 - It also can be "microchip,sam9x60-sfr", "syscon". 66 - - reg: Should contain registers location and length 67 - 68 - sfr@f0038000 { 69 - compatible = "atmel,sama5d3-sfr", "syscon"; 70 - reg = <0xf0038000 0x60>; 71 - }; 72 - 73 44 Security Module (SECUMOD) 74 45 75 46 The Security Module macrocell provides all necessary secure functions to avoid
-16
Documentation/devicetree/bindings/arm/axis.txt
··· 7 7 Required root node properties: 8 8 - compatible = "axis,artpec6"; 9 9 10 - ARTPEC-6 System Controller 11 - -------------------------- 12 - 13 - The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe 14 - and resets. 15 - 16 - Required properties: 17 - - compatible: "axis,artpec6-syscon", "syscon" 18 - - reg: Address and length of the register bank. 19 - 20 - Example: 21 - syscon { 22 - compatible = "axis,artpec6-syscon", "syscon"; 23 - reg = <0xf8000000 0x48>; 24 - }; 25 - 26 10 ARTPEC-6 Development board: 27 11 --------------------------- 28 12 Required root node properties:
-10
Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp
··· 27 27 - reg : Offset and length of the register set for the device 28 28 29 29 30 - * Alpine System-Fabric Service Registers 31 - 32 - The System-Fabric Service Registers allow various operation on CPU and 33 - system fabric, like powering CPUs off. 34 - 35 - Properties: 36 - - compatible : Should contain "al,alpine-sysfabric-service" and "syscon". 37 - - reg : Offset and length of the register set for the device 38 - 39 - 40 30 Example: 41 31 42 32 cpus {
-14
Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
··· 1 - Freescale Vybrid Miscellaneous System Control - CPU Configuration 2 - 3 - The MSCM IP contains multiple sub modules, this binding describes the first 4 - block of registers which contains CPU configuration information. 5 - 6 - Required properties: 7 - - compatible: "fsl,vf610-mscm-cpucfg", "syscon" 8 - - reg: the register range of the MSCM CPU configuration registers 9 - 10 - Example: 11 - mscm_cpucfg: cpucfg@40001000 { 12 - compatible = "fsl,vf610-mscm-cpucfg", "syscon"; 13 - reg = <0x40001000 0x800>; 14 - }
-15
Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt
··· 5 5 6 6 Required root node property: 7 7 - compatible: must contain "marvell,dove"; 8 - 9 - * Global Configuration registers 10 - 11 - Global Configuration registers of Dove SoC are shared by a syscon node. 12 - 13 - Required properties: 14 - - compatible: must contain "marvell,dove-global-config" and "syscon". 15 - - reg: base address and size of the Global Configuration registers. 16 - 17 - Example: 18 - 19 - gconf: global-config@e802c { 20 - compatible = "marvell,dove-global-config", "syscon"; 21 - reg = <0xe802c 0x14>; 22 - };
-9
Documentation/devicetree/bindings/arm/spear-misc.txt
··· 1 - SPEAr Misc configuration 2 - =========================== 3 - SPEAr SOCs have some miscellaneous registers which are used to configure 4 - few properties of different peripheral controllers. 5 - 6 - misc node required properties: 7 - 8 - - compatible Should be "st,spear1340-misc", "syscon". 9 - - reg: Address range of misc space up to 8K
-20
Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
··· 1 - * Device tree bindings for Texas Instruments keystone pll controller 2 - 3 - The main pll controller used to drive theC66x CorePacs, the switch fabric, 4 - and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and 5 - the NETCP modules) requires a PLL Controller to manage the various clock 6 - divisions, gating, and synchronization. 7 - 8 - Required properties: 9 - 10 - - compatible: "ti,keystone-pllctrl", "syscon" 11 - 12 - - reg: contains offset/length value for pll controller 13 - registers space. 14 - 15 - Example: 16 - 17 - pllctrl: pll-controller@02310000 { 18 - compatible = "ti,keystone-pllctrl", "syscon"; 19 - reg = <0x02310000 0x200>; 20 - };
+29
Documentation/devicetree/bindings/mfd/syscon.yaml
··· 34 34 anyOf: 35 35 - items: 36 36 - enum: 37 + - al,alpine-sysfabric-service 37 38 - allwinner,sun8i-a83t-system-controller 38 39 - allwinner,sun8i-h3-system-controller 39 40 - allwinner,sun8i-v3s-system-controller 40 41 - allwinner,sun50i-a64-system-controller 42 + - altr,l3regs 41 43 - altr,sdr-ctl 42 44 - amd,pensando-elba-syscon 45 + - amlogic,meson-mx-assist 46 + - amlogic,meson-mx-bootrom 47 + - amlogic,meson8-analog-top 48 + - amlogic,meson8b-analog-top 49 + - amlogic,meson8-pmu 50 + - amlogic,meson8b-pmu 43 51 - apm,xgene-csw 44 52 - apm,xgene-efuse 45 53 - apm,xgene-mcb 46 54 - apm,xgene-rb 47 55 - apm,xgene-scu 56 + - atmel,sama5d2-sfrbu 57 + - atmel,sama5d3-nfc-io 58 + - atmel,sama5d3-sfrbu 59 + - atmel,sama5d4-sfrbu 60 + - axis,artpec6-syscon 48 61 - brcm,cru-clkset 49 62 - brcm,sr-cdru 50 63 - brcm,sr-mhb 64 + - cirrus,ep7209-syscon1 65 + - cirrus,ep7209-syscon2 66 + - cirrus,ep7209-syscon3 67 + - cnxt,cx92755-uc 51 68 - freecom,fsg-cs2-system-controller 52 69 - fsl,imx93-aonmix-ns-syscfg 53 70 - fsl,imx93-wakeupmix-syscfg 54 71 - fsl,ls1088a-reset 72 + - fsl,vf610-anatop 73 + - fsl,vf610-mscm-cpucfg 55 74 - hisilicon,dsa-subctrl 56 75 - hisilicon,hi6220-sramctrl 76 + - hisilicon,hip04-ppe 57 77 - hisilicon,pcie-sas-subctrl 58 78 - hisilicon,peri-subctrl 59 79 - hpe,gxp-sysreg 60 80 - loongson,ls1b-syscon 61 81 - loongson,ls1c-syscon 82 + - lsi,axxia-syscon 62 83 - marvell,armada-3700-cpu-misc 63 84 - marvell,armada-3700-nb-pm 64 85 - marvell,armada-3700-avs 65 86 - marvell,armada-3700-usb2-host-misc 87 + - marvell,dove-global-config 88 + - mediatek,mt2701-pctl-a-syscfg 66 89 - mediatek,mt2712-pctl-a-syscfg 67 90 - mediatek,mt6397-pctl-pmic-syscfg 68 91 - mediatek,mt8135-pctl-a-syscfg ··· 93 70 - mediatek,mt8173-pctl-a-syscfg 94 71 - mediatek,mt8365-syscfg 95 72 - microchip,lan966x-cpu-syscon 73 + - microchip,sam9x60-sfr 74 + - microchip,sama7g5-ddr3phy 75 + - mscc,ocelot-cpu-syscon 96 76 - mstar,msc313-pmsleep 97 77 - nuvoton,ma35d1-sys 98 78 - nuvoton,wpcm450-shm ··· 110 84 - rockchip,rk3568-qos 111 85 - rockchip,rk3588-qos 112 86 - rockchip,rv1126-qos 87 + - st,spear1340-misc 88 + - stericsson,nomadik-pmu 113 89 - starfive,jh7100-sysmain 114 90 - ti,am62-usb-phy-ctrl 115 91 - ti,am625-dss-oldi-io-ctrl 116 92 - ti,am62p-cpsw-mac-efuse 117 93 - ti,am654-dss-oldi-io-ctrl 118 94 - ti,j784s4-pcie-ctrl 95 + - ti,keystone-pllctrl 119 96 120 97 - const: syscon 121 98
-17
Documentation/devicetree/bindings/mips/mscc.txt
··· 25 25 reg = <0x71070000 0x1c>; 26 26 }; 27 27 28 - 29 - o CPU system control: 30 - 31 - The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of 32 - the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU 33 - endianness, CPU bus control, CPU status. 34 - 35 - Required properties: 36 - - compatible: Should be "mscc,ocelot-cpu-syscon", "syscon" 37 - - reg : Should contain registers location and length 38 - 39 - Example: 40 - syscon@70000000 { 41 - compatible = "mscc,ocelot-cpu-syscon", "syscon"; 42 - reg = <0x70000000 0x2c>; 43 - }; 44 - 45 28 o HSIO regs: 46 29 47 30 The SoC has a few registers (HSIO) handling miscellaneous functionalities:
-9
Documentation/devicetree/bindings/mtd/atmel-nand.txt
··· 60 60 - reg: should contain 2 register ranges. The first one is pointing to the PMECC 61 61 block, and the second one to the PMECC_ERRLOC block. 62 62 63 - * SAMA5 NFC I/O bindings: 64 - 65 - SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page 66 - operations. This interface to this logic is placed in a separate I/O range and 67 - should thus have its own DT node. 68 - 69 - - compatible: should be "atmel,sama5d3-nfc-io", "syscon". 70 - - reg: should contain the I/O range used to interact with the NFC logic. 71 - 72 63 Example: 73 64 74 65 nfc_io: nfc-io@70000000 {
-10
Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt
··· 19 19 [1] Documentation/devicetree/bindings/net/ethernet.txt 20 20 21 21 22 - * Ethernet ppe node: 23 - Control rx & tx fifos of all ethernet controllers. 24 - Have 2048 recv channels shared by all ethernet controllers, only if no overlap. 25 - Each controller's recv channel start from channel * number (RX_DESC_NUM). 26 - 27 - Required properties: 28 - - compatible: "hisilicon,hip04-ppe", "syscon". 29 - - reg: address and length of the register set for the device. 30 - 31 - 32 22 * MDIO bus node: 33 23 34 24 Required properties: