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drm/amdgpu: Register aqua vanjaram vcn poison irq

Register aqua vanjaram vcn poison irq, add vcn poison handle.

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Stanley.Yang and committed by
Alex Deucher
4c4a8914 1327d8f4

+71
+65
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
··· 169 169 if (r) 170 170 return r; 171 171 172 + /* VCN POISON TRAP */ 173 + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 174 + VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq); 175 + 172 176 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 173 177 174 178 r = amdgpu_vcn_sw_init(adev, i); ··· 390 386 if (vinst->cur_state != AMD_PG_STATE_GATE) 391 387 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 392 388 } 389 + 390 + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 391 + amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0); 393 392 394 393 return 0; 395 394 } ··· 1821 1814 return 0; 1822 1815 } 1823 1816 1817 + static int vcn_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev, 1818 + struct amdgpu_irq_src *source, 1819 + unsigned int type, 1820 + enum amdgpu_interrupt_state state) 1821 + { 1822 + return 0; 1823 + } 1824 + 1824 1825 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 1825 1826 .set = vcn_v4_0_3_set_interrupt_state, 1826 1827 .process = vcn_v4_0_3_process_interrupt, 1828 + }; 1829 + 1830 + static const struct amdgpu_irq_src_funcs vcn_v4_0_3_ras_irq_funcs = { 1831 + .set = vcn_v4_0_3_set_ras_interrupt_state, 1832 + .process = amdgpu_vcn_process_poison_irq, 1827 1833 }; 1828 1834 1829 1835 /** ··· 1854 1834 adev->vcn.inst->irq.num_types++; 1855 1835 } 1856 1836 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 1837 + 1838 + adev->vcn.inst->ras_poison_irq.num_types = 1; 1839 + adev->vcn.inst->ras_poison_irq.funcs = &vcn_v4_0_3_ras_irq_funcs; 1857 1840 } 1858 1841 1859 1842 static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) ··· 2004 1981 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 2005 1982 } 2006 1983 1984 + static uint32_t vcn_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev, 1985 + uint32_t instance, uint32_t sub_block) 1986 + { 1987 + uint32_t poison_stat = 0, reg_value = 0; 1988 + 1989 + switch (sub_block) { 1990 + case AMDGPU_VCN_V4_0_3_VCPU_VCODEC: 1991 + reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 1992 + poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 1993 + break; 1994 + default: 1995 + break; 1996 + } 1997 + 1998 + if (poison_stat) 1999 + dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2000 + instance, sub_block); 2001 + 2002 + return poison_stat; 2003 + } 2004 + 2005 + static bool vcn_v4_0_3_query_poison_status(struct amdgpu_device *adev) 2006 + { 2007 + uint32_t inst, sub; 2008 + uint32_t poison_stat = 0; 2009 + 2010 + for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2011 + for (sub = 0; sub < AMDGPU_VCN_V4_0_3_MAX_SUB_BLOCK; sub++) 2012 + poison_stat += 2013 + vcn_v4_0_3_query_poison_by_instance(adev, inst, sub); 2014 + 2015 + return !!poison_stat; 2016 + } 2017 + 2007 2018 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 2008 2019 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 2009 2020 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 2021 + .query_poison_status = vcn_v4_0_3_query_poison_status, 2010 2022 }; 2011 2023 2012 2024 static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, ··· 2116 2058 r = amdgpu_ras_block_late_init(adev, ras_block); 2117 2059 if (r) 2118 2060 return r; 2061 + 2062 + if (amdgpu_ras_is_supported(adev, ras_block->block) && 2063 + adev->vcn.inst->ras_poison_irq.funcs) { 2064 + r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0); 2065 + if (r) 2066 + goto late_fini; 2067 + } 2119 2068 2120 2069 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN, 2121 2070 &vcn_v4_0_3_aca_info, NULL);
+6
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h
··· 24 24 #ifndef __VCN_V4_0_3_H__ 25 25 #define __VCN_V4_0_3_H__ 26 26 27 + enum amdgpu_vcn_v4_0_3_sub_block { 28 + AMDGPU_VCN_V4_0_3_VCPU_VCODEC = 0, 29 + 30 + AMDGPU_VCN_V4_0_3_MAX_SUB_BLOCK, 31 + }; 32 + 27 33 extern const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block; 28 34 29 35 void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,