tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ide: add struct ide_io_ports (take 3)

* Add struct ide_io_ports and use it instead of `unsigned long io_ports[]`
in ide_hwif_t.

* Rename io_ports[] in hw_regs_t to io_ports_array[].

* Use un-named union for 'unsigned long io_ports_array[]' and 'struct
ide_io_ports io_ports' in hw_regs_t.

* Remove IDE_*_OFFSET defines.

v2:
* scc_pata.c build fix from Stephen Rothwell.

v3:
* Fix ctl_adrr typo in Sparc-specific part of ns87415.c.
(Noticed by Andrew Morton)

Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Bartlomiej Zolnierkiewicz 4c3032d8 387750c3

+265 -271
+3 -3
drivers/ide/arm/bast-ide.c
··· 35 35 base += BAST_IDE_CS; 36 36 aux += BAST_IDE_CS; 37 37 38 - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { 39 - hw.io_ports[i] = (unsigned long)base; 38 + for (i = 0; i <= 7; i++) { 39 + hw.io_ports_array[i] = (unsigned long)base; 40 40 base += 0x20; 41 41 } 42 42 43 - hw.io_ports[IDE_CONTROL_OFFSET] = aux + (6 * 0x20); 43 + hw.io_ports.ctl_addr = aux + (6 * 0x20); 44 44 hw.irq = irq; 45 45 46 46 hwif = ide_find_port();
+4 -3
drivers/ide/arm/icside.c
··· 426 426 */ 427 427 default_hwif_mmiops(hwif); 428 428 429 - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { 430 - hwif->io_ports[i] = port; 429 + for (i = 0; i <= 7; i++) { 430 + hwif->io_ports_array[i] = port; 431 431 port += 1 << info->stepping; 432 432 } 433 - hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset; 433 + hwif->io_ports.ctl_addr = 434 + (unsigned long)base + info->ctrloffset; 434 435 hwif->irq = ec->irq; 435 436 hwif->chipset = ide_acorn; 436 437 hwif->gendev.parent = &ec->dev;
+3 -3
drivers/ide/arm/palm_bk3710.c
··· 321 321 const struct ide_port_info *d) 322 322 { 323 323 unsigned long base = 324 - hwif->io_ports[IDE_DATA_OFFSET] - IDE_PALM_ATA_PRI_REG_OFFSET; 324 + hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET; 325 325 326 326 printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name); 327 327 ··· 386 386 387 387 pribase = mem->start + IDE_PALM_ATA_PRI_REG_OFFSET; 388 388 for (i = 0; i < IDE_NR_PORTS - 2; i++) 389 - hw.io_ports[i] = pribase + i; 390 - hw.io_ports[IDE_CONTROL_OFFSET] = mem->start + 389 + hw.io_ports_array[i] = pribase + i; 390 + hw.io_ports.ctl_addr = mem->start + 391 391 IDE_PALM_ATA_PRI_CTL_OFFSET; 392 392 hw.irq = irq->start; 393 393 hw.chipset = ide_palm3710;
+3 -3
drivers/ide/arm/rapide.c
··· 17 17 unsigned long port = (unsigned long)base; 18 18 int i; 19 19 20 - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { 21 - hw->io_ports[i] = port; 20 + for (i = 0; i <= 7; i++) { 21 + hw->io_ports_array[i] = port; 22 22 port += sz; 23 23 } 24 - hw->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)ctrl; 24 + hw->io_ports.ctl_addr = (unsigned long)ctrl; 25 25 hw->irq = irq; 26 26 } 27 27
+9 -9
drivers/ide/cris/ide-cris.c
··· 88 88 int 89 89 cris_ide_ack_intr(ide_hwif_t* hwif) 90 90 { 91 - reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, 92 - int, hwif->io_ports[0]); 91 + reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, 92 + hwif->io_ports.data_addr); 93 93 REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel); 94 94 return 1; 95 95 } ··· 231 231 ide_hwif_t *hwif = drive->hwif; 232 232 233 233 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, 234 - hwif->io_ports[IDE_DATA_OFFSET]); 234 + hwif->io_ports.data_addr); 235 235 reg_ata_rw_trf_cnt trf_cnt = {0}; 236 236 237 237 mycontext.saved_data = (dma_descr_data*)virt_to_phys(d); ··· 271 271 int intr = REG_RD_INT(ata, regi_ata, r_intr); 272 272 273 273 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, 274 - hwif->io_ports[IDE_DATA_OFFSET]); 274 + hwif->io_ports.data_addr); 275 275 276 276 return intr & (1 << ctrl2.sel) ? 1 : 0; 277 277 } ··· 531 531 *R_ATA_CTRL_DATA = 532 532 cmd | 533 533 IO_FIELD(R_ATA_CTRL_DATA, data, 534 - drive->hwif->io_ports[IDE_DATA_OFFSET]) | 534 + drive->hwif->io_ports.data_addr) | 535 535 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | 536 536 IO_STATE(R_ATA_CTRL_DATA, multi, on) | 537 537 IO_STATE(R_ATA_CTRL_DATA, dma_size, word); ··· 550 550 { 551 551 int intr = *R_IRQ_MASK0_RD; 552 552 int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel, 553 - drive->hwif->io_ports[IDE_DATA_OFFSET]); 553 + drive->hwif->io_ports.data_addr); 554 554 555 555 return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0; 556 556 } ··· 644 644 * call will also timeout on busy, but as long as the 645 645 * write is still performed, everything will be fine. 646 646 */ 647 - if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET) 647 + if (cris_ide_get_reg(reg) == 7) 648 648 return BUSY_STAT; 649 649 else 650 650 /* For other rare cases we assume 0 is good enough. */ ··· 765 765 memset(hw, 0, sizeof(*hw)); 766 766 767 767 for (i = 0; i <= 7; i++) 768 - hw->io_ports[i] = base + cris_ide_reg_addr(i, 0, 1); 768 + hw->io_ports_array[i] = base + cris_ide_reg_addr(i, 0, 1); 769 769 770 770 /* 771 771 * the IDE control register is at ATA address 6, 772 772 * with CS1 active instead of CS0 773 773 */ 774 - hw->io_ports[IDE_CONTROL_OFFSET] = base + cris_ide_reg_addr(6, 1, 0); 774 + hw->io_ports.ctl_addr = base + cris_ide_reg_addr(6, 1, 0); 775 775 776 776 hw->irq = ide_default_irq(0); 777 777 hw->ack_intr = cris_ide_ack_intr;
+3 -3
drivers/ide/h8300/ide-h8300.c
··· 63 63 int i; 64 64 65 65 memset(hw, 0, sizeof(hw_regs_t)); 66 - for (i = 0; i <= IDE_STATUS_OFFSET; i++) 67 - hw->io_ports[i] = CONFIG_H8300_IDE_BASE + H8300_IDE_GAP*i; 68 - hw->io_ports[IDE_CONTROL_OFFSET] = CONFIG_H8300_IDE_ALT; 66 + for (i = 0; i <= 7; i++) 67 + hw->io_ports_array[i] = CONFIG_H8300_IDE_BASE + H8300_IDE_GAP*i; 68 + hw->io_ports.ctl_addr = CONFIG_H8300_IDE_ALT; 69 69 hw->irq = EXT_IRQ0 + CONFIG_H8300_IDE_IRQ; 70 70 hw->chipset = ide_generic; 71 71 }
+4 -4
drivers/ide/ide-cd.c
··· 560 560 /* packet command */ 561 561 spin_lock_irqsave(&ide_lock, flags); 562 562 hwif->OUTBSYNC(drive, WIN_PACKETCMD, 563 - hwif->io_ports[IDE_COMMAND_OFFSET]); 563 + hwif->io_ports.command_addr); 564 564 ndelay(400); 565 565 spin_unlock_irqrestore(&ide_lock, flags); 566 566 ··· 952 952 } 953 953 954 954 /* ok we fall to pio :/ */ 955 - ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]) & 0x3; 956 - lowcyl = hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]); 957 - highcyl = hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]); 955 + ireason = hwif->INB(hwif->io_ports.nsect_addr) & 0x3; 956 + lowcyl = hwif->INB(hwif->io_ports.lbam_addr); 957 + highcyl = hwif->INB(hwif->io_ports.lbah_addr); 958 958 959 959 len = lowcyl + (256 * highcyl); 960 960
+6 -6
drivers/ide/ide-floppy.c
··· 465 465 } 466 466 467 467 /* Get the number of bytes to transfer */ 468 - bcount = (hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]) << 8) | 469 - hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]); 468 + bcount = (hwif->INB(hwif->io_ports.lbah_addr) << 8) | 469 + hwif->INB(hwif->io_ports.lbam_addr); 470 470 /* on this interrupt */ 471 - ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 471 + ireason = hwif->INB(hwif->io_ports.nsect_addr); 472 472 473 473 if (ireason & CD) { 474 474 printk(KERN_ERR "ide-floppy: CoD != 0 in %s\n", __func__); ··· 539 539 "initiated yet DRQ isn't asserted\n"); 540 540 return startstop; 541 541 } 542 - ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 542 + ireason = hwif->INB(hwif->io_ports.nsect_addr); 543 543 if ((ireason & CD) == 0 || (ireason & IO)) { 544 544 printk(KERN_ERR "ide-floppy: (IO,CoD) != (0,1) while " 545 545 "issuing a packet command\n"); ··· 586 586 "initiated yet DRQ isn't asserted\n"); 587 587 return startstop; 588 588 } 589 - ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 589 + ireason = hwif->INB(hwif->io_ports.nsect_addr); 590 590 if ((ireason & CD) == 0 || (ireason & IO)) { 591 591 printk(KERN_ERR "ide-floppy: (IO,CoD) != (0,1) " 592 592 "while issuing a packet command\n"); ··· 692 692 return ide_started; 693 693 } else { 694 694 /* Issue the packet command */ 695 - hwif->OUTB(WIN_PACKETCMD, hwif->io_ports[IDE_COMMAND_OFFSET]); 695 + hwif->OUTB(WIN_PACKETCMD, hwif->io_ports.command_addr); 696 696 return (*pkt_xfer_routine) (drive); 697 697 } 698 698 }
+18 -24
drivers/ide/ide-io.c
··· 298 298 void ide_tf_read(ide_drive_t *drive, ide_task_t *task) 299 299 { 300 300 ide_hwif_t *hwif = drive->hwif; 301 + struct ide_io_ports *io_ports = &hwif->io_ports; 301 302 struct ide_taskfile *tf = &task->tf; 302 303 303 304 if (task->tf_flags & IDE_TFLAG_IN_DATA) { 304 - u16 data = hwif->INW(hwif->io_ports[IDE_DATA_OFFSET]); 305 + u16 data = hwif->INW(io_ports->data_addr); 305 306 306 307 tf->data = data & 0xff; 307 308 tf->hob_data = (data >> 8) & 0xff; 308 309 } 309 310 310 311 /* be sure we're looking at the low order bits */ 311 - hwif->OUTB(drive->ctl & ~0x80, hwif->io_ports[IDE_CONTROL_OFFSET]); 312 + hwif->OUTB(drive->ctl & ~0x80, io_ports->ctl_addr); 312 313 313 314 if (task->tf_flags & IDE_TFLAG_IN_NSECT) 314 - tf->nsect = hwif->INB(hwif->io_ports[IDE_NSECTOR_OFFSET]); 315 + tf->nsect = hwif->INB(io_ports->nsect_addr); 315 316 if (task->tf_flags & IDE_TFLAG_IN_LBAL) 316 - tf->lbal = hwif->INB(hwif->io_ports[IDE_SECTOR_OFFSET]); 317 + tf->lbal = hwif->INB(io_ports->lbal_addr); 317 318 if (task->tf_flags & IDE_TFLAG_IN_LBAM) 318 - tf->lbam = hwif->INB(hwif->io_ports[IDE_LCYL_OFFSET]); 319 + tf->lbam = hwif->INB(io_ports->lbam_addr); 319 320 if (task->tf_flags & IDE_TFLAG_IN_LBAH) 320 - tf->lbah = hwif->INB(hwif->io_ports[IDE_HCYL_OFFSET]); 321 + tf->lbah = hwif->INB(io_ports->lbah_addr); 321 322 if (task->tf_flags & IDE_TFLAG_IN_DEVICE) 322 - tf->device = hwif->INB(hwif->io_ports[IDE_SELECT_OFFSET]); 323 + tf->device = hwif->INB(io_ports->device_addr); 323 324 324 325 if (task->tf_flags & IDE_TFLAG_LBA48) { 325 - hwif->OUTB(drive->ctl | 0x80, 326 - hwif->io_ports[IDE_CONTROL_OFFSET]); 326 + hwif->OUTB(drive->ctl | 0x80, io_ports->ctl_addr); 327 327 328 328 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE) 329 - tf->hob_feature = 330 - hwif->INB(hwif->io_ports[IDE_FEATURE_OFFSET]); 329 + tf->hob_feature = hwif->INB(io_ports->feature_addr); 331 330 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT) 332 - tf->hob_nsect = 333 - hwif->INB(hwif->io_ports[IDE_NSECTOR_OFFSET]); 331 + tf->hob_nsect = hwif->INB(io_ports->nsect_addr); 334 332 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL) 335 - tf->hob_lbal = 336 - hwif->INB(hwif->io_ports[IDE_SECTOR_OFFSET]); 333 + tf->hob_lbal = hwif->INB(io_ports->lbal_addr); 337 334 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM) 338 - tf->hob_lbam = 339 - hwif->INB(hwif->io_ports[IDE_LCYL_OFFSET]); 335 + tf->hob_lbam = hwif->INB(io_ports->lbam_addr); 340 336 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH) 341 - tf->hob_lbah = 342 - hwif->INB(hwif->io_ports[IDE_HCYL_OFFSET]); 337 + tf->hob_lbah = hwif->INB(io_ports->lbah_addr); 343 338 } 344 339 } 345 340 ··· 449 454 if (err == ABRT_ERR) { 450 455 if (drive->select.b.lba && 451 456 /* some newer drives don't support WIN_SPECIFY */ 452 - hwif->INB(hwif->io_ports[IDE_COMMAND_OFFSET]) == 457 + hwif->INB(hwif->io_ports.command_addr) == 453 458 WIN_SPECIFY) 454 459 return ide_stopped; 455 460 } else if ((err & BAD_CRC) == BAD_CRC) { ··· 502 507 503 508 if (ide_read_status(drive) & (BUSY_STAT | DRQ_STAT)) 504 509 /* force an abort */ 505 - hwif->OUTB(WIN_IDLEIMMEDIATE, 506 - hwif->io_ports[IDE_COMMAND_OFFSET]); 510 + hwif->OUTB(WIN_IDLEIMMEDIATE, hwif->io_ports.command_addr); 507 511 508 512 if (rq->errors >= ERROR_MAX) { 509 513 ide_kill_rq(drive, rq); ··· 1415 1421 */ 1416 1422 do { 1417 1423 if (hwif->irq == irq) { 1418 - stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 1424 + stat = hwif->INB(hwif->io_ports.status_addr); 1419 1425 if (!OK_STAT(stat, READY_STAT, BAD_STAT)) { 1420 1426 /* Try to not flood the console with msgs */ 1421 1427 static unsigned long last_msgtime, count; ··· 1505 1511 * Whack the status register, just in case 1506 1512 * we have a leftover pending IRQ. 1507 1513 */ 1508 - (void) hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 1514 + (void) hwif->INB(hwif->io_ports.status_addr); 1509 1515 #endif /* CONFIG_BLK_DEV_IDEPCI */ 1510 1516 } 1511 1517 spin_unlock_irqrestore(&ide_lock, flags);
+34 -38
drivers/ide/ide-iops.c
··· 164 164 if (port_ops && port_ops->selectproc) 165 165 port_ops->selectproc(drive); 166 166 167 - hwif->OUTB(drive->select.all, hwif->io_ports[IDE_SELECT_OFFSET]); 167 + hwif->OUTB(drive->select.all, hwif->io_ports.device_addr); 168 168 } 169 169 170 170 void SELECT_MASK (ide_drive_t *drive, int mask) ··· 194 194 */ 195 195 static void ata_input_data(ide_drive_t *drive, void *buffer, u32 wcount) 196 196 { 197 - ide_hwif_t *hwif = HWIF(drive); 198 - u8 io_32bit = drive->io_32bit; 197 + ide_hwif_t *hwif = drive->hwif; 198 + struct ide_io_ports *io_ports = &hwif->io_ports; 199 + u8 io_32bit = drive->io_32bit; 199 200 200 201 if (io_32bit) { 201 202 if (io_32bit & 2) { 202 203 unsigned long flags; 203 204 204 205 local_irq_save(flags); 205 - ata_vlb_sync(drive, hwif->io_ports[IDE_NSECTOR_OFFSET]); 206 - hwif->INSL(hwif->io_ports[IDE_DATA_OFFSET], buffer, 207 - wcount); 206 + ata_vlb_sync(drive, io_ports->nsect_addr); 207 + hwif->INSL(io_ports->data_addr, buffer, wcount); 208 208 local_irq_restore(flags); 209 209 } else 210 - hwif->INSL(hwif->io_ports[IDE_DATA_OFFSET], buffer, 211 - wcount); 210 + hwif->INSL(io_ports->data_addr, buffer, wcount); 212 211 } else 213 - hwif->INSW(hwif->io_ports[IDE_DATA_OFFSET], buffer, 214 - wcount << 1); 212 + hwif->INSW(io_ports->data_addr, buffer, wcount << 1); 215 213 } 216 214 217 215 /* ··· 217 219 */ 218 220 static void ata_output_data(ide_drive_t *drive, void *buffer, u32 wcount) 219 221 { 220 - ide_hwif_t *hwif = HWIF(drive); 221 - u8 io_32bit = drive->io_32bit; 222 + ide_hwif_t *hwif = drive->hwif; 223 + struct ide_io_ports *io_ports = &hwif->io_ports; 224 + u8 io_32bit = drive->io_32bit; 222 225 223 226 if (io_32bit) { 224 227 if (io_32bit & 2) { 225 228 unsigned long flags; 226 229 227 230 local_irq_save(flags); 228 - ata_vlb_sync(drive, hwif->io_ports[IDE_NSECTOR_OFFSET]); 229 - hwif->OUTSL(hwif->io_ports[IDE_DATA_OFFSET], buffer, 230 - wcount); 231 + ata_vlb_sync(drive, io_ports->nsect_addr); 232 + hwif->OUTSL(io_ports->data_addr, buffer, wcount); 231 233 local_irq_restore(flags); 232 234 } else 233 - hwif->OUTSL(hwif->io_ports[IDE_DATA_OFFSET], buffer, 234 - wcount); 235 + hwif->OUTSL(io_ports->data_addr, buffer, wcount); 235 236 } else 236 - hwif->OUTSW(hwif->io_ports[IDE_DATA_OFFSET], buffer, 237 - wcount << 1); 237 + hwif->OUTSW(io_ports->data_addr, buffer, wcount << 1); 238 238 } 239 239 240 240 /* ··· 251 255 #if defined(CONFIG_ATARI) || defined(CONFIG_Q40) 252 256 if (MACH_IS_ATARI || MACH_IS_Q40) { 253 257 /* Atari has a byte-swapped IDE interface */ 254 - insw_swapw(hwif->io_ports[IDE_DATA_OFFSET], buffer, 255 - bytecount / 2); 258 + insw_swapw(hwif->io_ports.data_addr, buffer, bytecount / 2); 256 259 return; 257 260 } 258 261 #endif /* CONFIG_ATARI || CONFIG_Q40 */ 259 262 hwif->ata_input_data(drive, buffer, bytecount / 4); 260 263 if ((bytecount & 0x03) >= 2) 261 - hwif->INSW(hwif->io_ports[IDE_DATA_OFFSET], 264 + hwif->INSW(hwif->io_ports.data_addr, 262 265 (u8 *)buffer + (bytecount & ~0x03), 1); 263 266 } 264 267 ··· 269 274 #if defined(CONFIG_ATARI) || defined(CONFIG_Q40) 270 275 if (MACH_IS_ATARI || MACH_IS_Q40) { 271 276 /* Atari has a byte-swapped IDE interface */ 272 - outsw_swapw(hwif->io_ports[IDE_DATA_OFFSET], buffer, 273 - bytecount / 2); 277 + outsw_swapw(hwif->io_ports.data_addr, buffer, bytecount / 2); 274 278 return; 275 279 } 276 280 #endif /* CONFIG_ATARI || CONFIG_Q40 */ 277 281 hwif->ata_output_data(drive, buffer, bytecount / 4); 278 282 if ((bytecount & 0x03) >= 2) 279 - hwif->OUTSW(hwif->io_ports[IDE_DATA_OFFSET], 283 + hwif->OUTSW(hwif->io_ports.data_addr, 280 284 (u8 *)buffer + (bytecount & ~0x03), 1); 281 285 } 282 286 ··· 439 445 * an interrupt with another pci card/device. We make no assumptions 440 446 * about possible isa-pnp and pci-pnp issues yet. 441 447 */ 442 - if (hwif->io_ports[IDE_CONTROL_OFFSET]) 448 + if (hwif->io_ports.ctl_addr) 443 449 stat = ide_read_altstatus(drive); 444 450 else 445 451 /* Note: this may clear a pending IRQ!! */ ··· 641 647 SELECT_MASK(drive, 1); 642 648 ide_set_irq(drive, 1); 643 649 msleep(50); 644 - hwif->OUTB(WIN_IDENTIFY, hwif->io_ports[IDE_COMMAND_OFFSET]); 650 + hwif->OUTB(WIN_IDENTIFY, hwif->io_ports.command_addr); 645 651 timeout = jiffies + WAIT_WORSTCASE; 646 652 do { 647 653 if (time_after(jiffies, timeout)) { ··· 690 696 int ide_config_drive_speed(ide_drive_t *drive, u8 speed) 691 697 { 692 698 ide_hwif_t *hwif = drive->hwif; 699 + struct ide_io_ports *io_ports = &hwif->io_ports; 693 700 int error = 0; 694 701 u8 stat; 695 702 ··· 729 734 SELECT_MASK(drive, 0); 730 735 udelay(1); 731 736 ide_set_irq(drive, 0); 732 - hwif->OUTB(speed, hwif->io_ports[IDE_NSECTOR_OFFSET]); 733 - hwif->OUTB(SETFEATURES_XFER, hwif->io_ports[IDE_FEATURE_OFFSET]); 734 - hwif->OUTBSYNC(drive, WIN_SETFEATURES, 735 - hwif->io_ports[IDE_COMMAND_OFFSET]); 737 + hwif->OUTB(speed, io_ports->nsect_addr); 738 + hwif->OUTB(SETFEATURES_XFER, io_ports->feature_addr); 739 + hwif->OUTBSYNC(drive, WIN_SETFEATURES, io_ports->command_addr); 736 740 if (drive->quirk_list == 2) 737 741 ide_set_irq(drive, 1); 738 742 ··· 839 845 840 846 spin_lock_irqsave(&ide_lock, flags); 841 847 __ide_set_handler(drive, handler, timeout, expiry); 842 - hwif->OUTBSYNC(drive, cmd, hwif->io_ports[IDE_COMMAND_OFFSET]); 848 + hwif->OUTBSYNC(drive, cmd, hwif->io_ports.command_addr); 843 849 /* 844 850 * Drive takes 400nS to respond, we must avoid the IRQ being 845 851 * serviced before that. ··· 1023 1029 unsigned long flags; 1024 1030 ide_hwif_t *hwif; 1025 1031 ide_hwgroup_t *hwgroup; 1032 + struct ide_io_ports *io_ports; 1026 1033 const struct ide_port_ops *port_ops; 1027 1034 u8 ctl; 1028 1035 1029 1036 spin_lock_irqsave(&ide_lock, flags); 1030 1037 hwif = HWIF(drive); 1031 1038 hwgroup = HWGROUP(drive); 1039 + 1040 + io_ports = &hwif->io_ports; 1032 1041 1033 1042 /* We must not reset with running handlers */ 1034 1043 BUG_ON(hwgroup->handler != NULL); ··· 1042 1045 pre_reset(drive); 1043 1046 SELECT_DRIVE(drive); 1044 1047 udelay (20); 1045 - hwif->OUTBSYNC(drive, WIN_SRST, 1046 - hwif->io_ports[IDE_COMMAND_OFFSET]); 1048 + hwif->OUTBSYNC(drive, WIN_SRST, io_ports->command_addr); 1047 1049 ndelay(400); 1048 1050 hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE; 1049 1051 hwgroup->polling = 1; ··· 1058 1062 for (unit = 0; unit < MAX_DRIVES; ++unit) 1059 1063 pre_reset(&hwif->drives[unit]); 1060 1064 1061 - if (hwif->io_ports[IDE_CONTROL_OFFSET] == 0) { 1065 + if (io_ports->ctl_addr == 0) { 1062 1066 spin_unlock_irqrestore(&ide_lock, flags); 1063 1067 return ide_stopped; 1064 1068 } ··· 1073 1077 * recover from reset very quickly, saving us the first 50ms wait time. 1074 1078 */ 1075 1079 /* set SRST and nIEN */ 1076 - hwif->OUTBSYNC(drive, drive->ctl|6, hwif->io_ports[IDE_CONTROL_OFFSET]); 1080 + hwif->OUTBSYNC(drive, drive->ctl|6, io_ports->ctl_addr); 1077 1081 /* more than enough time */ 1078 1082 udelay(10); 1079 1083 if (drive->quirk_list == 2) 1080 1084 ctl = drive->ctl; /* clear SRST and nIEN */ 1081 1085 else 1082 1086 ctl = drive->ctl | 2; /* clear SRST, leave nIEN */ 1083 - hwif->OUTBSYNC(drive, ctl, hwif->io_ports[IDE_CONTROL_OFFSET]); 1087 + hwif->OUTBSYNC(drive, ctl, io_ports->ctl_addr); 1084 1088 /* more than enough time */ 1085 1089 udelay(10); 1086 1090 hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE; ··· 1125 1129 * about locking issues (2.5 work ?). 1126 1130 */ 1127 1131 mdelay(1); 1128 - stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 1132 + stat = hwif->INB(hwif->io_ports.status_addr); 1129 1133 if ((stat & BUSY_STAT) == 0) 1130 1134 return 0; 1131 1135 /*
+21 -20
drivers/ide/ide-probe.c
··· 264 264 static int actual_try_to_identify (ide_drive_t *drive, u8 cmd) 265 265 { 266 266 ide_hwif_t *hwif = HWIF(drive); 267 + struct ide_io_ports *io_ports = &hwif->io_ports; 267 268 int use_altstatus = 0, rc; 268 269 unsigned long timeout; 269 270 u8 s = 0, a = 0; ··· 272 271 /* take a deep breath */ 273 272 msleep(50); 274 273 275 - if (hwif->io_ports[IDE_CONTROL_OFFSET]) { 274 + if (io_ports->ctl_addr) { 276 275 a = ide_read_altstatus(drive); 277 276 s = ide_read_status(drive); 278 277 if ((a ^ s) & ~INDEX_STAT) ··· 290 289 */ 291 290 if ((cmd == WIN_PIDENTIFY)) 292 291 /* disable dma & overlap */ 293 - hwif->OUTB(0, hwif->io_ports[IDE_FEATURE_OFFSET]); 292 + hwif->OUTB(0, io_ports->feature_addr); 294 293 295 294 /* ask drive for ID */ 296 - hwif->OUTB(cmd, hwif->io_ports[IDE_COMMAND_OFFSET]); 295 + hwif->OUTB(cmd, io_ports->command_addr); 297 296 298 297 timeout = ((cmd == WIN_IDENTIFY) ? WAIT_WORSTCASE : WAIT_PIDENTIFY) / 2; 299 298 timeout += jiffies; ··· 354 353 * interrupts during the identify-phase that 355 354 * the irq handler isn't expecting. 356 355 */ 357 - if (hwif->io_ports[IDE_CONTROL_OFFSET]) { 356 + if (hwif->io_ports.ctl_addr) { 358 357 if (!hwif->irq) { 359 358 autoprobe = 1; 360 359 cookie = probe_irq_on(); ··· 394 393 395 394 do { 396 395 msleep(50); 397 - stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 396 + stat = hwif->INB(hwif->io_ports.status_addr); 398 397 if ((stat & BUSY_STAT) == 0) 399 398 return 0; 400 399 } while (time_before(jiffies, timeout)); ··· 426 425 static int do_probe (ide_drive_t *drive, u8 cmd) 427 426 { 428 427 ide_hwif_t *hwif = HWIF(drive); 428 + struct ide_io_ports *io_ports = &hwif->io_ports; 429 429 int rc; 430 430 u8 stat; 431 431 ··· 447 445 msleep(50); 448 446 SELECT_DRIVE(drive); 449 447 msleep(50); 450 - if (hwif->INB(hwif->io_ports[IDE_SELECT_OFFSET]) != drive->select.all && 448 + if (hwif->INB(io_ports->device_addr) != drive->select.all && 451 449 !drive->present) { 452 450 if (drive->select.b.unit != 0) { 453 451 /* exit with drive0 selected */ ··· 478 476 printk(KERN_ERR "%s: no response (status = 0x%02x), " 479 477 "resetting drive\n", drive->name, stat); 480 478 msleep(50); 481 - hwif->OUTB(drive->select.all, 482 - hwif->io_ports[IDE_SELECT_OFFSET]); 479 + hwif->OUTB(drive->select.all, io_ports->device_addr); 483 480 msleep(50); 484 - hwif->OUTB(WIN_SRST, 485 - hwif->io_ports[IDE_COMMAND_OFFSET]); 481 + hwif->OUTB(WIN_SRST, io_ports->command_addr); 486 482 (void)ide_busy_sleep(hwif); 487 483 rc = try_to_identify(drive, cmd); 488 484 } ··· 516 516 printk("%s: enabling %s -- ", hwif->name, drive->id->model); 517 517 SELECT_DRIVE(drive); 518 518 msleep(50); 519 - hwif->OUTB(EXABYTE_ENABLE_NEST, hwif->io_ports[IDE_COMMAND_OFFSET]); 519 + hwif->OUTB(EXABYTE_ENABLE_NEST, hwif->io_ports.command_addr); 520 520 521 521 if (ide_busy_sleep(hwif)) { 522 522 printk(KERN_CONT "failed (timeout)\n"); ··· 982 982 */ 983 983 static int init_irq (ide_hwif_t *hwif) 984 984 { 985 + struct ide_io_ports *io_ports = &hwif->io_ports; 985 986 unsigned int index; 986 987 ide_hwgroup_t *hwgroup; 987 988 ide_hwif_t *match = NULL; ··· 1066 1065 if (IDE_CHIPSET_IS_PCI(hwif->chipset)) 1067 1066 sa = IRQF_SHARED; 1068 1067 1069 - if (hwif->io_ports[IDE_CONTROL_OFFSET]) 1068 + if (io_ports->ctl_addr) 1070 1069 /* clear nIEN */ 1071 - hwif->OUTB(0x08, hwif->io_ports[IDE_CONTROL_OFFSET]); 1070 + hwif->OUTB(0x08, io_ports->ctl_addr); 1072 1071 1073 1072 if (request_irq(hwif->irq,&ide_intr,sa,hwif->name,hwgroup)) 1074 1073 goto out_unlink; ··· 1084 1083 1085 1084 #if !defined(__mc68000__) 1086 1085 printk("%s at 0x%03lx-0x%03lx,0x%03lx on irq %d", hwif->name, 1087 - hwif->io_ports[IDE_DATA_OFFSET], 1088 - hwif->io_ports[IDE_DATA_OFFSET]+7, 1089 - hwif->io_ports[IDE_CONTROL_OFFSET], hwif->irq); 1086 + io_ports->data_addr, io_ports->status_addr, 1087 + io_ports->ctl_addr, hwif->irq); 1090 1088 #else 1091 1089 printk("%s at 0x%08lx on irq %d", hwif->name, 1092 - hwif->io_ports[IDE_DATA_OFFSET], hwif->irq); 1090 + io_ports->data_addr, hwif->irq); 1093 1091 #endif /* __mc68000__ */ 1094 1092 if (match) 1095 1093 printk(" (%sed with %s)", ··· 1230 1230 int old_irq; 1231 1231 1232 1232 if (!hwif->irq) { 1233 - if (!(hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]))) 1234 - { 1233 + hwif->irq = ide_default_irq(hwif->io_ports.data_addr); 1234 + if (!hwif->irq) { 1235 1235 printk("%s: DISABLED, NO IRQ\n", hwif->name); 1236 1236 return 0; 1237 1237 } ··· 1260 1260 * It failed to initialise. Find the default IRQ for 1261 1261 * this port and try that. 1262 1262 */ 1263 - if (!(hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]))) { 1263 + hwif->irq = ide_default_irq(hwif->io_ports.data_addr); 1264 + if (!hwif->irq) { 1264 1265 printk("%s: Disabled unable to get IRQ %d.\n", 1265 1266 hwif->name, old_irq); 1266 1267 goto out;
+6 -6
drivers/ide/ide-tape.c
··· 849 849 return ide_do_reset(drive); 850 850 } 851 851 /* Get the number of bytes to transfer on this interrupt. */ 852 - bcount = (hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]) << 8) | 853 - hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]); 852 + bcount = (hwif->INB(hwif->io_ports.lbah_addr) << 8) | 853 + hwif->INB(hwif->io_ports.lbam_addr); 854 854 855 - ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 855 + ireason = hwif->INB(hwif->io_ports.nsect_addr); 856 856 857 857 if (ireason & CD) { 858 858 printk(KERN_ERR "ide-tape: CoD != 0 in %s\n", __func__); ··· 956 956 "yet DRQ isn't asserted\n"); 957 957 return startstop; 958 958 } 959 - ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 959 + ireason = hwif->INB(hwif->io_ports.nsect_addr); 960 960 while (retries-- && ((ireason & CD) == 0 || (ireason & IO))) { 961 961 printk(KERN_ERR "ide-tape: (IO,CoD != (0,1) while issuing " 962 962 "a packet command, retrying\n"); 963 963 udelay(100); 964 - ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 964 + ireason = hwif->INB(hwif->io_ports.nsect_addr); 965 965 if (retries == 0) { 966 966 printk(KERN_ERR "ide-tape: (IO,CoD != (0,1) while " 967 967 "issuing a packet command, ignoring\n"); ··· 1058 1058 IDETAPE_WAIT_CMD, NULL); 1059 1059 return ide_started; 1060 1060 } else { 1061 - hwif->OUTB(WIN_PACKETCMD, hwif->io_ports[IDE_COMMAND_OFFSET]); 1061 + hwif->OUTB(WIN_PACKETCMD, hwif->io_ports.command_addr); 1062 1062 return idetape_transfer_pc(drive); 1063 1063 } 1064 1064 }
+14 -15
drivers/ide/ide-taskfile.c
··· 36 36 void ide_tf_load(ide_drive_t *drive, ide_task_t *task) 37 37 { 38 38 ide_hwif_t *hwif = drive->hwif; 39 + struct ide_io_ports *io_ports = &hwif->io_ports; 39 40 struct ide_taskfile *tf = &task->tf; 40 41 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF; 41 42 ··· 60 59 SELECT_MASK(drive, 0); 61 60 62 61 if (task->tf_flags & IDE_TFLAG_OUT_DATA) 63 - hwif->OUTW((tf->hob_data << 8) | tf->data, 64 - hwif->io_ports[IDE_DATA_OFFSET]); 62 + hwif->OUTW((tf->hob_data << 8) | tf->data, io_ports->data_addr); 65 63 66 64 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE) 67 - hwif->OUTB(tf->hob_feature, hwif->io_ports[IDE_FEATURE_OFFSET]); 65 + hwif->OUTB(tf->hob_feature, io_ports->feature_addr); 68 66 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT) 69 - hwif->OUTB(tf->hob_nsect, hwif->io_ports[IDE_NSECTOR_OFFSET]); 67 + hwif->OUTB(tf->hob_nsect, io_ports->nsect_addr); 70 68 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL) 71 - hwif->OUTB(tf->hob_lbal, hwif->io_ports[IDE_SECTOR_OFFSET]); 69 + hwif->OUTB(tf->hob_lbal, io_ports->lbal_addr); 72 70 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM) 73 - hwif->OUTB(tf->hob_lbam, hwif->io_ports[IDE_LCYL_OFFSET]); 71 + hwif->OUTB(tf->hob_lbam, io_ports->lbam_addr); 74 72 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH) 75 - hwif->OUTB(tf->hob_lbah, hwif->io_ports[IDE_HCYL_OFFSET]); 73 + hwif->OUTB(tf->hob_lbah, io_ports->lbah_addr); 76 74 77 75 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE) 78 - hwif->OUTB(tf->feature, hwif->io_ports[IDE_FEATURE_OFFSET]); 76 + hwif->OUTB(tf->feature, io_ports->feature_addr); 79 77 if (task->tf_flags & IDE_TFLAG_OUT_NSECT) 80 - hwif->OUTB(tf->nsect, hwif->io_ports[IDE_NSECTOR_OFFSET]); 78 + hwif->OUTB(tf->nsect, io_ports->nsect_addr); 81 79 if (task->tf_flags & IDE_TFLAG_OUT_LBAL) 82 - hwif->OUTB(tf->lbal, hwif->io_ports[IDE_SECTOR_OFFSET]); 80 + hwif->OUTB(tf->lbal, io_ports->lbal_addr); 83 81 if (task->tf_flags & IDE_TFLAG_OUT_LBAM) 84 - hwif->OUTB(tf->lbam, hwif->io_ports[IDE_LCYL_OFFSET]); 82 + hwif->OUTB(tf->lbam, io_ports->lbam_addr); 85 83 if (task->tf_flags & IDE_TFLAG_OUT_LBAH) 86 - hwif->OUTB(tf->lbah, hwif->io_ports[IDE_HCYL_OFFSET]); 84 + hwif->OUTB(tf->lbah, io_ports->lbah_addr); 87 85 88 86 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) 89 87 hwif->OUTB((tf->device & HIHI) | drive->select.all, 90 - hwif->io_ports[IDE_SELECT_OFFSET]); 88 + io_ports->device_addr); 91 89 } 92 90 93 91 int taskfile_lib_get_identify (ide_drive_t *drive, u8 *buf) ··· 155 155 switch (task->data_phase) { 156 156 case TASKFILE_MULTI_OUT: 157 157 case TASKFILE_OUT: 158 - hwif->OUTBSYNC(drive, tf->command, 159 - hwif->io_ports[IDE_COMMAND_OFFSET]); 158 + hwif->OUTBSYNC(drive, tf->command, hwif->io_ports.command_addr); 160 159 ndelay(400); /* FIXME */ 161 160 return pre_task_out_intr(drive, task->rq); 162 161 case TASKFILE_MULTI_IN:
+1 -1
drivers/ide/ide.c
··· 368 368 369 369 void ide_init_port_hw(ide_hwif_t *hwif, hw_regs_t *hw) 370 370 { 371 - memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports)); 371 + memcpy(&hwif->io_ports, &hw->io_ports, sizeof(hwif->io_ports)); 372 372 hwif->irq = hw->irq; 373 373 hwif->chipset = hw->chipset; 374 374 hwif->gendev.parent = hw->dev;
+7 -7
drivers/ide/legacy/buddha.c
··· 102 102 { 103 103 unsigned char ch; 104 104 105 - ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]); 105 + ch = z_readb(hwif->io_ports.irq_addr); 106 106 if (!(ch & 0x80)) 107 107 return 0; 108 108 return 1; ··· 112 112 { 113 113 unsigned char ch; 114 114 115 - ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]); 115 + ch = z_readb(hwif->io_ports.irq_addr); 116 116 /* X-Surf needs a 0 written to IRQ register to ensure ISA bit A11 stays at 0 */ 117 - z_writeb(0, hwif->io_ports[IDE_IRQ_OFFSET]); 117 + z_writeb(0, hwif->io_ports.irq_addr); 118 118 if (!(ch & 0x80)) 119 119 return 0; 120 120 return 1; ··· 128 128 129 129 memset(hw, 0, sizeof(*hw)); 130 130 131 - hw->io_ports[IDE_DATA_OFFSET] = base; 131 + hw->io_ports.data_addr = base; 132 132 133 133 for (i = 1; i < 8; i++) 134 - hw->io_ports[i] = base + 2 + i * 4; 134 + hw->io_ports_array[i] = base + 2 + i * 4; 135 135 136 - hw->io_ports[IDE_CONTROL_OFFSET] = ctl; 137 - hw->io_ports[IDE_IRQ_OFFSET] = irq_port; 136 + hw->io_ports.ctl_addr = ctl; 137 + hw->io_ports.irq_addr = irq_port; 138 138 139 139 hw->irq = IRQ_AMIGA_PORTS; 140 140 hw->ack_intr = ack_intr;
+3 -3
drivers/ide/legacy/falconide.c
··· 50 50 51 51 memset(hw, 0, sizeof(*hw)); 52 52 53 - hw->io_ports[IDE_DATA_OFFSET] = ATA_HD_BASE; 53 + hw->io_ports.data_addr = ATA_HD_BASE; 54 54 55 55 for (i = 1; i < 8; i++) 56 - hw->io_ports[i] = ATA_HD_BASE + 1 + i * 4; 56 + hw->io_ports_array[i] = ATA_HD_BASE + 1 + i * 4; 57 57 58 - hw->io_ports[IDE_CONTROL_OFFSET] = ATA_HD_BASE + ATA_HD_CONTROL; 58 + hw->io_ports.ctl_addr = ATA_HD_BASE + ATA_HD_CONTROL; 59 59 60 60 hw->irq = IRQ_MFP_IDE; 61 61 hw->ack_intr = NULL;
+8 -8
drivers/ide/legacy/gayle.c
··· 76 76 { 77 77 unsigned char ch; 78 78 79 - ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]); 79 + ch = z_readb(hwif->io_ports.irq_addr); 80 80 if (!(ch & GAYLE_IRQ_IDE)) 81 81 return 0; 82 82 return 1; ··· 86 86 { 87 87 unsigned char ch; 88 88 89 - ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]); 89 + ch = z_readb(hwif->io_ports.irq_addr); 90 90 if (!(ch & GAYLE_IRQ_IDE)) 91 91 return 0; 92 - (void)z_readb(hwif->io_ports[IDE_STATUS_OFFSET]); 93 - z_writeb(0x7c, hwif->io_ports[IDE_IRQ_OFFSET]); 92 + (void)z_readb(hwif->io_ports.status_addr); 93 + z_writeb(0x7c, hwif->io_ports.irq_addr); 94 94 return 1; 95 95 } 96 96 ··· 102 102 103 103 memset(hw, 0, sizeof(*hw)); 104 104 105 - hw->io_ports[IDE_DATA_OFFSET] = base; 105 + hw->io_ports.data_addr = base; 106 106 107 107 for (i = 1; i < 8; i++) 108 - hw->io_ports[i] = base + 2 + i * 4; 108 + hw->io_ports_array[i] = base + 2 + i * 4; 109 109 110 - hw->io_ports[IDE_CONTROL_OFFSET] = ctl; 111 - hw->io_ports[IDE_IRQ_OFFSET] = irq_port; 110 + hw->io_ports.ctl_addr = ctl; 111 + hw->io_ports.irq_addr = irq_port; 112 112 113 113 hw->irq = IRQ_AMIGA_PORTS; 114 114 hw->ack_intr = ack_intr;
+2 -2
drivers/ide/legacy/ht6560b.c
··· 157 157 /* 158 158 * Set timing for this drive: 159 159 */ 160 - outb(timing, hwif->io_ports[IDE_SELECT_OFFSET]); 161 - (void)inb(hwif->io_ports[IDE_STATUS_OFFSET]); 160 + outb(timing, hwif->io_ports.device_addr); 161 + (void)inb(hwif->io_ports.status_addr); 162 162 #ifdef DEBUG 163 163 printk("ht6560b: %s: select=%#x timing=%#x\n", 164 164 drive->name, select, timing);
+2 -2
drivers/ide/legacy/ide-cs.c
··· 140 140 141 141 ide_release(link); 142 142 143 - release_region(hwif->io_ports[IDE_CONTROL_OFFSET], 1); 144 - release_region(hwif->io_ports[IDE_DATA_OFFSET], 8); 143 + release_region(hwif->io_ports.ctl_addr, 1); 144 + release_region(hwif->io_ports.data_addr, 8); 145 145 146 146 kfree(info); 147 147 } /* ide_detach */
+4 -4
drivers/ide/legacy/ide_platform.c
··· 30 30 unsigned long port = (unsigned long)base; 31 31 int i; 32 32 33 - hw->io_ports[IDE_DATA_OFFSET] = port; 33 + hw->io_ports.data_addr = port; 34 34 35 35 port += (1 << pdata->ioport_shift); 36 - for (i = IDE_ERROR_OFFSET; i <= IDE_STATUS_OFFSET; 36 + for (i = 1; i <= 7; 37 37 i++, port += (1 << pdata->ioport_shift)) 38 - hw->io_ports[i] = port; 38 + hw->io_ports_array[i] = port; 39 39 40 - hw->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)ctrl; 40 + hw->io_ports.ctl_addr = (unsigned long)ctrl; 41 41 42 42 hw->irq = irq; 43 43
+2 -2
drivers/ide/legacy/macide.c
··· 72 72 memset(hw, 0, sizeof(*hw)); 73 73 74 74 for (i = 0; i < 8; i++) 75 - hw->io_ports[i] = base + i * 4; 75 + hw->io_ports_array[i] = base + i * 4; 76 76 77 - hw->io_ports[IDE_CONTROL_OFFSET] = base + IDE_CONTROL; 77 + hw->io_ports.ctl_addr = base + IDE_CONTROL; 78 78 79 79 hw->irq = irq; 80 80 hw->ack_intr = ack_intr;
+3 -3
drivers/ide/legacy/q40ide.c
··· 80 80 for (i = 0; i < IDE_NR_PORTS; i++) { 81 81 /* BIG FAT WARNING: 82 82 assumption: only DATA port is ever used in 16 bit mode */ 83 - if ( i==0 ) 84 - hw->io_ports[i] = Q40_ISA_IO_W(base + offsets[i]); 83 + if (i == 0) 84 + hw->io_ports_array[i] = Q40_ISA_IO_W(base + offsets[i]); 85 85 else 86 - hw->io_ports[i] = Q40_ISA_IO_B(base + offsets[i]); 86 + hw->io_ports_array[i] = Q40_ISA_IO_B(base + offsets[i]); 87 87 } 88 88 89 89 hw->irq = irq;
+2 -3
drivers/ide/mips/au1xxx-ide.c
··· 502 502 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif) 503 503 { 504 504 int i; 505 - unsigned long *ata_regs = hw->io_ports; 505 + unsigned long *ata_regs = hw->io_ports_array; 506 506 507 507 /* FIXME? */ 508 - for (i = 0; i < IDE_CONTROL_OFFSET; i++) { 508 + for (i = 0; i < 8; i++) 509 509 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET); 510 - } 511 510 512 511 /* set the Alternative Status register */ 513 512 *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
+3 -3
drivers/ide/mips/swarm.c
··· 113 113 114 114 hwif->chipset = ide_generic; 115 115 116 - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) 117 - hwif->io_ports[i] = 116 + for (i = 0; i <= 7; i++) 117 + hwif->io_ports_array[i] = 118 118 (unsigned long)(base + ((0x1f0 + i) << 5)); 119 - hwif->io_ports[IDE_CONTROL_OFFSET] = 119 + hwif->io_ports.ctl_addr = 120 120 (unsigned long)(base + (0x3f6 << 5)); 121 121 hwif->irq = K_INT_GB_IDE; 122 122
+4 -4
drivers/ide/pci/cmd640.c
··· 347 347 348 348 spin_lock_irqsave(&cmd640_lock, flags); 349 349 350 - outb_p(0x0a, 0x170 + IDE_SELECT_OFFSET); /* select drive0 */ 350 + outb_p(0x0a, 0x176); /* select drive0 */ 351 351 udelay(100); 352 - if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x0a) { 353 - outb_p(0x1a, 0x170 + IDE_SELECT_OFFSET); /* select drive1 */ 352 + if ((inb_p(0x176) & 0x1f) != 0x0a) { 353 + outb_p(0x1a, 0x176); /* select drive1 */ 354 354 udelay(100); 355 - if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x1a) { 355 + if ((inb_p(0x176) & 0x1f) != 0x1a) { 356 356 spin_unlock_irqrestore(&cmd640_lock, flags); 357 357 return 0; /* nothing responded */ 358 358 }
+1 -1
drivers/ide/pci/hpt366.c
··· 760 760 } 761 761 } else 762 762 outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 763 - hwif->io_ports[IDE_CONTROL_OFFSET]); 763 + hwif->io_ports.ctl_addr); 764 764 } 765 765 766 766 /*
+6 -6
drivers/ide/pci/ns87415.c
··· 72 72 base = pci_resource_start(pdev, port * 2) & ~3; 73 73 dmabase = pci_resource_start(pdev, 4) & ~3; 74 74 75 - superio_ide_status[port] = base + IDE_STATUS_OFFSET; 76 - superio_ide_select[port] = base + IDE_SELECT_OFFSET; 75 + superio_ide_status[port] = base + 7; 76 + superio_ide_select[port] = base + 6; 77 77 superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa); 78 78 79 79 /* Clear error/interrupt, enable dma */ ··· 231 231 * SELECT_DRIVE() properly during first ide_probe_port(). 232 232 */ 233 233 timeout = 10000; 234 - outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]); 234 + outb(12, hwif->io_ports.ctl_addr); 235 235 udelay(10); 236 - outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]); 236 + outb(8, hwif->io_ports.ctl_addr); 237 237 do { 238 238 udelay(50); 239 - stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 239 + stat = hwif->INB(hwif->io_ports.status_addr); 240 240 if (stat == 0xff) 241 241 break; 242 242 } while ((stat & BUSY_STAT) && --timeout); ··· 244 244 } 245 245 246 246 if (!using_inta) 247 - hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]); 247 + hwif->irq = ide_default_irq(hwif->io_ports.data_addr); 248 248 else if (!hwif->irq && hwif->mate && hwif->mate->irq) 249 249 hwif->irq = hwif->mate->irq; /* share IRQ with mate */ 250 250
+1 -1
drivers/ide/pci/opti621.c
··· 279 279 280 280 spin_lock_irqsave(&opti621_lock, flags); 281 281 282 - reg_base = hwif->io_ports[IDE_DATA_OFFSET]; 282 + reg_base = hwif->io_ports.data_addr; 283 283 284 284 /* allow Register-B */ 285 285 outb(0xc0, reg_base + CNTRL_REG);
+4 -4
drivers/ide/pci/scc_pata.c
··· 334 334 335 335 /* errata A308 workaround: Step5 (check data loss) */ 336 336 /* We don't check non ide_disk because it is limited to UDMA4 */ 337 - if (!(in_be32((void __iomem *)hwif->io_ports[IDE_ALTSTATUS_OFFSET]) 337 + if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr) 338 338 & ERR_STAT) && 339 339 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) { 340 340 reg = in_be32((void __iomem *)intsts_port); ··· 438 438 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014); 439 439 440 440 /* SCC errata A252,A308 workaround: Step4 */ 441 - if ((in_be32((void __iomem *)hwif->io_ports[IDE_ALTSTATUS_OFFSET]) 441 + if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr) 442 442 & ERR_STAT) && 443 443 (int_stat & INTSTS_INTRQ)) 444 444 return 1; ··· 534 534 } 535 535 536 536 memset(&hw, 0, sizeof(hw)); 537 - for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; i++) 538 - hw.io_ports[i] = ports->dma + 0x20 + i * 4; 537 + for (i = 0; i <= 8; i++) 538 + hw.io_ports_array[i] = ports->dma + 0x20 + i * 4; 539 539 hw.irq = dev->irq; 540 540 hw.dev = &dev->dev; 541 541 hw.chipset = ide_pci;
+13 -13
drivers/ide/pci/sgiioc4.c
··· 98 98 int i; 99 99 100 100 /* Registers are word (32 bit) aligned */ 101 - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) 102 - hw->io_ports[i] = reg + i * 4; 101 + for (i = 0; i <= 7; i++) 102 + hw->io_ports_array[i] = reg + i * 4; 103 103 104 104 if (ctrl_port) 105 - hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; 105 + hw->io_ports.ctl_addr = ctrl_port; 106 106 107 107 if (irq_port) 108 - hw->io_ports[IDE_IRQ_OFFSET] = irq_port; 108 + hw->io_ports.irq_addr = irq_port; 109 109 } 110 110 111 111 static void 112 112 sgiioc4_maskproc(ide_drive_t * drive, int mask) 113 113 { 114 114 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 115 - (void __iomem *)drive->hwif->io_ports[IDE_CONTROL_OFFSET]); 115 + (void __iomem *)drive->hwif->io_ports.ctl_addr); 116 116 } 117 117 118 118 static int 119 119 sgiioc4_checkirq(ide_hwif_t * hwif) 120 120 { 121 121 unsigned long intr_addr = 122 - hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4; 122 + hwif->io_ports.irq_addr + IOC4_INTR_REG * 4; 123 123 124 124 if ((u8)readl((void __iomem *)intr_addr) & 0x03) 125 125 return 1; ··· 134 134 { 135 135 u32 intr_reg; 136 136 ide_hwif_t *hwif = HWIF(drive); 137 - unsigned long other_ir = 138 - hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2); 137 + struct ide_io_ports *io_ports = &hwif->io_ports; 138 + unsigned long other_ir = io_ports->irq_addr + (IOC4_INTR_REG << 2); 139 139 140 140 /* Code to check for PCI error conditions */ 141 141 intr_reg = readl((void __iomem *)other_ir); ··· 147 147 * a "clear" status if it got cleared. If not, then spin 148 148 * for a bit trying to clear it. 149 149 */ 150 - u8 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]); 150 + u8 stat = sgiioc4_INB(io_ports->status_addr); 151 151 int count = 0; 152 - stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]); 152 + stat = sgiioc4_INB(io_ports->status_addr); 153 153 while ((stat & 0x80) && (count++ < 100)) { 154 154 udelay(1); 155 - stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]); 155 + stat = sgiioc4_INB(io_ports->status_addr); 156 156 } 157 157 158 158 if (intr_reg & 0x02) { ··· 162 162 pci_stat_cmd_reg; 163 163 164 164 pci_err_addr_low = 165 - readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]); 165 + readl((void __iomem *)io_ports->irq_addr); 166 166 pci_err_addr_high = 167 - readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4)); 167 + readl((void __iomem *)(io_ports->irq_addr + 4)); 168 168 pci_read_config_dword(dev, PCI_COMMAND, 169 169 &pci_stat_cmd_reg); 170 170 printk(KERN_ERR
+12 -15
drivers/ide/pci/siimage.c
··· 622 622 struct pci_dev *dev = to_pci_dev(hwif->dev); 623 623 void *addr = pci_get_drvdata(dev); 624 624 u8 ch = hwif->channel; 625 - hw_regs_t hw; 626 625 unsigned long base; 626 + 627 + struct ide_io_ports *io_ports = &hwif->io_ports; 627 628 628 629 /* 629 630 * Fill in the basic HWIF bits ··· 639 638 * based I/O 640 639 */ 641 640 642 - memset(&hw, 0, sizeof(hw_regs_t)); 641 + memset(io_ports, 0, sizeof(*io_ports)); 643 642 644 643 base = (unsigned long)addr; 645 644 if (ch) ··· 652 651 * so we can't currently use it sanely since we want to 653 652 * use LBA48 mode. 654 653 */ 655 - hw.io_ports[IDE_DATA_OFFSET] = base; 656 - hw.io_ports[IDE_ERROR_OFFSET] = base + 1; 657 - hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2; 658 - hw.io_ports[IDE_SECTOR_OFFSET] = base + 3; 659 - hw.io_ports[IDE_LCYL_OFFSET] = base + 4; 660 - hw.io_ports[IDE_HCYL_OFFSET] = base + 5; 661 - hw.io_ports[IDE_SELECT_OFFSET] = base + 6; 662 - hw.io_ports[IDE_STATUS_OFFSET] = base + 7; 663 - hw.io_ports[IDE_CONTROL_OFFSET] = base + 10; 664 - 665 - hw.io_ports[IDE_IRQ_OFFSET] = 0; 654 + io_ports->data_addr = base; 655 + io_ports->error_addr = base + 1; 656 + io_ports->nsect_addr = base + 2; 657 + io_ports->lbal_addr = base + 3; 658 + io_ports->lbam_addr = base + 4; 659 + io_ports->lbah_addr = base + 5; 660 + io_ports->device_addr = base + 6; 661 + io_ports->status_addr = base + 7; 662 + io_ports->ctl_addr = base + 10; 666 663 667 664 if (pdev_is_sata(dev)) { 668 665 base = (unsigned long)addr; ··· 670 671 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; 671 672 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; 672 673 } 673 - 674 - memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports)); 675 674 676 675 hwif->irq = dev->irq; 677 676
+1 -1
drivers/ide/pci/trm290.c
··· 298 298 if (old != compat && old_mask == 0xff) { 299 299 /* leave lower 10 bits untouched */ 300 300 compat += (next_offset += 0x400); 301 - hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2; 301 + hwif->io_ports.ctl_addr = compat + 2; 302 302 outw(compat | 1, hwif->config_data); 303 303 new = inw(hwif->config_data); 304 304 printk(KERN_INFO "%s: control basereg workaround: "
+2 -2
drivers/ide/ppc/mpc8xx.c
··· 131 131 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) 132 132 static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port) 133 133 { 134 - unsigned long *p = hw->io_ports; 134 + unsigned long *p = hw->io_ports_array; 135 135 int i; 136 136 137 137 typedef struct { ··· 314 314 #if defined(CONFIG_IDE_EXT_DIRECT) 315 315 static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port) 316 316 { 317 - unsigned long *p = hw->io_ports; 317 + unsigned long *p = hw->io_ports_array; 318 318 int i; 319 319 320 320 u32 ide_phy_base;
+4 -3
drivers/ide/ppc/pmac.c
··· 417 417 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ 418 418 419 419 #define PMAC_IDE_REG(x) \ 420 - ((void __iomem *)((drive)->hwif->io_ports[IDE_DATA_OFFSET] + (x))) 420 + ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x))) 421 421 422 422 /* 423 423 * Apply the timings of the proper unit (master/slave) to the shared ··· 1086 1086 int i; 1087 1087 1088 1088 for (i = 0; i < 8; ++i) 1089 - hw->io_ports[i] = base + i * 0x10; 1090 - hw->io_ports[8] = base + 0x160; 1089 + hw->io_ports_array[i] = base + i * 0x10; 1090 + 1091 + hw->io_ports.ctl_addr = base + 0x160; 1091 1092 } 1092 1093 1093 1094 /*
+6 -7
drivers/scsi/ide-scsi.c
··· 258 258 259 259 if (ide_read_status(drive) & (BUSY_STAT | DRQ_STAT)) 260 260 /* force an abort */ 261 - hwif->OUTB(WIN_IDLEIMMEDIATE, 262 - hwif->io_ports[IDE_COMMAND_OFFSET]); 261 + hwif->OUTB(WIN_IDLEIMMEDIATE, hwif->io_ports.command_addr); 263 262 264 263 rq->errors++; 265 264 ··· 409 410 idescsi_end_request (drive, 1, 0); 410 411 return ide_stopped; 411 412 } 412 - bcount = (hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]) << 8) | 413 - hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]); 414 - ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 413 + bcount = (hwif->INB(hwif->io_ports.lbah_addr) << 8) | 414 + hwif->INB(hwif->io_ports.lbam_addr); 415 + ireason = hwif->INB(hwif->io_ports.nsect_addr); 415 416 416 417 if (ireason & CD) { 417 418 printk(KERN_ERR "ide-scsi: CoD != 0 in idescsi_pc_intr\n"); ··· 484 485 "initiated yet DRQ isn't asserted\n"); 485 486 return startstop; 486 487 } 487 - ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 488 + ireason = hwif->INB(hwif->io_ports.nsect_addr); 488 489 if ((ireason & CD) == 0 || (ireason & IO)) { 489 490 printk(KERN_ERR "ide-scsi: (IO,CoD) != (0,1) while " 490 491 "issuing a packet command\n"); ··· 574 575 return ide_started; 575 576 } else { 576 577 /* Issue the packet command */ 577 - hwif->OUTB(WIN_PACKETCMD, hwif->io_ports[IDE_COMMAND_OFFSET]); 578 + hwif->OUTB(WIN_PACKETCMD, hwif->io_ports.command_addr); 578 579 return idescsi_transfer_pc(drive); 579 580 } 580 581 }
+3 -3
include/asm-arm/arch-sa1100/ide.h
··· 37 37 38 38 memset(hw, 0, sizeof(*hw)); 39 39 40 - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { 41 - hw->io_ports[i] = reg; 40 + for (i = 0; i <= 7; i++) { 41 + hw->io_ports_array[i] = reg; 42 42 reg += regincr; 43 43 } 44 44 45 - hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; 45 + hw->io_ports.ctl_addr = ctrl_port; 46 46 47 47 if (irq) 48 48 *irq = 0;
+4 -7
include/asm-cris/arch-v10/ide.h
··· 59 59 int i; 60 60 61 61 /* fill in ports for ATA addresses 0 to 7 */ 62 - 63 - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { 64 - hw->io_ports[i] = data_port | 62 + for (i = 0; i <= 7; i++) { 63 + hw->io_ports_array[i] = data_port | 65 64 IO_FIELD(R_ATA_CTRL_DATA, addr, i) | 66 65 IO_STATE(R_ATA_CTRL_DATA, cs0, active); 67 66 } 68 67 69 68 /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */ 70 - 71 - hw->io_ports[IDE_CONTROL_OFFSET] = data_port | 69 + hw->io_ports.ctl_addr = data_port | 72 70 IO_FIELD(R_ATA_CTRL_DATA, addr, 6) | 73 71 IO_STATE(R_ATA_CTRL_DATA, cs1, active); 74 72 75 73 /* whats this for ? */ 76 - 77 - hw->io_ports[IDE_IRQ_OFFSET] = 0; 74 + hw->io_ports.irq_addr = 0; 78 75 } 79 76 80 77 static inline void ide_init_default_hwifs(void)
+39 -29
include/linux/ide.h
··· 61 61 */ 62 62 #define IDE_NR_PORTS (10) 63 63 64 - #define IDE_DATA_OFFSET (0) 65 - #define IDE_ERROR_OFFSET (1) 66 - #define IDE_NSECTOR_OFFSET (2) 67 - #define IDE_SECTOR_OFFSET (3) 68 - #define IDE_LCYL_OFFSET (4) 69 - #define IDE_HCYL_OFFSET (5) 70 - #define IDE_SELECT_OFFSET (6) 71 - #define IDE_STATUS_OFFSET (7) 72 - #define IDE_CONTROL_OFFSET (8) 73 - #define IDE_IRQ_OFFSET (9) 64 + struct ide_io_ports { 65 + unsigned long data_addr; 74 66 75 - #define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET 76 - #define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET 77 - #define IDE_ALTSTATUS_OFFSET IDE_CONTROL_OFFSET 78 - #define IDE_IREASON_OFFSET IDE_NSECTOR_OFFSET 79 - #define IDE_BCOUNTL_OFFSET IDE_LCYL_OFFSET 80 - #define IDE_BCOUNTH_OFFSET IDE_HCYL_OFFSET 67 + union { 68 + unsigned long error_addr; /* read: error */ 69 + unsigned long feature_addr; /* write: feature */ 70 + }; 71 + 72 + unsigned long nsect_addr; 73 + unsigned long lbal_addr; 74 + unsigned long lbam_addr; 75 + unsigned long lbah_addr; 76 + 77 + unsigned long device_addr; 78 + 79 + union { 80 + unsigned long status_addr; /*  read: status  */ 81 + unsigned long command_addr; /* write: command */ 82 + }; 83 + 84 + unsigned long ctl_addr; 85 + 86 + unsigned long irq_addr; 87 + }; 81 88 82 89 #define OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good)) 83 90 #define BAD_R_STAT (BUSY_STAT | ERR_STAT) ··· 163 156 * Structure to hold all information about the location of this port 164 157 */ 165 158 typedef struct hw_regs_s { 166 - unsigned long io_ports[IDE_NR_PORTS]; /* task file registers */ 159 + union { 160 + struct ide_io_ports io_ports; 161 + unsigned long io_ports_array[IDE_NR_PORTS]; 162 + }; 163 + 167 164 int irq; /* our irq number */ 168 165 ide_ack_intr_t *ack_intr; /* acknowledge interrupt */ 169 166 hwif_chipset_t chipset; ··· 183 172 { 184 173 unsigned int i; 185 174 186 - for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) 187 - hw->io_ports[i] = io_addr++; 175 + for (i = 0; i <= 7; i++) 176 + hw->io_ports_array[i] = io_addr++; 188 177 189 - hw->io_ports[IDE_CONTROL_OFFSET] = ctl_addr; 178 + hw->io_ports.ctl_addr = ctl_addr; 190 179 } 191 180 192 181 #include <asm/ide.h> ··· 435 424 436 425 char name[6]; /* name of interface, eg. "ide0" */ 437 426 438 - /* task file registers for pata and sata */ 439 - unsigned long io_ports[IDE_NR_PORTS]; 427 + struct ide_io_ports io_ports; 428 + 440 429 unsigned long sata_scr[SATA_NR_PORTS]; 441 430 442 431 ide_drive_t drives[MAX_DRIVES]; /* drive info */ ··· 1341 1330 { 1342 1331 ide_hwif_t *hwif = drive->hwif; 1343 1332 1344 - hwif->OUTB(drive->ctl | (on ? 0 : 2), 1345 - hwif->io_ports[IDE_CONTROL_OFFSET]); 1333 + hwif->OUTB(drive->ctl | (on ? 0 : 2), hwif->io_ports.ctl_addr); 1346 1334 } 1347 1335 1348 1336 static inline u8 ide_read_status(ide_drive_t *drive) 1349 1337 { 1350 1338 ide_hwif_t *hwif = drive->hwif; 1351 1339 1352 - return hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 1340 + return hwif->INB(hwif->io_ports.status_addr); 1353 1341 } 1354 1342 1355 1343 static inline u8 ide_read_altstatus(ide_drive_t *drive) 1356 1344 { 1357 1345 ide_hwif_t *hwif = drive->hwif; 1358 1346 1359 - return hwif->INB(hwif->io_ports[IDE_CONTROL_OFFSET]); 1347 + return hwif->INB(hwif->io_ports.ctl_addr); 1360 1348 } 1361 1349 1362 1350 static inline u8 ide_read_error(ide_drive_t *drive) 1363 1351 { 1364 1352 ide_hwif_t *hwif = drive->hwif; 1365 1353 1366 - return hwif->INB(hwif->io_ports[IDE_ERROR_OFFSET]); 1354 + return hwif->INB(hwif->io_ports.error_addr); 1367 1355 } 1368 1356 1369 1357 /* ··· 1375 1365 1376 1366 /* FIXME: use ->atapi_input_bytes */ 1377 1367 while (bcount--) 1378 - (void)hwif->INB(hwif->io_ports[IDE_DATA_OFFSET]); 1368 + (void)hwif->INB(hwif->io_ports.data_addr); 1379 1369 } 1380 1370 1381 1371 static inline void ide_atapi_write_zeros(ide_drive_t *drive, unsigned bcount) ··· 1384 1374 1385 1375 /* FIXME: use ->atapi_output_bytes */ 1386 1376 while (bcount--) 1387 - hwif->OUTB(0, hwif->io_ports[IDE_DATA_OFFSET]); 1377 + hwif->OUTB(0, hwif->io_ports.data_addr); 1388 1378 } 1389 1379 1390 1380 #endif /* _IDE_H */