Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branch 'mlx4-misc-improvements'

Tariq Toukan says:

====================
mlx4 misc improvements

This patchset contains several improvements and cleanups
from the team to the mlx4 Eth and core drivers.

Series generated against net-next commit:
4e8f2fc1a55d Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

Thanks,
Tariq.

v3:
* Patch 6/9: forgot to actually update the commit message in v2, now it is.

v2:
* Patch 1/9: used EOPNOTSUPP and not ENOTSUPP.
* Patch 3/9: dropped, to be submitted separately in the future.
* Patch 6/9: updated commit message.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

+228 -63
+21 -7
drivers/net/ethernet/mellanox/mlx4/en_ethtool.c
··· 902 902 struct mlx4_en_priv *priv = netdev_priv(dev); 903 903 struct mlx4_ptys_reg ptys_reg; 904 904 __be32 proto_admin; 905 + u8 cur_autoneg; 905 906 int ret; 906 907 907 908 u32 ptys_adv = ethtool2ptys_link_modes( ··· 932 931 return 0; 933 932 } 934 933 935 - proto_admin = link_ksettings->base.autoneg == AUTONEG_ENABLE ? 936 - cpu_to_be32(ptys_adv) : 937 - speed_set_ptys_admin(priv, speed, 938 - ptys_reg.eth_proto_cap); 934 + cur_autoneg = ptys_reg.flags & MLX4_PTYS_AN_DISABLE_ADMIN ? 935 + AUTONEG_DISABLE : AUTONEG_ENABLE; 936 + 937 + if (link_ksettings->base.autoneg == AUTONEG_DISABLE) { 938 + proto_admin = speed_set_ptys_admin(priv, speed, 939 + ptys_reg.eth_proto_cap); 940 + if ((be32_to_cpu(proto_admin) & 941 + (MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII) | 942 + MLX4_PROT_MASK(MLX4_1000BASE_KX))) && 943 + (ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP)) 944 + ptys_reg.flags |= MLX4_PTYS_AN_DISABLE_ADMIN; 945 + } else { 946 + proto_admin = cpu_to_be32(ptys_adv); 947 + ptys_reg.flags &= ~MLX4_PTYS_AN_DISABLE_ADMIN; 948 + } 939 949 940 950 proto_admin &= ptys_reg.eth_proto_cap; 941 951 if (!proto_admin) { ··· 954 942 return -EINVAL; /* nothing to change due to bad input */ 955 943 } 956 944 957 - if (proto_admin == ptys_reg.eth_proto_admin) 945 + if ((proto_admin == ptys_reg.eth_proto_admin) && 946 + ((ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP) && 947 + (link_ksettings->base.autoneg == cur_autoneg))) 958 948 return 0; /* Nothing to change */ 959 949 960 950 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n", ··· 1802 1788 netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]); 1803 1789 netif_set_real_num_rx_queues(dev, priv->rx_ring_num); 1804 1790 1805 - if (dev->num_tc) 1791 + if (netdev_get_num_tc(dev)) 1806 1792 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP); 1807 1793 1808 1794 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num[TX]); ··· 1994 1980 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1995 1981 break; 1996 1982 default: 1997 - return -ENOSYS; 1983 + return -EINVAL; 1998 1984 } 1999 1985 2000 1986 return 0;
+8
drivers/net/ethernet/mellanox/mlx4/en_netdev.c
··· 1695 1695 priv->port, err); 1696 1696 goto tx_err; 1697 1697 } 1698 + 1699 + err = mlx4_SET_PORT_user_mtu(mdev->dev, priv->port, dev->mtu); 1700 + if (err) { 1701 + en_err(priv, "Failed to pass user MTU(%d) to Firmware for port %d, with error %d\n", 1702 + dev->mtu, priv->port, err); 1703 + goto tx_err; 1704 + } 1705 + 1698 1706 /* Set default qp number */ 1699 1707 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0); 1700 1708 if (err) {
-1
drivers/net/ethernet/mellanox/mlx4/en_port.h
··· 35 35 #define _MLX4_EN_PORT_H_ 36 36 37 37 38 - #define SET_PORT_GEN_ALL_VALID 0x7 39 38 #define SET_PORT_PROMISC_SHIFT 31 40 39 #define SET_PORT_MC_PROMISC_SHIFT 30 41 40
+1 -1
drivers/net/ethernet/mellanox/mlx4/en_tx.c
··· 710 710 u16 rings_p_up = priv->num_tx_rings_p_up; 711 711 u8 up = 0; 712 712 713 - if (dev->num_tc) 713 + if (netdev_get_num_tc(dev)) 714 714 return skb_tx_hash(dev, skb); 715 715 716 716 if (skb_vlan_tag_present(skb))
+3 -3
drivers/net/ethernet/mellanox/mlx4/fw.c
··· 672 672 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 673 673 func_cap->physical_port = field; 674 674 if (func_cap->physical_port != gen_or_port) { 675 - err = -ENOSYS; 675 + err = -EINVAL; 676 676 goto out; 677 677 } 678 678 ··· 1875 1875 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1876 1876 1877 1877 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1878 - (ilog2(cache_line_size()) - 4) << 5; 1878 + ((ilog2(cache_line_size()) - 4) << 5) | (1 << 4); 1879 1879 1880 1880 #if defined(__LITTLE_ENDIAN) 1881 1881 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); ··· 2983 2983 return PTR_ERR(mailbox); 2984 2984 context = mailbox->buf; 2985 2985 2986 - context->v_ignore_fcs |= SET_PORT_GEN_PHV_VALID; 2986 + context->flags2 |= SET_PORT_GEN_PHV_VALID; 2987 2987 if (phv_bit) 2988 2988 context->phv_en |= SET_PORT_GEN_PHV_EN; 2989 2989
+3 -3
drivers/net/ethernet/mellanox/mlx4/main.c
··· 838 838 */ 839 839 if (hca_param.global_caps) { 840 840 mlx4_err(dev, "Unknown hca global capabilities\n"); 841 - return -ENOSYS; 841 + return -EINVAL; 842 842 } 843 843 844 844 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; ··· 896 896 PF_CONTEXT_BEHAVIOUR_MASK) { 897 897 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 898 898 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK); 899 - return -ENOSYS; 899 + return -EINVAL; 900 900 } 901 901 902 902 dev->caps.num_ports = func_cap.num_ports; ··· 3492 3492 mlx4_enable_msi_x(dev); 3493 3493 if ((mlx4_is_mfunc(dev)) && 3494 3494 !(dev->flags & MLX4_FLAG_MSI_X)) { 3495 - err = -ENOSYS; 3495 + err = -EOPNOTSUPP; 3496 3496 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 3497 3497 goto err_free_eq; 3498 3498 }
+8 -3
drivers/net/ethernet/mellanox/mlx4/mlx4.h
··· 487 487 bool vst_qinq_supported; 488 488 u8 function; 489 489 dma_addr_t vhcr_dma; 490 + u16 user_mtu[MLX4_MAX_PORTS + 1]; 490 491 u16 mtu[MLX4_MAX_PORTS + 1]; 491 492 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 492 493 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; ··· 591 590 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 592 591 int init_port_ref[MLX4_MAX_PORTS + 1]; 593 592 u16 max_mtu[MLX4_MAX_PORTS + 1]; 593 + u16 max_user_mtu[MLX4_MAX_PORTS + 1]; 594 594 u8 pptx; 595 595 u8 pprx; 596 596 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; ··· 776 774 int max; 777 775 }; 778 776 779 - #define SET_PORT_GEN_ALL_VALID 0x7 777 + #define SET_PORT_GEN_ALL_VALID (MLX4_FLAG_V_MTU_MASK | \ 778 + MLX4_FLAG_V_PPRX_MASK | \ 779 + MLX4_FLAG_V_PPTX_MASK) 780 780 #define SET_PORT_PROMISC_SHIFT 31 781 781 #define SET_PORT_MC_PROMISC_SHIFT 30 782 782 ··· 791 787 792 788 struct mlx4_set_port_general_context { 793 789 u16 reserved1; 794 - u8 v_ignore_fcs; 790 + u8 flags2; 795 791 u8 flags; 796 792 union { 797 793 u8 ignore_fcs; ··· 807 803 u16 reserved4; 808 804 u32 reserved5; 809 805 u8 phv_en; 810 - u8 reserved6[3]; 806 + u8 reserved6[5]; 807 + __be16 user_mtu; 811 808 }; 812 809 813 810 struct mlx4_set_port_rqp_calc_context {
+131 -39
drivers/net/ethernet/mellanox/mlx4/port.c
··· 50 50 #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL 51 51 #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL 52 52 53 - #define MLX4_FLAG_V_IGNORE_FCS_MASK 0x2 53 + #define MLX4_FLAG2_V_IGNORE_FCS_MASK BIT(1) 54 + #define MLX4_FLAG2_V_USER_MTU_MASK BIT(5) 55 + #define MLX4_FLAG_V_MTU_MASK BIT(0) 56 + #define MLX4_FLAG_V_PPRX_MASK BIT(1) 57 + #define MLX4_FLAG_V_PPTX_MASK BIT(2) 54 58 #define MLX4_IGNORE_FCS_MASK 0x1 55 59 #define MLX4_TC_MAX_NUMBER 8 56 60 ··· 1243 1239 return; 1244 1240 } 1245 1241 1242 + static void 1243 + mlx4_en_set_port_mtu(struct mlx4_dev *dev, int slave, int port, 1244 + struct mlx4_set_port_general_context *gen_context) 1245 + { 1246 + struct mlx4_priv *priv = mlx4_priv(dev); 1247 + struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master; 1248 + struct mlx4_slave_state *slave_st = &master->slave_state[slave]; 1249 + u16 mtu, prev_mtu; 1250 + 1251 + /* Mtu is configured as the max USER_MTU among all 1252 + * the functions on the port. 1253 + */ 1254 + mtu = be16_to_cpu(gen_context->mtu); 1255 + mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port] + 1256 + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 1257 + prev_mtu = slave_st->mtu[port]; 1258 + slave_st->mtu[port] = mtu; 1259 + if (mtu > master->max_mtu[port]) 1260 + master->max_mtu[port] = mtu; 1261 + if (mtu < prev_mtu && prev_mtu == master->max_mtu[port]) { 1262 + int i; 1263 + 1264 + slave_st->mtu[port] = mtu; 1265 + master->max_mtu[port] = mtu; 1266 + for (i = 0; i < dev->num_slaves; i++) 1267 + master->max_mtu[port] = 1268 + max_t(u16, master->max_mtu[port], 1269 + master->slave_state[i].mtu[port]); 1270 + } 1271 + gen_context->mtu = cpu_to_be16(master->max_mtu[port]); 1272 + } 1273 + 1274 + static void 1275 + mlx4_en_set_port_user_mtu(struct mlx4_dev *dev, int slave, int port, 1276 + struct mlx4_set_port_general_context *gen_context) 1277 + { 1278 + struct mlx4_priv *priv = mlx4_priv(dev); 1279 + struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master; 1280 + struct mlx4_slave_state *slave_st = &master->slave_state[slave]; 1281 + u16 user_mtu, prev_user_mtu; 1282 + 1283 + /* User Mtu is configured as the max USER_MTU among all 1284 + * the functions on the port. 1285 + */ 1286 + user_mtu = be16_to_cpu(gen_context->user_mtu); 1287 + user_mtu = min_t(int, user_mtu, dev->caps.eth_mtu_cap[port]); 1288 + prev_user_mtu = slave_st->user_mtu[port]; 1289 + slave_st->user_mtu[port] = user_mtu; 1290 + if (user_mtu > master->max_user_mtu[port]) 1291 + master->max_user_mtu[port] = user_mtu; 1292 + if (user_mtu < prev_user_mtu && 1293 + prev_user_mtu == master->max_user_mtu[port]) { 1294 + int i; 1295 + 1296 + slave_st->user_mtu[port] = user_mtu; 1297 + master->max_user_mtu[port] = user_mtu; 1298 + for (i = 0; i < dev->num_slaves; i++) 1299 + master->max_user_mtu[port] = 1300 + max_t(u16, master->max_user_mtu[port], 1301 + master->slave_state[i].user_mtu[port]); 1302 + } 1303 + gen_context->user_mtu = cpu_to_be16(master->max_user_mtu[port]); 1304 + } 1305 + 1306 + static void 1307 + mlx4_en_set_port_global_pause(struct mlx4_dev *dev, int slave, 1308 + struct mlx4_set_port_general_context *gen_context) 1309 + { 1310 + struct mlx4_priv *priv = mlx4_priv(dev); 1311 + struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master; 1312 + 1313 + /* Slave cannot change Global Pause configuration */ 1314 + if (slave != mlx4_master_func_num(dev) && 1315 + (gen_context->pptx != master->pptx || 1316 + gen_context->pprx != master->pprx)) { 1317 + gen_context->pptx = master->pptx; 1318 + gen_context->pprx = master->pprx; 1319 + mlx4_warn(dev, "denying Global Pause change for slave:%d\n", 1320 + slave); 1321 + } else { 1322 + master->pptx = gen_context->pptx; 1323 + master->pprx = gen_context->pprx; 1324 + } 1325 + } 1326 + 1246 1327 static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod, 1247 1328 u8 op_mod, struct mlx4_cmd_mailbox *inbox) 1248 1329 { 1249 1330 struct mlx4_priv *priv = mlx4_priv(dev); 1250 1331 struct mlx4_port_info *port_info; 1251 - struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master; 1252 - struct mlx4_slave_state *slave_st = &master->slave_state[slave]; 1253 1332 struct mlx4_set_port_rqp_calc_context *qpn_context; 1254 1333 struct mlx4_set_port_general_context *gen_context; 1255 1334 struct mlx4_roce_gid_entry *gid_entry_tbl, *gid_entry_mbox, *gid_entry_mb1; ··· 1343 1256 int base; 1344 1257 u32 in_modifier; 1345 1258 u32 promisc; 1346 - u16 mtu, prev_mtu; 1347 1259 int err; 1348 1260 int i, j; 1349 1261 int offset; ··· 1355 1269 is_eth = op_mod; 1356 1270 port_info = &priv->port[port]; 1357 1271 1358 - /* Slaves cannot perform SET_PORT operations except changing MTU */ 1272 + /* Slaves cannot perform SET_PORT operations, 1273 + * except for changing MTU and USER_MTU. 1274 + */ 1359 1275 if (is_eth) { 1360 1276 if (slave != dev->caps.function && 1361 1277 in_modifier != MLX4_SET_PORT_GENERAL && ··· 1385 1297 break; 1386 1298 case MLX4_SET_PORT_GENERAL: 1387 1299 gen_context = inbox->buf; 1388 - /* Mtu is configured as the max MTU among all the 1389 - * the functions on the port. */ 1390 - mtu = be16_to_cpu(gen_context->mtu); 1391 - mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port] + 1392 - ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 1393 - prev_mtu = slave_st->mtu[port]; 1394 - slave_st->mtu[port] = mtu; 1395 - if (mtu > master->max_mtu[port]) 1396 - master->max_mtu[port] = mtu; 1397 - if (mtu < prev_mtu && prev_mtu == 1398 - master->max_mtu[port]) { 1399 - slave_st->mtu[port] = mtu; 1400 - master->max_mtu[port] = mtu; 1401 - for (i = 0; i < dev->num_slaves; i++) { 1402 - master->max_mtu[port] = 1403 - max(master->max_mtu[port], 1404 - master->slave_state[i].mtu[port]); 1405 - } 1406 - } 1407 1300 1408 - gen_context->mtu = cpu_to_be16(master->max_mtu[port]); 1409 - /* Slave cannot change Global Pause configuration */ 1410 - if (slave != mlx4_master_func_num(dev) && 1411 - ((gen_context->pptx != master->pptx) || 1412 - (gen_context->pprx != master->pprx))) { 1413 - gen_context->pptx = master->pptx; 1414 - gen_context->pprx = master->pprx; 1415 - mlx4_warn(dev, 1416 - "denying Global Pause change for slave:%d\n", 1417 - slave); 1418 - } else { 1419 - master->pptx = gen_context->pptx; 1420 - master->pprx = gen_context->pprx; 1421 - } 1301 + if (gen_context->flags & MLX4_FLAG_V_MTU_MASK) 1302 + mlx4_en_set_port_mtu(dev, slave, port, 1303 + gen_context); 1304 + 1305 + if (gen_context->flags2 & MLX4_FLAG2_V_USER_MTU_MASK) 1306 + mlx4_en_set_port_user_mtu(dev, slave, port, 1307 + gen_context); 1308 + 1309 + if (gen_context->flags & 1310 + (MLX4_FLAG_V_PPRX_MASK || MLX4_FLAG_V_PPTX_MASK)) 1311 + mlx4_en_set_port_global_pause(dev, slave, 1312 + gen_context); 1313 + 1422 1314 break; 1423 1315 case MLX4_SET_PORT_GID_TABLE: 1424 1316 /* change to MULTIPLE entries: number of guest's gids ··· 1676 1608 } 1677 1609 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc); 1678 1610 1611 + int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu) 1612 + { 1613 + struct mlx4_cmd_mailbox *mailbox; 1614 + struct mlx4_set_port_general_context *context; 1615 + u32 in_mod; 1616 + int err; 1617 + 1618 + mailbox = mlx4_alloc_cmd_mailbox(dev); 1619 + if (IS_ERR(mailbox)) 1620 + return PTR_ERR(mailbox); 1621 + context = mailbox->buf; 1622 + context->flags2 |= MLX4_FLAG2_V_USER_MTU_MASK; 1623 + context->user_mtu = cpu_to_be16(user_mtu); 1624 + 1625 + in_mod = MLX4_SET_PORT_GENERAL << 8 | port; 1626 + err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, 1627 + MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 1628 + MLX4_CMD_WRAPPED); 1629 + 1630 + mlx4_free_cmd_mailbox(dev, mailbox); 1631 + return err; 1632 + } 1633 + EXPORT_SYMBOL(mlx4_SET_PORT_user_mtu); 1634 + 1679 1635 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, u8 ignore_fcs_value) 1680 1636 { 1681 1637 struct mlx4_cmd_mailbox *mailbox; ··· 1711 1619 if (IS_ERR(mailbox)) 1712 1620 return PTR_ERR(mailbox); 1713 1621 context = mailbox->buf; 1714 - context->v_ignore_fcs |= MLX4_FLAG_V_IGNORE_FCS_MASK; 1622 + context->flags2 |= MLX4_FLAG2_V_IGNORE_FCS_MASK; 1715 1623 if (ignore_fcs_value) 1716 1624 context->ignore_fcs |= MLX4_IGNORE_FCS_MASK; 1717 1625 else
+46 -5
drivers/net/ethernet/mellanox/mlx4/resource_tracker.c
··· 77 77 int from_state; 78 78 int to_state; 79 79 int removing; 80 + const char *func_name; 80 81 }; 81 82 82 83 enum { ··· 838 837 return dev->caps.num_mpts - 1; 839 838 } 840 839 840 + static const char *mlx4_resource_type_to_str(enum mlx4_resource t) 841 + { 842 + switch (t) { 843 + case RES_QP: 844 + return "QP"; 845 + case RES_CQ: 846 + return "CQ"; 847 + case RES_SRQ: 848 + return "SRQ"; 849 + case RES_XRCD: 850 + return "XRCD"; 851 + case RES_MPT: 852 + return "MPT"; 853 + case RES_MTT: 854 + return "MTT"; 855 + case RES_MAC: 856 + return "MAC"; 857 + case RES_VLAN: 858 + return "VLAN"; 859 + case RES_COUNTER: 860 + return "COUNTER"; 861 + case RES_FS_RULE: 862 + return "FS_RULE"; 863 + case RES_EQ: 864 + return "EQ"; 865 + default: 866 + return "INVALID RESOURCE"; 867 + } 868 + } 869 + 841 870 static void *find_res(struct mlx4_dev *dev, u64 res_id, 842 871 enum mlx4_resource type) 843 872 { ··· 877 846 res_id); 878 847 } 879 848 880 - static int get_res(struct mlx4_dev *dev, int slave, u64 res_id, 881 - enum mlx4_resource type, 882 - void *res) 849 + static int _get_res(struct mlx4_dev *dev, int slave, u64 res_id, 850 + enum mlx4_resource type, 851 + void *res, const char *func_name) 883 852 { 884 853 struct res_common *r; 885 854 int err = 0; ··· 892 861 } 893 862 894 863 if (r->state == RES_ANY_BUSY) { 864 + mlx4_warn(dev, 865 + "%s(%d) trying to get resource %llx of type %s, but it's already taken by %s\n", 866 + func_name, slave, res_id, mlx4_resource_type_to_str(type), 867 + r->func_name); 895 868 err = -EBUSY; 896 869 goto exit; 897 870 } ··· 907 872 908 873 r->from_state = r->state; 909 874 r->state = RES_ANY_BUSY; 875 + r->func_name = func_name; 910 876 911 877 if (res) 912 878 *((struct res_common **)res) = r; ··· 916 880 spin_unlock_irq(mlx4_tlock(dev)); 917 881 return err; 918 882 } 883 + 884 + #define get_res(dev, slave, res_id, type, res) \ 885 + _get_res((dev), (slave), (res_id), (type), (res), __func__) 919 886 920 887 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 921 888 enum mlx4_resource type, ··· 950 911 951 912 spin_lock_irq(mlx4_tlock(dev)); 952 913 r = find_res(dev, res_id, type); 953 - if (r) 914 + if (r) { 954 915 r->state = r->from_state; 916 + r->func_name = ""; 917 + } 955 918 spin_unlock_irq(mlx4_tlock(dev)); 956 919 } 957 920 ··· 1437 1396 case RES_MTT: 1438 1397 return remove_mtt_ok((struct res_mtt *)res, extra); 1439 1398 case RES_MAC: 1440 - return -ENOSYS; 1399 + return -EOPNOTSUPP; 1441 1400 case RES_EQ: 1442 1401 return remove_eq_ok((struct res_eq *)res); 1443 1402 case RES_COUNTER:
+7 -1
include/linux/mlx4/device.h
··· 1374 1374 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1375 1375 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1376 1376 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1377 + int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu); 1377 1378 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1378 1379 u8 promisc); 1379 1380 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); ··· 1540 1539 MLX4_PTYS_EN = 1<<2, 1541 1540 }; 1542 1541 1542 + enum mlx4_ptys_flags { 1543 + MLX4_PTYS_AN_DISABLE_CAP = 1 << 5, 1544 + MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6, 1545 + }; 1546 + 1543 1547 struct mlx4_ptys_reg { 1544 - u8 resrvd1; 1548 + u8 flags; 1545 1549 u8 local_port; 1546 1550 u8 resrvd2; 1547 1551 u8 proto_mask;