tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

[media] davinci vpbe: add dm365 and dm355 specific OSD changes

Add OSD block changes to enable dm365 and dm355 for vpbe driver.
Changes are based on version number of OSD, which have incremental
changes over 644x OSD hardware interms of few registers.

VPBE_VERSION_2 = dm365 specific
VPBE_VERSION_3 = dm355 specific

Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

authored by

Manjunath Hadli and committed by
Mauro Carvalho Chehab 4be54445 9a7f95ad

+432 -41
+432 -41
drivers/media/video/davinci/vpbe_osd.c
··· 248 248 osd_modify(sd, OSD_OSDWIN0MD_ATN0E, 249 249 enable ? OSD_OSDWIN0MD_ATN0E : 0, 250 250 OSD_OSDWIN0MD); 251 + if (sd->vpbe_type == VPBE_VERSION_1) 252 + osd_modify(sd, OSD_OSDWIN0MD_ATN0E, 253 + enable ? OSD_OSDWIN0MD_ATN0E : 0, 254 + OSD_OSDWIN0MD); 255 + else if ((sd->vpbe_type == VPBE_VERSION_3) || 256 + (sd->vpbe_type == VPBE_VERSION_2)) 257 + osd_modify(sd, OSD_EXTMODE_ATNOSD0EN, 258 + enable ? OSD_EXTMODE_ATNOSD0EN : 0, 259 + OSD_EXTMODE); 251 260 break; 252 261 case OSDWIN_OSD1: 253 262 osd_modify(sd, OSD_OSDWIN1MD_ATN1E, 254 263 enable ? OSD_OSDWIN1MD_ATN1E : 0, 255 264 OSD_OSDWIN1MD); 265 + if (sd->vpbe_type == VPBE_VERSION_1) 266 + osd_modify(sd, OSD_OSDWIN1MD_ATN1E, 267 + enable ? OSD_OSDWIN1MD_ATN1E : 0, 268 + OSD_OSDWIN1MD); 269 + else if ((sd->vpbe_type == VPBE_VERSION_3) || 270 + (sd->vpbe_type == VPBE_VERSION_2)) 271 + osd_modify(sd, OSD_EXTMODE_ATNOSD1EN, 272 + enable ? OSD_EXTMODE_ATNOSD1EN : 0, 273 + OSD_EXTMODE); 256 274 break; 257 275 } 258 276 } ··· 291 273 } 292 274 } 293 275 276 + static void _osd_enable_rgb888_pixblend(struct osd_state *sd, 277 + enum osd_win_layer osdwin) 278 + { 279 + 280 + osd_modify(sd, OSD_MISCCTL_BLDSEL, 0, OSD_MISCCTL); 281 + switch (osdwin) { 282 + case OSDWIN_OSD0: 283 + osd_modify(sd, OSD_EXTMODE_OSD0BLDCHR, 284 + OSD_EXTMODE_OSD0BLDCHR, OSD_EXTMODE); 285 + break; 286 + case OSDWIN_OSD1: 287 + osd_modify(sd, OSD_EXTMODE_OSD1BLDCHR, 288 + OSD_EXTMODE_OSD1BLDCHR, OSD_EXTMODE); 289 + break; 290 + } 291 + } 292 + 294 293 static void _osd_enable_color_key(struct osd_state *sd, 295 294 enum osd_win_layer osdwin, 296 295 unsigned colorkey, 297 296 enum osd_pix_format pixfmt) 298 297 { 299 298 switch (pixfmt) { 299 + case PIXFMT_1BPP: 300 + case PIXFMT_2BPP: 301 + case PIXFMT_4BPP: 302 + case PIXFMT_8BPP: 303 + if (sd->vpbe_type == VPBE_VERSION_3) { 304 + switch (osdwin) { 305 + case OSDWIN_OSD0: 306 + osd_modify(sd, OSD_TRANSPBMPIDX_BMP0, 307 + colorkey << 308 + OSD_TRANSPBMPIDX_BMP0_SHIFT, 309 + OSD_TRANSPBMPIDX); 310 + break; 311 + case OSDWIN_OSD1: 312 + osd_modify(sd, OSD_TRANSPBMPIDX_BMP1, 313 + colorkey << 314 + OSD_TRANSPBMPIDX_BMP1_SHIFT, 315 + OSD_TRANSPBMPIDX); 316 + break; 317 + } 318 + } 319 + break; 300 320 case PIXFMT_RGB565: 301 - osd_write(sd, colorkey & OSD_TRANSPVAL_RGBTRANS, 302 - OSD_TRANSPVAL); 321 + if (sd->vpbe_type == VPBE_VERSION_1) 322 + osd_write(sd, colorkey & OSD_TRANSPVAL_RGBTRANS, 323 + OSD_TRANSPVAL); 324 + else if (sd->vpbe_type == VPBE_VERSION_3) 325 + osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL, 326 + OSD_TRANSPVALL); 327 + break; 328 + case PIXFMT_YCbCrI: 329 + case PIXFMT_YCrCbI: 330 + if (sd->vpbe_type == VPBE_VERSION_3) 331 + osd_modify(sd, OSD_TRANSPVALU_Y, colorkey, 332 + OSD_TRANSPVALU); 333 + break; 334 + case PIXFMT_RGB888: 335 + if (sd->vpbe_type == VPBE_VERSION_3) { 336 + osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL, 337 + OSD_TRANSPVALL); 338 + osd_modify(sd, OSD_TRANSPVALU_RGBU, colorkey >> 16, 339 + OSD_TRANSPVALU); 340 + } 303 341 break; 304 342 default: 305 343 break; ··· 544 470 return 0; 545 471 } 546 472 473 + #define OSD_SRC_ADDR_HIGH4 0x7800000 474 + #define OSD_SRC_ADDR_HIGH7 0x7F0000 475 + #define OSD_SRCADD_OFSET_SFT 23 476 + #define OSD_SRCADD_ADD_SFT 16 477 + #define OSD_WINADL_MASK 0xFFFF 478 + #define OSD_WINOFST_MASK 0x1000 479 + #define VPBE_REG_BASE 0x80000000 480 + 547 481 static void _osd_start_layer(struct osd_state *sd, enum osd_layer layer, 548 482 unsigned long fb_base_phys, 549 483 unsigned long cbcr_ofst) 550 484 { 551 - switch (layer) { 552 - case WIN_OSD0: 553 - osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN0ADR); 554 - break; 555 - case WIN_VID0: 556 - osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR); 557 - break; 558 - case WIN_OSD1: 559 - osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN1ADR); 560 - break; 561 - case WIN_VID1: 562 - osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN1ADR); 563 - break; 485 + 486 + if (sd->vpbe_type == VPBE_VERSION_1) { 487 + switch (layer) { 488 + case WIN_OSD0: 489 + osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN0ADR); 490 + break; 491 + case WIN_VID0: 492 + osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR); 493 + break; 494 + case WIN_OSD1: 495 + osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN1ADR); 496 + break; 497 + case WIN_VID1: 498 + osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN1ADR); 499 + break; 500 + } 501 + } else if (sd->vpbe_type == VPBE_VERSION_3) { 502 + unsigned long fb_offset_32 = 503 + (fb_base_phys - VPBE_REG_BASE) >> 5; 504 + 505 + switch (layer) { 506 + case WIN_OSD0: 507 + osd_modify(sd, OSD_OSDWINADH_O0AH, 508 + fb_offset_32 >> (OSD_SRCADD_ADD_SFT - 509 + OSD_OSDWINADH_O0AH_SHIFT), 510 + OSD_OSDWINADH); 511 + osd_write(sd, fb_offset_32 & OSD_OSDWIN0ADL_O0AL, 512 + OSD_OSDWIN0ADL); 513 + break; 514 + case WIN_VID0: 515 + osd_modify(sd, OSD_VIDWINADH_V0AH, 516 + fb_offset_32 >> (OSD_SRCADD_ADD_SFT - 517 + OSD_VIDWINADH_V0AH_SHIFT), 518 + OSD_VIDWINADH); 519 + osd_write(sd, fb_offset_32 & OSD_VIDWIN0ADL_V0AL, 520 + OSD_VIDWIN0ADL); 521 + break; 522 + case WIN_OSD1: 523 + osd_modify(sd, OSD_OSDWINADH_O1AH, 524 + fb_offset_32 >> (OSD_SRCADD_ADD_SFT - 525 + OSD_OSDWINADH_O1AH_SHIFT), 526 + OSD_OSDWINADH); 527 + osd_write(sd, fb_offset_32 & OSD_OSDWIN1ADL_O1AL, 528 + OSD_OSDWIN1ADL); 529 + break; 530 + case WIN_VID1: 531 + osd_modify(sd, OSD_VIDWINADH_V1AH, 532 + fb_offset_32 >> (OSD_SRCADD_ADD_SFT - 533 + OSD_VIDWINADH_V1AH_SHIFT), 534 + OSD_VIDWINADH); 535 + osd_write(sd, fb_offset_32 & OSD_VIDWIN1ADL_V1AL, 536 + OSD_VIDWIN1ADL); 537 + break; 538 + } 539 + } else if (sd->vpbe_type == VPBE_VERSION_2) { 540 + struct osd_window_state *win = &sd->win[layer]; 541 + unsigned long fb_offset_32, cbcr_offset_32; 542 + 543 + fb_offset_32 = fb_base_phys - VPBE_REG_BASE; 544 + if (cbcr_ofst) 545 + cbcr_offset_32 = cbcr_ofst; 546 + else 547 + cbcr_offset_32 = win->lconfig.line_length * 548 + win->lconfig.ysize; 549 + cbcr_offset_32 += fb_offset_32; 550 + fb_offset_32 = fb_offset_32 >> 5; 551 + cbcr_offset_32 = cbcr_offset_32 >> 5; 552 + /* 553 + * DM365: start address is 27-bit long address b26 - b23 are 554 + * in offset register b12 - b9, and * bit 26 has to be '1' 555 + */ 556 + if (win->lconfig.pixfmt == PIXFMT_NV12) { 557 + switch (layer) { 558 + case WIN_VID0: 559 + case WIN_VID1: 560 + /* Y is in VID0 */ 561 + osd_modify(sd, OSD_VIDWIN0OFST_V0AH, 562 + ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >> 563 + (OSD_SRCADD_OFSET_SFT - 564 + OSD_WINOFST_AH_SHIFT)) | 565 + OSD_WINOFST_MASK, OSD_VIDWIN0OFST); 566 + osd_modify(sd, OSD_VIDWINADH_V0AH, 567 + (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >> 568 + (OSD_SRCADD_ADD_SFT - 569 + OSD_VIDWINADH_V0AH_SHIFT), 570 + OSD_VIDWINADH); 571 + osd_write(sd, fb_offset_32 & OSD_WINADL_MASK, 572 + OSD_VIDWIN0ADL); 573 + /* CbCr is in VID1 */ 574 + osd_modify(sd, OSD_VIDWIN1OFST_V1AH, 575 + ((cbcr_offset_32 & 576 + OSD_SRC_ADDR_HIGH4) >> 577 + (OSD_SRCADD_OFSET_SFT - 578 + OSD_WINOFST_AH_SHIFT)) | 579 + OSD_WINOFST_MASK, OSD_VIDWIN1OFST); 580 + osd_modify(sd, OSD_VIDWINADH_V1AH, 581 + (cbcr_offset_32 & 582 + OSD_SRC_ADDR_HIGH7) >> 583 + (OSD_SRCADD_ADD_SFT - 584 + OSD_VIDWINADH_V1AH_SHIFT), 585 + OSD_VIDWINADH); 586 + osd_write(sd, cbcr_offset_32 & OSD_WINADL_MASK, 587 + OSD_VIDWIN1ADL); 588 + break; 589 + default: 590 + break; 591 + } 592 + } 593 + 594 + switch (layer) { 595 + case WIN_OSD0: 596 + osd_modify(sd, OSD_OSDWIN0OFST_O0AH, 597 + ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >> 598 + (OSD_SRCADD_OFSET_SFT - 599 + OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK, 600 + OSD_OSDWIN0OFST); 601 + osd_modify(sd, OSD_OSDWINADH_O0AH, 602 + (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >> 603 + (OSD_SRCADD_ADD_SFT - 604 + OSD_OSDWINADH_O0AH_SHIFT), OSD_OSDWINADH); 605 + osd_write(sd, fb_offset_32 & OSD_WINADL_MASK, 606 + OSD_OSDWIN0ADL); 607 + break; 608 + case WIN_VID0: 609 + if (win->lconfig.pixfmt != PIXFMT_NV12) { 610 + osd_modify(sd, OSD_VIDWIN0OFST_V0AH, 611 + ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >> 612 + (OSD_SRCADD_OFSET_SFT - 613 + OSD_WINOFST_AH_SHIFT)) | 614 + OSD_WINOFST_MASK, OSD_VIDWIN0OFST); 615 + osd_modify(sd, OSD_VIDWINADH_V0AH, 616 + (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >> 617 + (OSD_SRCADD_ADD_SFT - 618 + OSD_VIDWINADH_V0AH_SHIFT), 619 + OSD_VIDWINADH); 620 + osd_write(sd, fb_offset_32 & OSD_WINADL_MASK, 621 + OSD_VIDWIN0ADL); 622 + } 623 + break; 624 + case WIN_OSD1: 625 + osd_modify(sd, OSD_OSDWIN1OFST_O1AH, 626 + ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >> 627 + (OSD_SRCADD_OFSET_SFT - 628 + OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK, 629 + OSD_OSDWIN1OFST); 630 + osd_modify(sd, OSD_OSDWINADH_O1AH, 631 + (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >> 632 + (OSD_SRCADD_ADD_SFT - 633 + OSD_OSDWINADH_O1AH_SHIFT), 634 + OSD_OSDWINADH); 635 + osd_write(sd, fb_offset_32 & OSD_WINADL_MASK, 636 + OSD_OSDWIN1ADL); 637 + break; 638 + case WIN_VID1: 639 + if (win->lconfig.pixfmt != PIXFMT_NV12) { 640 + osd_modify(sd, OSD_VIDWIN1OFST_V1AH, 641 + ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >> 642 + (OSD_SRCADD_OFSET_SFT - 643 + OSD_WINOFST_AH_SHIFT)) | 644 + OSD_WINOFST_MASK, OSD_VIDWIN1OFST); 645 + osd_modify(sd, OSD_VIDWINADH_V1AH, 646 + (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >> 647 + (OSD_SRCADD_ADD_SFT - 648 + OSD_VIDWINADH_V1AH_SHIFT), 649 + OSD_VIDWINADH); 650 + osd_write(sd, fb_offset_32 & OSD_WINADL_MASK, 651 + OSD_VIDWIN1ADL); 652 + } 653 + break; 654 + } 564 655 } 565 656 } 566 657 ··· 784 545 { 785 546 struct osd_state *osd = sd; 786 547 struct osd_window_state *win = &osd->win[layer]; 787 - int bad_config; 548 + int bad_config = 0; 788 549 789 550 /* verify that the pixel format is compatible with the layer */ 790 551 switch (lconfig->pixfmt) { ··· 793 554 case PIXFMT_4BPP: 794 555 case PIXFMT_8BPP: 795 556 case PIXFMT_RGB565: 796 - bad_config = !is_osd_win(layer); 557 + if (osd->vpbe_type == VPBE_VERSION_1) 558 + bad_config = !is_vid_win(layer); 797 559 break; 798 560 case PIXFMT_YCbCrI: 799 561 case PIXFMT_YCrCbI: 800 562 bad_config = !is_vid_win(layer); 801 563 break; 802 564 case PIXFMT_RGB888: 803 - bad_config = !is_vid_win(layer); 565 + if (osd->vpbe_type == VPBE_VERSION_1) 566 + bad_config = !is_vid_win(layer); 567 + else if ((osd->vpbe_type == VPBE_VERSION_3) || 568 + (osd->vpbe_type == VPBE_VERSION_2)) 569 + bad_config = !is_osd_win(layer); 804 570 break; 805 571 case PIXFMT_NV12: 806 - bad_config = 1; 572 + if (osd->vpbe_type != VPBE_VERSION_2) 573 + bad_config = 1; 574 + else 575 + bad_config = is_osd_win(layer); 807 576 break; 808 577 case PIXFMT_OSD_ATTR: 809 578 bad_config = (layer != WIN_OSD1); ··· 831 584 832 585 /* DM6446: */ 833 586 /* only one OSD window at a time can use RGB pixel formats */ 834 - if (is_osd_win(layer) && is_rgb_pixfmt(lconfig->pixfmt)) { 587 + if ((osd->vpbe_type == VPBE_VERSION_1) && 588 + is_osd_win(layer) && is_rgb_pixfmt(lconfig->pixfmt)) { 835 589 enum osd_pix_format pixfmt; 836 590 if (layer == WIN_OSD0) 837 591 pixfmt = osd->win[WIN_OSD1].lconfig.pixfmt; ··· 850 602 } 851 603 852 604 /* DM6446: only one video window at a time can use RGB888 */ 853 - if (is_vid_win(layer) && lconfig->pixfmt == PIXFMT_RGB888) { 605 + if ((osd->vpbe_type == VPBE_VERSION_1) && is_vid_win(layer) && 606 + lconfig->pixfmt == PIXFMT_RGB888) { 854 607 enum osd_pix_format pixfmt; 855 608 856 609 if (layer == WIN_VID0) ··· 901 652 * The caller must ensure that neither video window is currently 902 653 * configured for RGB888 pixel format. 903 654 */ 904 - osd_clear(sd, OSD_MISCCTL_RGBEN, OSD_MISCCTL); 655 + if (sd->vpbe_type == VPBE_VERSION_1) 656 + osd_clear(sd, OSD_MISCCTL_RGBEN, OSD_MISCCTL); 905 657 } 906 658 907 659 static void _osd_enable_vid_rgb888(struct osd_state *sd, ··· 915 665 * currently configured for RGB888 pixel format, as this routine will 916 666 * disable RGB888 pixel format for the other window. 917 667 */ 918 - if (layer == WIN_VID0) { 919 - osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN, 920 - OSD_MISCCTL_RGBEN, OSD_MISCCTL); 921 - } else if (layer == WIN_VID1) { 922 - osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN, 923 - OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN, 924 - OSD_MISCCTL); 668 + if (sd->vpbe_type == VPBE_VERSION_1) { 669 + if (layer == WIN_VID0) 670 + osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN, 671 + OSD_MISCCTL_RGBEN, OSD_MISCCTL); 672 + else if (layer == WIN_VID1) 673 + osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN, 674 + OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN, 675 + OSD_MISCCTL); 925 676 } 926 677 } 927 678 ··· 948 697 949 698 switch (layer) { 950 699 case WIN_OSD0: 951 - winmd_mask |= OSD_OSDWIN0MD_RGB0E; 952 - if (lconfig->pixfmt == PIXFMT_RGB565) 953 - winmd |= OSD_OSDWIN0MD_RGB0E; 700 + if (sd->vpbe_type == VPBE_VERSION_1) { 701 + winmd_mask |= OSD_OSDWIN0MD_RGB0E; 702 + if (lconfig->pixfmt == PIXFMT_RGB565) 703 + winmd |= OSD_OSDWIN0MD_RGB0E; 704 + } else if ((sd->vpbe_type == VPBE_VERSION_3) || 705 + (sd->vpbe_type == VPBE_VERSION_2)) { 706 + winmd_mask |= OSD_OSDWIN0MD_BMP0MD; 707 + switch (lconfig->pixfmt) { 708 + case PIXFMT_RGB565: 709 + winmd |= (1 << 710 + OSD_OSDWIN0MD_BMP0MD_SHIFT); 711 + break; 712 + case PIXFMT_RGB888: 713 + winmd |= (2 << OSD_OSDWIN0MD_BMP0MD_SHIFT); 714 + _osd_enable_rgb888_pixblend(sd, OSDWIN_OSD0); 715 + break; 716 + case PIXFMT_YCbCrI: 717 + case PIXFMT_YCrCbI: 718 + winmd |= (3 << OSD_OSDWIN0MD_BMP0MD_SHIFT); 719 + break; 720 + default: 721 + break; 722 + } 723 + } 954 724 955 725 winmd_mask |= OSD_OSDWIN0MD_BMW0 | OSD_OSDWIN0MD_OFF0; 956 726 ··· 1021 749 * For YUV420P format the register contents are 1022 750 * duplicated in both VID registers 1023 751 */ 752 + if ((sd->vpbe_type == VPBE_VERSION_2) && 753 + (lconfig->pixfmt == PIXFMT_NV12)) { 754 + /* other window also */ 755 + if (lconfig->interlaced) { 756 + winmd_mask |= OSD_VIDWINMD_VFF1; 757 + winmd |= OSD_VIDWINMD_VFF1; 758 + osd_modify(sd, winmd_mask, winmd, 759 + OSD_VIDWINMD); 760 + } 761 + 762 + osd_modify(sd, OSD_MISCCTL_S420D, 763 + OSD_MISCCTL_S420D, OSD_MISCCTL); 764 + osd_write(sd, lconfig->line_length >> 5, 765 + OSD_VIDWIN1OFST); 766 + osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP); 767 + osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL); 768 + /* 769 + * if NV21 pixfmt and line length not 32B 770 + * aligned (e.g. NTSC), Need to set window 771 + * X pixel size to be 32B aligned as well 772 + */ 773 + if (lconfig->xsize % 32) { 774 + osd_write(sd, 775 + ((lconfig->xsize + 31) & ~31), 776 + OSD_VIDWIN1XL); 777 + osd_write(sd, 778 + ((lconfig->xsize + 31) & ~31), 779 + OSD_VIDWIN0XL); 780 + } 781 + } else if ((sd->vpbe_type == VPBE_VERSION_2) && 782 + (lconfig->pixfmt != PIXFMT_NV12)) { 783 + osd_modify(sd, OSD_MISCCTL_S420D, ~OSD_MISCCTL_S420D, 784 + OSD_MISCCTL); 785 + } 786 + 1024 787 if (lconfig->interlaced) { 1025 788 osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN0YP); 1026 789 osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN0YL); 790 + if ((sd->vpbe_type == VPBE_VERSION_2) && 791 + lconfig->pixfmt == PIXFMT_NV12) { 792 + osd_write(sd, lconfig->ypos >> 1, 793 + OSD_VIDWIN1YP); 794 + osd_write(sd, lconfig->ysize >> 1, 795 + OSD_VIDWIN1YL); 796 + } 1027 797 } else { 1028 798 osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP); 1029 799 osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL); 800 + if ((sd->vpbe_type == VPBE_VERSION_2) && 801 + lconfig->pixfmt == PIXFMT_NV12) { 802 + osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP); 803 + osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL); 804 + } 1030 805 } 1031 806 break; 1032 807 case WIN_OSD1: ··· 1083 764 * attribute mode to a normal mode. 1084 765 */ 1085 766 if (lconfig->pixfmt == PIXFMT_OSD_ATTR) { 1086 - winmd_mask |= 1087 - OSD_OSDWIN1MD_ATN1E | OSD_OSDWIN1MD_RGB1E | 1088 - OSD_OSDWIN1MD_CLUTS1 | 1089 - OSD_OSDWIN1MD_BLND1 | OSD_OSDWIN1MD_TE1; 767 + if (sd->vpbe_type == VPBE_VERSION_1) { 768 + winmd_mask |= OSD_OSDWIN1MD_ATN1E | 769 + OSD_OSDWIN1MD_RGB1E | OSD_OSDWIN1MD_CLUTS1 | 770 + OSD_OSDWIN1MD_BLND1 | OSD_OSDWIN1MD_TE1; 771 + } else { 772 + winmd_mask |= OSD_OSDWIN1MD_BMP1MD | 773 + OSD_OSDWIN1MD_CLUTS1 | OSD_OSDWIN1MD_BLND1 | 774 + OSD_OSDWIN1MD_TE1; 775 + } 1090 776 } else { 1091 - winmd_mask |= OSD_OSDWIN1MD_RGB1E; 1092 - if (lconfig->pixfmt == PIXFMT_RGB565) 1093 - winmd |= OSD_OSDWIN1MD_RGB1E; 777 + if (sd->vpbe_type == VPBE_VERSION_1) { 778 + winmd_mask |= OSD_OSDWIN1MD_RGB1E; 779 + if (lconfig->pixfmt == PIXFMT_RGB565) 780 + winmd |= OSD_OSDWIN1MD_RGB1E; 781 + } else if ((sd->vpbe_type == VPBE_VERSION_3) 782 + || (sd->vpbe_type == VPBE_VERSION_2)) { 783 + winmd_mask |= OSD_OSDWIN1MD_BMP1MD; 784 + switch (lconfig->pixfmt) { 785 + case PIXFMT_RGB565: 786 + winmd |= 787 + (1 << OSD_OSDWIN1MD_BMP1MD_SHIFT); 788 + break; 789 + case PIXFMT_RGB888: 790 + winmd |= 791 + (2 << OSD_OSDWIN1MD_BMP1MD_SHIFT); 792 + _osd_enable_rgb888_pixblend(sd, 793 + OSDWIN_OSD1); 794 + break; 795 + case PIXFMT_YCbCrI: 796 + case PIXFMT_YCrCbI: 797 + winmd |= 798 + (3 << OSD_OSDWIN1MD_BMP1MD_SHIFT); 799 + break; 800 + default: 801 + break; 802 + } 803 + } 1094 804 1095 805 winmd_mask |= OSD_OSDWIN1MD_BMW1; 1096 806 switch (lconfig->pixfmt) { ··· 1170 822 * For YUV420P format the register contents are 1171 823 * duplicated in both VID registers 1172 824 */ 1173 - osd_modify(sd, OSD_MISCCTL_S420D, ~OSD_MISCCTL_S420D, 1174 - OSD_MISCCTL); 825 + if (sd->vpbe_type == VPBE_VERSION_2) { 826 + if (lconfig->pixfmt == PIXFMT_NV12) { 827 + /* other window also */ 828 + if (lconfig->interlaced) { 829 + winmd_mask |= OSD_VIDWINMD_VFF0; 830 + winmd |= OSD_VIDWINMD_VFF0; 831 + osd_modify(sd, winmd_mask, winmd, 832 + OSD_VIDWINMD); 833 + } 834 + osd_modify(sd, OSD_MISCCTL_S420D, 835 + OSD_MISCCTL_S420D, OSD_MISCCTL); 836 + osd_write(sd, lconfig->line_length >> 5, 837 + OSD_VIDWIN0OFST); 838 + osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP); 839 + osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL); 840 + } else { 841 + osd_modify(sd, OSD_MISCCTL_S420D, 842 + ~OSD_MISCCTL_S420D, OSD_MISCCTL); 843 + } 844 + } 1175 845 1176 846 if (lconfig->interlaced) { 1177 847 osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN1YP); 1178 848 osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN1YL); 849 + if ((sd->vpbe_type == VPBE_VERSION_2) && 850 + lconfig->pixfmt == PIXFMT_NV12) { 851 + osd_write(sd, lconfig->ypos >> 1, 852 + OSD_VIDWIN0YP); 853 + osd_write(sd, lconfig->ysize >> 1, 854 + OSD_VIDWIN0YL); 855 + } 1179 856 } else { 1180 857 osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP); 1181 858 osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL); 859 + if ((sd->vpbe_type == VPBE_VERSION_2) && 860 + lconfig->pixfmt == PIXFMT_NV12) { 861 + osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP); 862 + osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL); 863 + } 1182 864 } 1183 865 break; 1184 866 } ··· 1467 1089 osd_write(sd, 0, OSD_OSDWIN1MD); 1468 1090 osd_write(sd, 0, OSD_RECTCUR); 1469 1091 osd_write(sd, 0, OSD_MISCCTL); 1092 + if (sd->vpbe_type == VPBE_VERSION_3) { 1093 + osd_write(sd, 0, OSD_VBNDRY); 1094 + osd_write(sd, 0, OSD_EXTMODE); 1095 + osd_write(sd, OSD_MISCCTL_DMANG, OSD_MISCCTL); 1096 + } 1470 1097 } 1471 1098 1472 1099 static void osd_set_left_margin(struct osd_state *sd, u32 val) ··· 1492 1109 1493 1110 /* set default Cb/Cr order */ 1494 1111 osd->yc_pixfmt = PIXFMT_YCbCrI; 1112 + 1113 + if (osd->vpbe_type == VPBE_VERSION_3) { 1114 + /* 1115 + * ROM CLUT1 on the DM355 is similar (identical?) to ROM CLUT0 1116 + * on the DM6446, so make ROM_CLUT1 the default on the DM355. 1117 + */ 1118 + osd->rom_clut = ROM_CLUT1; 1119 + } 1495 1120 1496 1121 _osd_set_field_inversion(osd, osd->field_inversion); 1497 1122 _osd_set_rom_clut(osd, osd->rom_clut);