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kernel os linux

drm/amd/amdgpu: coding style refine in sdma_v4_0.c

Replace 8 spaces with tabs.
correct {} braces, etc.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher
4bdcc4ea 79690b84

+75 -76
+75 -76
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
··· 48 48 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 49 49 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 50 50 51 - static const u32 golden_settings_sdma_4[] = 52 - { 51 + static const u32 golden_settings_sdma_4[] = { 53 52 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07, 54 53 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100, 55 54 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100, ··· 75 76 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0 76 77 }; 77 78 78 - static const u32 golden_settings_sdma_vg10[] = 79 - { 79 + static const u32 golden_settings_sdma_vg10[] = { 80 80 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002, 81 81 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002, 82 82 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002, ··· 85 87 static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset) 86 88 { 87 89 u32 base = 0; 90 + 88 91 switch (instance) { 89 - case 0: 90 - base = SDMA0_BASE.instance[0].segment[0]; 91 - break; 92 - case 1: 93 - base = SDMA1_BASE.instance[0].segment[0]; 94 - break; 95 - default: 96 - BUG(); 97 - break; 92 + case 0: 93 + base = SDMA0_BASE.instance[0].segment[0]; 94 + break; 95 + case 1: 96 + base = SDMA1_BASE.instance[0].segment[0]; 97 + break; 98 + default: 99 + BUG(); 100 + break; 98 101 } 99 102 100 103 return base + internal_offset; ··· 158 159 case CHIP_VEGA10: 159 160 chip_name = "vega10"; 160 161 break; 161 - default: BUG(); 162 + default: 163 + BUG(); 162 164 } 163 165 164 166 for (i = 0; i < adev->sdma.num_instances; i++) { ··· 179 179 if (adev->sdma.instance[i].feature_version >= 20) 180 180 adev->sdma.instance[i].burst_nop = true; 181 181 DRM_DEBUG("psp_load == '%s'\n", 182 - adev->firmware.load_type == AMDGPU_FW_LOAD_PSP? "true": "false"); 182 + adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 183 183 184 184 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 185 185 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; ··· 192 192 } 193 193 out: 194 194 if (err) { 195 - printk(KERN_ERR 196 - "sdma_v4_0: Failed to load firmware \"%s\"\n", 197 - fw_name); 195 + DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 198 196 for (i = 0; i < adev->sdma.num_instances; i++) { 199 197 release_firmware(adev->sdma.instance[i].fw); 200 198 adev->sdma.instance[i].fw = NULL; ··· 210 212 */ 211 213 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 212 214 { 213 - u64* rptr; 215 + u64 *rptr; 214 216 215 217 /* XXX check if swapping is necessary on BE */ 216 - rptr =((u64*)&ring->adev->wb.wb[ring->rptr_offs]); 218 + rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 217 219 218 220 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 219 221 return ((*rptr) >> 2); ··· 229 231 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 230 232 { 231 233 struct amdgpu_device *adev = ring->adev; 232 - u64* wptr = NULL; 233 - uint64_t local_wptr=0; 234 + u64 *wptr = NULL; 235 + uint64_t local_wptr = 0; 234 236 235 237 if (ring->use_doorbell) { 236 238 /* XXX check if swapping is necessary on BE */ 237 - wptr = ((u64*)&adev->wb.wb[ring->wptr_offs]); 239 + wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); 238 240 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); 239 241 *wptr = (*wptr) >> 2; 240 242 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); 241 243 } else { 242 244 u32 lowbit, highbit; 243 245 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 244 - wptr=&local_wptr; 246 + 247 + wptr = &local_wptr; 245 248 lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2; 246 249 highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 247 250 ··· 284 285 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 285 286 } else { 286 287 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 288 + 287 289 DRM_DEBUG("Not using doorbell -- " 288 290 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 289 - "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x \n", 291 + "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 290 292 me, 291 293 lower_32_bits(ring->wptr << 2), 292 294 me, ··· 319 319 * Schedule an IB in the DMA ring (VEGA10). 320 320 */ 321 321 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 322 - struct amdgpu_ib *ib, 323 - unsigned vm_id, bool ctx_switch) 322 + struct amdgpu_ib *ib, 323 + unsigned vm_id, bool ctx_switch) 324 324 { 325 - u32 vmid = vm_id & 0xf; 325 + u32 vmid = vm_id & 0xf; 326 326 327 - /* IB packet must end on a 8 DW boundary */ 328 - sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 327 + /* IB packet must end on a 8 DW boundary */ 328 + sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 329 329 330 - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 331 - SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 332 - /* base must be 32 byte aligned */ 333 - amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 334 - amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 335 - amdgpu_ring_write(ring, ib->length_dw); 336 - amdgpu_ring_write(ring, 0); 337 - amdgpu_ring_write(ring, 0); 330 + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 331 + SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 332 + /* base must be 32 byte aligned */ 333 + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 334 + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 335 + amdgpu_ring_write(ring, ib->length_dw); 336 + amdgpu_ring_write(ring, 0); 337 + amdgpu_ring_write(ring, 0); 338 338 339 339 } 340 340 ··· 523 523 u32 doorbell; 524 524 u32 doorbell_offset; 525 525 u32 temp; 526 - int i,r; 526 + int i, r; 527 527 528 528 for (i = 0; i < adev->sdma.num_instances; i++) { 529 529 ring = &adev->sdma.instance[i].ring; ··· 572 572 doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL)); 573 573 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET)); 574 574 575 - if (ring->use_doorbell){ 575 + if (ring->use_doorbell) { 576 576 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 577 577 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 578 578 OFFSET, ring->doorbell_index); ··· 694 694 695 695 696 696 for (j = 0; j < fw_size; j++) 697 - { 698 697 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 699 - } 700 698 701 699 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 702 700 } ··· 793 795 794 796 for (i = 0; i < adev->usec_timeout; i++) { 795 797 tmp = le32_to_cpu(adev->wb.wb[index]); 796 - if (tmp == 0xDEADBEEF) { 798 + if (tmp == 0xDEADBEEF) 797 799 break; 798 - } 799 800 DRM_UDELAY(1); 800 801 } 801 802 ··· 859 862 if (r) 860 863 goto err1; 861 864 862 - r = dma_fence_wait_timeout(f, false, timeout); 863 - if (r == 0) { 864 - DRM_ERROR("amdgpu: IB test timed out\n"); 865 - r = -ETIMEDOUT; 866 - goto err1; 867 - } else if (r < 0) { 868 - DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 869 - goto err1; 870 - } 871 - tmp = le32_to_cpu(adev->wb.wb[index]); 872 - if (tmp == 0xDEADBEEF) { 873 - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 874 - r = 0; 875 - } else { 876 - DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 877 - r = -EINVAL; 878 - } 865 + r = dma_fence_wait_timeout(f, false, timeout); 866 + if (r == 0) { 867 + DRM_ERROR("amdgpu: IB test timed out\n"); 868 + r = -ETIMEDOUT; 869 + goto err1; 870 + } else if (r < 0) { 871 + DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 872 + goto err1; 873 + } 874 + tmp = le32_to_cpu(adev->wb.wb[index]); 875 + if (tmp == 0xDEADBEEF) { 876 + DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 877 + r = 0; 878 + } else { 879 + DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 880 + r = -EINVAL; 881 + } 879 882 err1: 880 - amdgpu_ib_free(adev, &ib, NULL); 881 - dma_fence_put(f); 883 + amdgpu_ib_free(adev, &ib, NULL); 884 + dma_fence_put(f); 882 885 err0: 883 - amdgpu_wb_free(adev, index); 884 - return r; 886 + amdgpu_wb_free(adev, index); 887 + return r; 885 888 } 886 889 887 890 ··· 1188 1191 { 1189 1192 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1190 1193 u32 i; 1194 + 1191 1195 for (i = 0; i < adev->sdma.num_instances; i++) { 1192 1196 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG)); 1197 + 1193 1198 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1194 - return false; 1199 + return false; 1195 1200 } 1196 1201 1197 1202 return true; ··· 1202 1203 static int sdma_v4_0_wait_for_idle(void *handle) 1203 1204 { 1204 1205 unsigned i; 1205 - u32 sdma0,sdma1; 1206 + u32 sdma0, sdma1; 1206 1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1208 + 1207 1209 for (i = 0; i < adev->usec_timeout; i++) { 1208 1210 sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG)); 1209 1211 sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG)); ··· 1232 1232 1233 1233 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 1234 1234 sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) : 1235 - sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL); 1235 + sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL); 1236 1236 1237 1237 sdma_cntl = RREG32(reg_offset); 1238 1238 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, ··· 1324 1324 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1325 1325 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1326 1326 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1327 - if(def != data) 1327 + if (def != data) 1328 1328 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1329 1329 } 1330 1330 } else { ··· 1374 1374 1375 1375 /* 1-not override: enable sdma1 mem light sleep */ 1376 1376 if (adev->asic_type == CHIP_VEGA10) { 1377 - def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1378 - data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1379 - if (def != data) 1380 - WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1377 + def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1378 + data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1379 + if (def != data) 1380 + WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1381 1381 } 1382 1382 } else { 1383 1383 /* 0-override:disable sdma0 mem light sleep */ 1384 1384 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1385 1385 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1386 1386 if (def != data) 1387 - WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1387 + WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1388 1388 1389 1389 /* 0-override:disable sdma1 mem light sleep */ 1390 1390 if (adev->asic_type == CHIP_VEGA10) { ··· 1599 1599 } 1600 1600 } 1601 1601 1602 - const struct amdgpu_ip_block_version sdma_v4_0_ip_block = 1603 - { 1602 + const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 1604 1603 .type = AMD_IP_BLOCK_TYPE_SDMA, 1605 1604 .major = 4, 1606 1605 .minor = 0,