tjh.dev / kernel
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ASoC: max98090: revert invalid fix for handling SHDN

Reverts commit 62d5ae4cafb7 ("ASoC: max98090: save and restore
SHDN when changing sensitive registers").

A critical side-effect was observed: when keep playing something,
the recorded sound has chance to break (clipping).

Signed-off-by: Tzung-Bi Shih <tzungbi@google.com>
Link: https://lore.kernel.org/r/20200214105744.82258-2-tzungbi@google.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Tzung-Bi Shih and committed by
Mark Brown 4b8a1ca4 b6570fdb

+121 -310
+120 -308
sound/soc/codecs/max98090.c
··· 5 5 * Copyright 2011-2012 Maxim Integrated Products 6 6 */ 7 7 8 - #include <linux/acpi.h> 9 - #include <linux/clk.h> 10 8 #include <linux/delay.h> 11 9 #include <linux/i2c.h> 12 10 #include <linux/module.h> 13 - #include <linux/mutex.h> 14 11 #include <linux/of.h> 15 12 #include <linux/pm.h> 16 13 #include <linux/pm_runtime.h> 17 14 #include <linux/regmap.h> 18 15 #include <linux/slab.h> 16 + #include <linux/acpi.h> 17 + #include <linux/clk.h> 19 18 #include <sound/jack.h> 20 - #include <sound/max98090.h> 21 19 #include <sound/pcm.h> 22 20 #include <sound/pcm_params.h> 23 21 #include <sound/soc.h> 24 22 #include <sound/tlv.h> 23 + #include <sound/max98090.h> 25 24 #include "max98090.h" 26 - 27 - static void max98090_shdn_save_locked(struct max98090_priv *max98090) 28 - { 29 - int shdn = 0; 30 - 31 - /* saved_shdn, saved_count, SHDN are protected by card->dapm_mutex */ 32 - regmap_read(max98090->regmap, M98090_REG_DEVICE_SHUTDOWN, &shdn); 33 - max98090->saved_shdn |= shdn; 34 - ++max98090->saved_count; 35 - 36 - if (shdn) 37 - regmap_write(max98090->regmap, M98090_REG_DEVICE_SHUTDOWN, 0x0); 38 - } 39 - 40 - static void max98090_shdn_restore_locked(struct max98090_priv *max98090) 41 - { 42 - /* saved_shdn, saved_count, SHDN are protected by card->dapm_mutex */ 43 - if (--max98090->saved_count == 0) { 44 - if (max98090->saved_shdn) { 45 - regmap_write(max98090->regmap, 46 - M98090_REG_DEVICE_SHUTDOWN, 47 - M98090_SHDNN_MASK); 48 - max98090->saved_shdn = 0; 49 - } 50 - } 51 - } 52 - 53 - static void max98090_shdn_save(struct max98090_priv *max98090) 54 - { 55 - mutex_lock_nested(&max98090->component->card->dapm_mutex, 56 - SND_SOC_DAPM_CLASS_RUNTIME); 57 - max98090_shdn_save_locked(max98090); 58 - } 59 - 60 - static void max98090_shdn_restore(struct max98090_priv *max98090) 61 - { 62 - max98090_shdn_restore_locked(max98090); 63 - mutex_unlock(&max98090->component->card->dapm_mutex); 64 - } 65 - 66 - static int max98090_put_volsw(struct snd_kcontrol *kcontrol, 67 - struct snd_ctl_elem_value *ucontrol) 68 - { 69 - struct snd_soc_component *component = 70 - snd_soc_kcontrol_component(kcontrol); 71 - struct max98090_priv *max98090 = 72 - snd_soc_component_get_drvdata(component); 73 - int ret; 74 - 75 - max98090_shdn_save(max98090); 76 - ret = snd_soc_put_volsw(kcontrol, ucontrol); 77 - max98090_shdn_restore(max98090); 78 - 79 - return ret; 80 - } 81 - 82 - static int max98090_dapm_put_enum_double(struct snd_kcontrol *kcontrol, 83 - struct snd_ctl_elem_value *ucontrol) 84 - { 85 - struct snd_soc_component *component = 86 - snd_soc_dapm_kcontrol_component(kcontrol); 87 - struct max98090_priv *max98090 = 88 - snd_soc_component_get_drvdata(component); 89 - int ret; 90 - 91 - max98090_shdn_save(max98090); 92 - ret = snd_soc_dapm_put_enum_double_locked(kcontrol, ucontrol); 93 - max98090_shdn_restore(max98090); 94 - 95 - return ret; 96 - } 97 - 98 - static int max98090_put_enum_double(struct snd_kcontrol *kcontrol, 99 - struct snd_ctl_elem_value *ucontrol) 100 - { 101 - struct snd_soc_component *component = 102 - snd_soc_kcontrol_component(kcontrol); 103 - struct max98090_priv *max98090 = 104 - snd_soc_component_get_drvdata(component); 105 - int ret; 106 - 107 - max98090_shdn_save(max98090); 108 - ret = snd_soc_put_enum_double(kcontrol, ucontrol); 109 - max98090_shdn_restore(max98090); 110 - 111 - return ret; 112 - } 113 - 114 - static int max98090_bytes_put(struct snd_kcontrol *kcontrol, 115 - struct snd_ctl_elem_value *ucontrol) 116 - { 117 - struct snd_soc_component *component = 118 - snd_soc_kcontrol_component(kcontrol); 119 - struct max98090_priv *max98090 = 120 - snd_soc_component_get_drvdata(component); 121 - int ret; 122 - 123 - max98090_shdn_save(max98090); 124 - ret = snd_soc_bytes_put(kcontrol, ucontrol); 125 - max98090_shdn_restore(max98090); 126 - 127 - return ret; 128 - } 129 - 130 - static int max98090_dapm_event(struct snd_soc_dapm_widget *w, 131 - struct snd_kcontrol *kcontrol, int event) 132 - { 133 - struct snd_soc_component *component = 134 - snd_soc_dapm_to_component(w->dapm); 135 - struct max98090_priv *max98090 = 136 - snd_soc_component_get_drvdata(component); 137 - 138 - switch (event) { 139 - case SND_SOC_DAPM_PRE_PMU: 140 - case SND_SOC_DAPM_PRE_PMD: 141 - max98090_shdn_save_locked(max98090); 142 - break; 143 - case SND_SOC_DAPM_POST_PMU: 144 - case SND_SOC_DAPM_POST_PMD: 145 - max98090_shdn_restore_locked(max98090); 146 - break; 147 - } 148 - 149 - return 0; 150 - } 151 25 152 26 /* Allows for sparsely populated register maps */ 153 27 static const struct reg_default max98090_reg[] = { ··· 506 632 max98090_pwr_perf_text); 507 633 508 634 static const struct snd_kcontrol_new max98090_snd_controls[] = { 509 - SOC_ENUM_EXT("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum, 510 - snd_soc_get_enum_double, max98090_put_enum_double), 635 + SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), 511 636 512 - SOC_SINGLE_EXT("DMIC MIC Comp Filter Config", 513 - M98090_REG_DIGITAL_MIC_CONFIG, 514 - M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0, 515 - snd_soc_get_volsw, max98090_put_volsw), 637 + SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, 638 + M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), 516 639 517 640 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 518 641 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, ··· 564 693 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, 565 694 max98090_av_tlv), 566 695 567 - SOC_ENUM_EXT("ADC Oversampling Rate", max98090_osr128_enum, 568 - snd_soc_get_enum_double, max98090_put_enum_double), 569 - SOC_SINGLE_EXT("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, 570 - M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0, 571 - snd_soc_get_volsw, max98090_put_volsw), 572 - SOC_ENUM_EXT("ADC High Performance Mode", max98090_adchp_enum, 573 - snd_soc_get_enum_double, max98090_put_enum_double), 696 + SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), 697 + SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, 698 + M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), 699 + SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), 574 700 575 - SOC_SINGLE_EXT("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, 576 - M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0, 577 - snd_soc_get_volsw, max98090_put_volsw), 578 - SOC_SINGLE_EXT("SDIN Mode", M98090_REG_IO_CONFIGURATION, 579 - M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0, 580 - snd_soc_get_volsw, max98090_put_volsw), 581 - SOC_SINGLE_EXT("SDOUT Mode", M98090_REG_IO_CONFIGURATION, 582 - M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0, 583 - snd_soc_get_volsw, max98090_put_volsw), 584 - SOC_SINGLE_EXT("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, 585 - M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1, 586 - snd_soc_get_volsw, max98090_put_volsw), 587 - SOC_ENUM_EXT("Filter Mode", max98090_mode_enum, 588 - snd_soc_get_enum_double, max98090_put_enum_double), 589 - SOC_SINGLE_EXT("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, 590 - M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0, 591 - snd_soc_get_volsw, max98090_put_volsw), 592 - SOC_SINGLE_EXT("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, 593 - M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0, 594 - snd_soc_get_volsw, max98090_put_volsw), 701 + SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, 702 + M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), 703 + SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, 704 + M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), 705 + SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, 706 + M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), 707 + SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, 708 + M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), 709 + SOC_ENUM("Filter Mode", max98090_mode_enum), 710 + SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, 711 + M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), 712 + SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, 713 + M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), 595 714 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, 596 715 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), 597 716 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", ··· 594 733 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 595 734 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, 596 735 max98090_dv_tlv), 597 - SND_SOC_BYTES_E("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105, 598 - snd_soc_bytes_get, max98090_bytes_put), 599 - SOC_SINGLE_EXT("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 600 - M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0, 601 - snd_soc_get_volsw, max98090_put_volsw), 602 - SOC_SINGLE_EXT("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 603 - M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0, 604 - snd_soc_get_volsw, max98090_put_volsw), 605 - SOC_SINGLE_EXT("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 606 - M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0, 607 - snd_soc_get_volsw, max98090_put_volsw), 736 + SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), 737 + SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 738 + M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), 739 + SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 740 + M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), 741 + SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 742 + M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), 608 743 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 609 744 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, 610 745 1), ··· 608 751 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, 609 752 max98090_dv_tlv), 610 753 611 - SOC_SINGLE_EXT("ALC Enable", M98090_REG_DRC_TIMING, 612 - M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0, 613 - snd_soc_get_volsw, max98090_put_volsw), 614 - SOC_ENUM_EXT("ALC Attack Time", max98090_drcatk_enum, 615 - snd_soc_get_enum_double, max98090_put_enum_double), 616 - SOC_ENUM_EXT("ALC Release Time", max98090_drcrls_enum, 617 - snd_soc_get_enum_double, max98090_put_enum_double), 754 + SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, 755 + M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), 756 + SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), 757 + SOC_ENUM("ALC Release Time", max98090_drcrls_enum), 618 758 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, 619 759 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, 620 760 max98090_alcmakeup_tlv), 621 - SOC_ENUM_EXT("ALC Compression Ratio", max98090_alccmp_enum, 622 - snd_soc_get_enum_double, max98090_put_enum_double), 623 - SOC_ENUM_EXT("ALC Expansion Ratio", max98090_drcexp_enum, 624 - snd_soc_get_enum_double, max98090_put_enum_double), 625 - SOC_SINGLE_EXT_TLV("ALC Compression Threshold Volume", 761 + SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), 762 + SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), 763 + SOC_SINGLE_TLV("ALC Compression Threshold Volume", 626 764 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, 627 - M98090_DRCTHC_NUM - 1, 1, 628 - snd_soc_get_volsw, max98090_put_volsw, max98090_alccomp_tlv), 629 - SOC_SINGLE_EXT_TLV("ALC Expansion Threshold Volume", 765 + M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), 766 + SOC_SINGLE_TLV("ALC Expansion Threshold Volume", 630 767 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, 631 - M98090_DRCTHE_NUM - 1, 1, 632 - snd_soc_get_volsw, max98090_put_volsw, max98090_drcexp_tlv), 768 + M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), 633 769 634 - SOC_ENUM_EXT("DAC HP Playback Performance Mode", 635 - max98090_dac_perfmode_enum, 636 - snd_soc_get_enum_double, max98090_put_enum_double), 637 - SOC_ENUM_EXT("DAC High Performance Mode", max98090_dachp_enum, 638 - snd_soc_get_enum_double, max98090_put_enum_double), 770 + SOC_ENUM("DAC HP Playback Performance Mode", 771 + max98090_dac_perfmode_enum), 772 + SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), 639 773 640 774 SOC_SINGLE_TLV("Headphone Left Mixer Volume", 641 775 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, ··· 684 836 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, 685 837 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), 686 838 687 - SND_SOC_BYTES_E("Biquad Coefficients", 688 - M98090_REG_RECORD_BIQUAD_BASE, 15, 689 - snd_soc_bytes_get, max98090_bytes_put), 690 - SOC_SINGLE_EXT("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 691 - M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0, 692 - snd_soc_get_volsw, max98090_put_volsw), 839 + SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), 840 + SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 841 + M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), 693 842 }; 694 843 695 844 static const struct snd_kcontrol_new max98091_snd_controls[] = { ··· 695 850 M98090_DMIC34_ZEROPAD_SHIFT, 696 851 M98090_DMIC34_ZEROPAD_NUM - 1, 0), 697 852 698 - SOC_ENUM_EXT("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum, 699 - snd_soc_get_enum_double, max98090_put_enum_double), 700 - SOC_SINGLE_EXT("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, 853 + SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), 854 + SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, 701 855 M98090_FLT_DMIC34HPF_SHIFT, 702 - M98090_FLT_DMIC34HPF_NUM - 1, 0, 703 - snd_soc_get_volsw, max98090_put_volsw), 856 + M98090_FLT_DMIC34HPF_NUM - 1, 0), 704 857 705 858 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, 706 859 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, ··· 716 873 717 874 SND_SOC_BYTES("DMIC34 Biquad Coefficients", 718 875 M98090_REG_DMIC34_BIQUAD_BASE, 15), 719 - SOC_SINGLE_EXT("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 720 - M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0, 721 - snd_soc_get_volsw, max98090_put_volsw), 876 + SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 877 + M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), 722 878 723 879 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", 724 880 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, ··· 769 927 val << M98090_MIC_PA2EN_SHIFT); 770 928 771 929 return 0; 930 + } 931 + 932 + static int max98090_shdn_event(struct snd_soc_dapm_widget *w, 933 + struct snd_kcontrol *kcontrol, int event) 934 + { 935 + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 936 + struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 937 + 938 + if (event & SND_SOC_DAPM_POST_PMU) 939 + max98090->shdn_pending = true; 940 + 941 + return 0; 942 + 772 943 } 773 944 774 945 static const char *mic1_mux_text[] = { "IN12", "IN56" }; ··· 884 1029 lten_mux_text); 885 1030 886 1031 static const struct snd_kcontrol_new max98090_ltenl_mux = 887 - SOC_DAPM_ENUM_EXT("LTENL Mux", ltenl_mux_enum, 888 - snd_soc_dapm_get_enum_double, 889 - max98090_dapm_put_enum_double); 1032 + SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); 890 1033 891 1034 static const struct snd_kcontrol_new max98090_ltenr_mux = 892 - SOC_DAPM_ENUM_EXT("LTENR Mux", ltenr_mux_enum, 893 - snd_soc_dapm_get_enum_double, 894 - max98090_dapm_put_enum_double); 1035 + SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); 895 1036 896 1037 static const char *lben_mux_text[] = { "Normal", "Loopback" }; 897 1038 ··· 902 1051 lben_mux_text); 903 1052 904 1053 static const struct snd_kcontrol_new max98090_lbenl_mux = 905 - SOC_DAPM_ENUM_EXT("LBENL Mux", lbenl_mux_enum, 906 - snd_soc_dapm_get_enum_double, 907 - max98090_dapm_put_enum_double); 1054 + SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); 908 1055 909 1056 static const struct snd_kcontrol_new max98090_lbenr_mux = 910 - SOC_DAPM_ENUM_EXT("LBENR Mux", lbenr_mux_enum, 911 - snd_soc_dapm_get_enum_double, 912 - max98090_dapm_put_enum_double); 1057 + SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); 913 1058 914 1059 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; 915 1060 ··· 1072 1225 SND_SOC_DAPM_INPUT("IN56"), 1073 1226 1074 1227 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, 1075 - M98090_MBEN_SHIFT, 0, max98090_dapm_event, 1076 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1228 + M98090_MBEN_SHIFT, 0, NULL, 0), 1077 1229 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, 1078 1230 M98090_SHDNN_SHIFT, 0, NULL, 0), 1079 1231 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, 1080 - M98090_SDIEN_SHIFT, 0, max98090_dapm_event, 1081 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1232 + M98090_SDIEN_SHIFT, 0, NULL, 0), 1082 1233 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, 1083 - M98090_SDOEN_SHIFT, 0, max98090_dapm_event, 1084 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1234 + M98090_SDOEN_SHIFT, 0, NULL, 0), 1085 1235 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1086 - M98090_DIGMICL_SHIFT, 0, max98090_dapm_event, 1087 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1236 + M98090_DIGMICL_SHIFT, 0, max98090_shdn_event, 1237 + SND_SOC_DAPM_POST_PMU), 1088 1238 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1089 - M98090_DIGMICR_SHIFT, 0, max98090_dapm_event, 1090 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1239 + M98090_DIGMICR_SHIFT, 0, max98090_shdn_event, 1240 + SND_SOC_DAPM_POST_PMU), 1091 1241 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, 1092 - M98090_AHPF_SHIFT, 0, max98090_dapm_event, 1093 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1242 + M98090_AHPF_SHIFT, 0, NULL, 0), 1094 1243 1095 1244 /* 1096 1245 * Note: Sysclk and misc power supplies are taken care of by SHDN ··· 1116 1273 &max98090_lineb_mixer_controls[0], 1117 1274 ARRAY_SIZE(max98090_lineb_mixer_controls)), 1118 1275 1119 - SND_SOC_DAPM_PGA_E("LINEA Input", M98090_REG_INPUT_ENABLE, 1120 - M98090_LINEAEN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1121 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1122 - SND_SOC_DAPM_PGA_E("LINEB Input", M98090_REG_INPUT_ENABLE, 1123 - M98090_LINEBEN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1124 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1276 + SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, 1277 + M98090_LINEAEN_SHIFT, 0, NULL, 0), 1278 + SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, 1279 + M98090_LINEBEN_SHIFT, 0, NULL, 0), 1125 1280 1126 1281 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1127 1282 &max98090_left_adc_mixer_controls[0], ··· 1130 1289 ARRAY_SIZE(max98090_right_adc_mixer_controls)), 1131 1290 1132 1291 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE, 1133 - M98090_ADLEN_SHIFT, 0, max98090_dapm_event, 1134 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1292 + M98090_ADLEN_SHIFT, 0, max98090_shdn_event, 1293 + SND_SOC_DAPM_POST_PMU), 1135 1294 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE, 1136 - M98090_ADREN_SHIFT, 0, max98090_dapm_event, 1137 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1295 + M98090_ADREN_SHIFT, 0, max98090_shdn_event, 1296 + SND_SOC_DAPM_POST_PMU), 1138 1297 1139 1298 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, 1140 1299 SND_SOC_NOPM, 0, 0), ··· 1162 1321 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 1163 1322 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), 1164 1323 1165 - SND_SOC_DAPM_DAC_E("DACL", NULL, M98090_REG_OUTPUT_ENABLE, 1166 - M98090_DALEN_SHIFT, 0, max98090_dapm_event, 1167 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1168 - SND_SOC_DAPM_DAC_E("DACR", NULL, M98090_REG_OUTPUT_ENABLE, 1169 - M98090_DAREN_SHIFT, 0, max98090_dapm_event, 1170 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1324 + SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, 1325 + M98090_DALEN_SHIFT, 0), 1326 + SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, 1327 + M98090_DAREN_SHIFT, 0), 1171 1328 1172 1329 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1173 1330 &max98090_left_hp_mixer_controls[0], ··· 1200 1361 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0, 1201 1362 &max98090_mixhprsel_mux), 1202 1363 1203 - SND_SOC_DAPM_PGA_E("HP Left Out", M98090_REG_OUTPUT_ENABLE, 1204 - M98090_HPLEN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1205 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1206 - SND_SOC_DAPM_PGA_E("HP Right Out", M98090_REG_OUTPUT_ENABLE, 1207 - M98090_HPREN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1208 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1364 + SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, 1365 + M98090_HPLEN_SHIFT, 0, NULL, 0), 1366 + SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, 1367 + M98090_HPREN_SHIFT, 0, NULL, 0), 1209 1368 1210 - SND_SOC_DAPM_PGA_E("SPK Left Out", M98090_REG_OUTPUT_ENABLE, 1211 - M98090_SPLEN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1212 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1213 - SND_SOC_DAPM_PGA_E("SPK Right Out", M98090_REG_OUTPUT_ENABLE, 1214 - M98090_SPREN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1215 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1369 + SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, 1370 + M98090_SPLEN_SHIFT, 0, NULL, 0), 1371 + SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, 1372 + M98090_SPREN_SHIFT, 0, NULL, 0), 1216 1373 1217 - SND_SOC_DAPM_PGA_E("RCV Left Out", M98090_REG_OUTPUT_ENABLE, 1218 - M98090_RCVLEN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1219 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1220 - SND_SOC_DAPM_PGA_E("RCV Right Out", M98090_REG_OUTPUT_ENABLE, 1221 - M98090_RCVREN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1222 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1374 + SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, 1375 + M98090_RCVLEN_SHIFT, 0, NULL, 0), 1376 + SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, 1377 + M98090_RCVREN_SHIFT, 0, NULL, 0), 1223 1378 1224 1379 SND_SOC_DAPM_OUTPUT("HPL"), 1225 1380 SND_SOC_DAPM_OUTPUT("HPR"), ··· 1228 1395 SND_SOC_DAPM_INPUT("DMIC4"), 1229 1396 1230 1397 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1231 - M98090_DIGMIC3_SHIFT, 0, max98090_dapm_event, 1232 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1398 + M98090_DIGMIC3_SHIFT, 0, NULL, 0), 1233 1399 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1234 - M98090_DIGMIC4_SHIFT, 0, max98090_dapm_event, 1235 - SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1400 + M98090_DIGMIC4_SHIFT, 0, NULL, 0), 1236 1401 }; 1237 1402 1238 1403 static const struct snd_soc_dapm_route max98090_dapm_routes[] = { ··· 1501 1670 return; 1502 1671 } 1503 1672 1504 - /* 1505 - * Master mode: no need to save and restore SHDN for the following 1506 - * sensitive registers. 1507 - */ 1508 - 1509 1673 /* Check for supported PCLK to LRCLK ratios */ 1510 1674 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { 1511 1675 if ((pclk_rates[i] == max98090->sysclk) && ··· 1587 1761 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1588 1762 case SND_SOC_DAIFMT_CBS_CFS: 1589 1763 /* Set to slave mode PLL - MAS mode off */ 1590 - max98090_shdn_save(max98090); 1591 1764 snd_soc_component_write(component, 1592 1765 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); 1593 1766 snd_soc_component_write(component, 1594 1767 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); 1595 1768 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1596 1769 M98090_USE_M1_MASK, 0); 1597 - max98090_shdn_restore(max98090); 1598 1770 max98090->master = false; 1599 1771 break; 1600 1772 case SND_SOC_DAIFMT_CBM_CFM: ··· 1618 1794 dev_err(component->dev, "DAI clock mode unsupported"); 1619 1795 return -EINVAL; 1620 1796 } 1621 - max98090_shdn_save(max98090); 1622 1797 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval); 1623 - max98090_shdn_restore(max98090); 1624 1798 1625 1799 regval = 0; 1626 1800 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ··· 1663 1841 if (max98090->tdm_slots > 1) 1664 1842 regval ^= M98090_BCI_MASK; 1665 1843 1666 - max98090_shdn_save(max98090); 1667 1844 snd_soc_component_write(component, 1668 1845 M98090_REG_INTERFACE_FORMAT, regval); 1669 - max98090_shdn_restore(max98090); 1670 1846 } 1671 1847 1672 1848 return 0; ··· 1676 1856 struct snd_soc_component *component = codec_dai->component; 1677 1857 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1678 1858 struct max98090_cdata *cdata; 1679 - 1680 1859 cdata = &max98090->dai[0]; 1681 1860 1682 1861 if (slots < 0 || slots > 4) ··· 1685 1866 max98090->tdm_width = slot_width; 1686 1867 1687 1868 if (max98090->tdm_slots > 1) { 1688 - max98090_shdn_save(max98090); 1689 1869 /* SLOTL SLOTR SLOTDLY */ 1690 1870 snd_soc_component_write(component, M98090_REG_TDM_FORMAT, 1691 1871 0 << M98090_TDM_SLOTL_SHIFT | ··· 1695 1877 snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL, 1696 1878 M98090_TDM_MASK, 1697 1879 M98090_TDM_MASK); 1698 - max98090_shdn_restore(max98090); 1699 1880 } 1700 1881 1701 1882 /* ··· 1894 2077 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq; 1895 2078 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i]; 1896 2079 1897 - max98090_shdn_save(max98090); 1898 2080 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, 1899 2081 M98090_MICCLK_MASK, 1900 2082 micclk_index << M98090_MICCLK_SHIFT); ··· 1902 2086 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK, 1903 2087 dmic_comp << M98090_DMIC_COMP_SHIFT | 1904 2088 dmic_freq << M98090_DMIC_FREQ_SHIFT); 1905 - max98090_shdn_restore(max98090); 1906 2089 1907 2090 return 0; 1908 2091 } ··· 1938 2123 1939 2124 switch (params_width(params)) { 1940 2125 case 16: 1941 - max98090_shdn_save(max98090); 1942 2126 snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT, 1943 2127 M98090_WS_MASK, 0); 1944 - max98090_shdn_restore(max98090); 1945 2128 break; 1946 2129 default: 1947 2130 return -EINVAL; ··· 1950 2137 1951 2138 cdata->rate = max98090->lrclk; 1952 2139 1953 - max98090_shdn_save(max98090); 1954 2140 /* Update filter mode */ 1955 2141 if (max98090->lrclk < 24000) 1956 2142 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, ··· 1965 2153 else 1966 2154 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 1967 2155 M98090_DHF_MASK, M98090_DHF_MASK); 1968 - max98090_shdn_restore(max98090); 1969 2156 1970 2157 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, 1971 2158 max98090->lrclk); ··· 1995 2184 * 0x02 (when master clk is 20MHz to 40MHz).. 1996 2185 * 0x03 (when master clk is 40MHz to 60MHz).. 1997 2186 */ 1998 - max98090_shdn_save(max98090); 1999 2187 if ((freq >= 10000000) && (freq <= 20000000)) { 2000 2188 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2001 2189 M98090_PSCLK_DIV1); ··· 2009 2199 max98090->pclk = freq >> 2; 2010 2200 } else { 2011 2201 dev_err(component->dev, "Invalid master clock frequency\n"); 2012 - max98090_shdn_restore(max98090); 2013 2202 return -EINVAL; 2014 2203 } 2015 - max98090_shdn_restore(max98090); 2016 2204 2017 2205 max98090->sysclk = freq; 2018 2206 ··· 2122 2314 */ 2123 2315 2124 2316 /* Toggle shutdown OFF then ON */ 2125 - mutex_lock(&component->card->dapm_mutex); 2126 2317 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2127 2318 M98090_SHDNN_MASK, 0); 2128 2319 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2129 2320 M98090_SHDNN_MASK, M98090_SHDNN_MASK); 2130 - mutex_unlock(&component->card->dapm_mutex); 2131 2321 2132 2322 for (i = 0; i < 10; ++i) { 2133 2323 /* Give PLL time to lock */ ··· 2448 2642 */ 2449 2643 snd_soc_component_read32(component, M98090_REG_DEVICE_STATUS); 2450 2644 2451 - /* 2452 - * SHDN should be 0 at the point, no need to save/restore for the 2453 - * following registers. 2454 - * 2455 - * High Performance is default 2456 - */ 2645 + /* High Performance is default */ 2457 2646 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, 2458 2647 M98090_DACHP_MASK, 2459 2648 1 << M98090_DACHP_SHIFT); ··· 2459 2658 M98090_ADCHP_MASK, 2460 2659 1 << M98090_ADCHP_SHIFT); 2461 2660 2462 - /* 2463 - * SHDN should be 0 at the point, no need to save/restore for the 2464 - * following registers. 2465 - * 2466 - * Turn on VCM bandgap reference 2467 - */ 2661 + /* Turn on VCM bandgap reference */ 2468 2662 snd_soc_component_write(component, M98090_REG_BIAS_CONTROL, 2469 2663 M98090_VCM_MODE_MASK); 2470 2664 ··· 2491 2695 max98090->component = NULL; 2492 2696 } 2493 2697 2698 + static void max98090_seq_notifier(struct snd_soc_component *component, 2699 + enum snd_soc_dapm_type event, int subseq) 2700 + { 2701 + struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2702 + 2703 + if (max98090->shdn_pending) { 2704 + snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2705 + M98090_SHDNN_MASK, 0); 2706 + msleep(40); 2707 + snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2708 + M98090_SHDNN_MASK, M98090_SHDNN_MASK); 2709 + max98090->shdn_pending = false; 2710 + } 2711 + } 2712 + 2494 2713 static const struct snd_soc_component_driver soc_component_dev_max98090 = { 2495 2714 .probe = max98090_probe, 2496 2715 .remove = max98090_remove, 2716 + .seq_notifier = max98090_seq_notifier, 2497 2717 .set_bias_level = max98090_set_bias_level, 2498 2718 .idle_bias_on = 1, 2499 2719 .use_pmdown_time = 1,
+1 -2
sound/soc/codecs/max98090.h
··· 1539 1539 unsigned int pa2en; 1540 1540 unsigned int sidetone; 1541 1541 bool master; 1542 - int saved_count; 1543 - int saved_shdn; 1542 + bool shdn_pending; 1544 1543 }; 1545 1544 1546 1545 int max98090_mic_detect(struct snd_soc_component *component,