Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branch 'bnxt_en-next'

Michael Chan says:

====================
bnxt_en: Misc. updates for net-next.

Miscellaneous updates including firmware spec update, ethtool -p blinking
LED support, RDMA SRIOV config callback, and minor fixes.

v2: Dropped the DCBX RoCE app TLV patch until the ETH_P_IBOE RDMA patch
is merged.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

+369 -25
+44
drivers/net/ethernet/broadcom/bnxt/bnxt.c
··· 2467 2467 static void bnxt_set_tpa_flags(struct bnxt *bp) 2468 2468 { 2469 2469 bp->flags &= ~BNXT_FLAG_TPA; 2470 + if (bp->flags & BNXT_FLAG_NO_AGG_RINGS) 2471 + return; 2470 2472 if (bp->dev->features & NETIF_F_LRO) 2471 2473 bp->flags |= BNXT_FLAG_LRO; 2472 2474 if (bp->dev->features & NETIF_F_GRO) ··· 4946 4944 return rc; 4947 4945 } 4948 4946 4947 + #ifdef CONFIG_RFS_ACCEL 4949 4948 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp) 4950 4949 { 4951 4950 #if defined(CONFIG_BNXT_SRIOV) ··· 4964 4961 #endif 4965 4962 return bp->pf.max_vnics; 4966 4963 } 4964 + #endif 4967 4965 4968 4966 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp) 4969 4967 { ··· 5619 5615 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 5620 5616 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN); 5621 5617 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5618 + } 5619 + 5620 + static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 5621 + { 5622 + struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 5623 + struct hwrm_port_led_qcaps_input req = {0}; 5624 + struct bnxt_pf_info *pf = &bp->pf; 5625 + int rc; 5626 + 5627 + if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601) 5628 + return 0; 5629 + 5630 + bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1); 5631 + req.port_id = cpu_to_le16(pf->port_id); 5632 + mutex_lock(&bp->hwrm_cmd_lock); 5633 + rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 5634 + if (rc) { 5635 + mutex_unlock(&bp->hwrm_cmd_lock); 5636 + return rc; 5637 + } 5638 + if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) { 5639 + int i; 5640 + 5641 + bp->num_leds = resp->num_leds; 5642 + memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) * 5643 + bp->num_leds); 5644 + for (i = 0; i < bp->num_leds; i++) { 5645 + struct bnxt_led_info *led = &bp->leds[i]; 5646 + __le16 caps = led->led_state_caps; 5647 + 5648 + if (!led->led_group_id || 5649 + !BNXT_LED_ALT_BLINK_CAP(caps)) { 5650 + bp->num_leds = 0; 5651 + break; 5652 + } 5653 + } 5654 + } 5655 + mutex_unlock(&bp->hwrm_cmd_lock); 5656 + return 0; 5622 5657 } 5623 5658 5624 5659 static bool bnxt_eee_config_ok(struct bnxt *bp) ··· 7283 7240 } 7284 7241 7285 7242 bnxt_hwrm_func_qcfg(bp); 7243 + bnxt_hwrm_port_led_qcaps(bp); 7286 7244 7287 7245 bnxt_set_tpa_flags(bp); 7288 7246 bnxt_set_ring_params(bp);
+17
drivers/net/ethernet/broadcom/bnxt/bnxt.h
··· 868 868 u8 queue_profile; 869 869 }; 870 870 871 + #define BNXT_MAX_LED 4 872 + 873 + struct bnxt_led_info { 874 + u8 led_id; 875 + u8 led_type; 876 + u8 led_group_id; 877 + u8 unused; 878 + __le16 led_state_caps; 879 + #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 880 + cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED)) 881 + 882 + __le16 led_color_caps; 883 + }; 884 + 871 885 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 872 886 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 873 887 #define BNXT_CAG_REG_BASE 0x300000 ··· 1137 1123 struct ethtool_eee eee; 1138 1124 u32 lpi_tmr_lo; 1139 1125 u32 lpi_tmr_hi; 1126 + 1127 + u8 num_leds; 1128 + struct bnxt_led_info leds[BNXT_MAX_LED]; 1140 1129 }; 1141 1130 1142 1131 #define BNXT_RX_STATS_OFFSET(counter) \
+43 -1
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
··· 2080 2080 return rc; 2081 2081 } 2082 2082 2083 + static int bnxt_set_phys_id(struct net_device *dev, 2084 + enum ethtool_phys_id_state state) 2085 + { 2086 + struct hwrm_port_led_cfg_input req = {0}; 2087 + struct bnxt *bp = netdev_priv(dev); 2088 + struct bnxt_pf_info *pf = &bp->pf; 2089 + struct bnxt_led_cfg *led_cfg; 2090 + u8 led_state; 2091 + __le16 duration; 2092 + int i, rc; 2093 + 2094 + if (!bp->num_leds || BNXT_VF(bp)) 2095 + return -EOPNOTSUPP; 2096 + 2097 + if (state == ETHTOOL_ID_ACTIVE) { 2098 + led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 2099 + duration = cpu_to_le16(500); 2100 + } else if (state == ETHTOOL_ID_INACTIVE) { 2101 + led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 2102 + duration = cpu_to_le16(0); 2103 + } else { 2104 + return -EINVAL; 2105 + } 2106 + bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1); 2107 + req.port_id = cpu_to_le16(pf->port_id); 2108 + req.num_leds = bp->num_leds; 2109 + led_cfg = (struct bnxt_led_cfg *)&req.led0_id; 2110 + for (i = 0; i < bp->num_leds; i++, led_cfg++) { 2111 + req.enables |= BNXT_LED_DFLT_ENABLES(i); 2112 + led_cfg->led_id = bp->leds[i].led_id; 2113 + led_cfg->led_state = led_state; 2114 + led_cfg->led_blink_on = duration; 2115 + led_cfg->led_blink_off = duration; 2116 + led_cfg->led_group_id = bp->leds[i].led_group_id; 2117 + } 2118 + rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2119 + if (rc) 2120 + rc = -EIO; 2121 + return rc; 2122 + } 2123 + 2083 2124 const struct ethtool_ops bnxt_ethtool_ops = { 2084 2125 .get_link_ksettings = bnxt_get_link_ksettings, 2085 2126 .set_link_ksettings = bnxt_set_link_ksettings, ··· 2152 2111 .set_eee = bnxt_set_eee, 2153 2112 .get_module_info = bnxt_get_module_info, 2154 2113 .get_module_eeprom = bnxt_get_module_eeprom, 2155 - .nway_reset = bnxt_nway_reset 2114 + .nway_reset = bnxt_nway_reset, 2115 + .set_phys_id = bnxt_set_phys_id, 2156 2116 };
+23
drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.h
··· 10 10 #ifndef BNXT_ETHTOOL_H 11 11 #define BNXT_ETHTOOL_H 12 12 13 + struct bnxt_led_cfg { 14 + u8 led_id; 15 + u8 led_state; 16 + u8 led_color; 17 + u8 unused; 18 + __le16 led_blink_on; 19 + __le16 led_blink_off; 20 + u8 led_group_id; 21 + u8 rsvd; 22 + }; 23 + 24 + #define BNXT_LED_DFLT_ENA \ 25 + (PORT_LED_CFG_REQ_ENABLES_LED0_ID | \ 26 + PORT_LED_CFG_REQ_ENABLES_LED0_STATE | \ 27 + PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON | \ 28 + PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF | \ 29 + PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID) 30 + 31 + #define BNXT_LED_DFLT_ENA_SHIFT 6 32 + 33 + #define BNXT_LED_DFLT_ENABLES(x) \ 34 + cpu_to_le32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x))) 35 + 13 36 extern const struct ethtool_ops bnxt_ethtool_ops; 14 37 15 38 u32 _bnxt_fw_to_ethtool_adv_spds(u16, u8);
+237 -24
drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
··· 1 1 /* Broadcom NetXtreme-C/E network driver. 2 2 * 3 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 - * Copyright (c) 2016 Broadcom Limited 4 + * Copyright (c) 2016-2017 Broadcom Limited 5 5 * 6 6 * This program is free software; you can redistribute it and/or modify 7 7 * it under the terms of the GNU General Public License as published by ··· 11 11 #ifndef BNXT_HSI_H 12 12 #define BNXT_HSI_H 13 13 14 - /* HSI and HWRM Specification 1.6.0 */ 14 + /* HSI and HWRM Specification 1.6.1 */ 15 15 #define HWRM_VERSION_MAJOR 1 16 16 #define HWRM_VERSION_MINOR 6 17 - #define HWRM_VERSION_UPDATE 0 17 + #define HWRM_VERSION_UPDATE 1 18 18 19 - #define HWRM_VERSION_STR "1.6.0" 19 + #define HWRM_VERSION_STR "1.6.1" 20 20 /* 21 21 * Following is the signature for HWRM message field that indicates not 22 22 * applicable (All F's). Need to cast it the size of the field if needed. ··· 549 549 __le32 dev_caps_cfg; 550 550 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 551 551 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 552 + #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 553 + #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 552 554 u8 roce_fw_maj; 553 555 u8 roce_fw_min; 554 556 u8 roce_fw_bld; ··· 1918 1916 u8 unused_1; 1919 1917 u8 unused_2; 1920 1918 u8 unused_3; 1919 + u8 valid; 1920 + }; 1921 + 1922 + /* hwrm_port_led_cfg */ 1923 + /* Input (64 bytes) */ 1924 + struct hwrm_port_led_cfg_input { 1925 + __le16 req_type; 1926 + __le16 cmpl_ring; 1927 + __le16 seq_id; 1928 + __le16 target_id; 1929 + __le64 resp_addr; 1930 + __le32 enables; 1931 + #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 1932 + #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 1933 + #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 1934 + #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 1935 + #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 1936 + #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 1937 + #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 1938 + #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 1939 + #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 1940 + #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 1941 + #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 1942 + #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 1943 + #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 1944 + #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 1945 + #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 1946 + #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 1947 + #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 1948 + #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 1949 + #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 1950 + #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 1951 + #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 1952 + #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 1953 + #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 1954 + #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 1955 + __le16 port_id; 1956 + u8 num_leds; 1957 + u8 rsvd; 1958 + u8 led0_id; 1959 + u8 led0_state; 1960 + #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 1961 + #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 1962 + #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 1963 + #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 1964 + #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 1965 + u8 led0_color; 1966 + #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 1967 + #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 1968 + #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 1969 + #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 1970 + u8 unused_0; 1971 + __le16 led0_blink_on; 1972 + __le16 led0_blink_off; 1973 + u8 led0_group_id; 1974 + u8 rsvd0; 1975 + u8 led1_id; 1976 + u8 led1_state; 1977 + #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 1978 + #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 1979 + #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 1980 + #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 1981 + #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 1982 + u8 led1_color; 1983 + #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 1984 + #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 1985 + #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 1986 + #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 1987 + u8 unused_1; 1988 + __le16 led1_blink_on; 1989 + __le16 led1_blink_off; 1990 + u8 led1_group_id; 1991 + u8 rsvd1; 1992 + u8 led2_id; 1993 + u8 led2_state; 1994 + #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 1995 + #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 1996 + #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 1997 + #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 1998 + #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 1999 + u8 led2_color; 2000 + #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 2001 + #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 2002 + #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 2003 + #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 2004 + u8 unused_2; 2005 + __le16 led2_blink_on; 2006 + __le16 led2_blink_off; 2007 + u8 led2_group_id; 2008 + u8 rsvd2; 2009 + u8 led3_id; 2010 + u8 led3_state; 2011 + #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 2012 + #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 2013 + #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 2014 + #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 2015 + #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 2016 + u8 led3_color; 2017 + #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 2018 + #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 2019 + #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 2020 + #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 2021 + u8 unused_3; 2022 + __le16 led3_blink_on; 2023 + __le16 led3_blink_off; 2024 + u8 led3_group_id; 2025 + u8 rsvd3; 2026 + }; 2027 + 2028 + /* Output (16 bytes) */ 2029 + struct hwrm_port_led_cfg_output { 2030 + __le16 error_code; 2031 + __le16 req_type; 2032 + __le16 seq_id; 2033 + __le16 resp_len; 2034 + __le32 unused_0; 2035 + u8 unused_1; 2036 + u8 unused_2; 2037 + u8 unused_3; 2038 + u8 valid; 2039 + }; 2040 + 2041 + /* hwrm_port_led_qcaps */ 2042 + /* Input (24 bytes) */ 2043 + struct hwrm_port_led_qcaps_input { 2044 + __le16 req_type; 2045 + __le16 cmpl_ring; 2046 + __le16 seq_id; 2047 + __le16 target_id; 2048 + __le64 resp_addr; 2049 + __le16 port_id; 2050 + __le16 unused_0[3]; 2051 + }; 2052 + 2053 + /* Output (48 bytes) */ 2054 + struct hwrm_port_led_qcaps_output { 2055 + __le16 error_code; 2056 + __le16 req_type; 2057 + __le16 seq_id; 2058 + __le16 resp_len; 2059 + u8 num_leds; 2060 + u8 unused_0[3]; 2061 + u8 led0_id; 2062 + u8 led0_type; 2063 + #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 2064 + #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 2065 + #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 2066 + u8 led0_group_id; 2067 + u8 unused_1; 2068 + __le16 led0_state_caps; 2069 + #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 2070 + #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 2071 + #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 2072 + #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2073 + #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2074 + __le16 led0_color_caps; 2075 + #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 2076 + #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2077 + #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2078 + u8 led1_id; 2079 + u8 led1_type; 2080 + #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 2081 + #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 2082 + #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 2083 + u8 led1_group_id; 2084 + u8 unused_2; 2085 + __le16 led1_state_caps; 2086 + #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 2087 + #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 2088 + #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 2089 + #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2090 + #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2091 + __le16 led1_color_caps; 2092 + #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 2093 + #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2094 + #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2095 + u8 led2_id; 2096 + u8 led2_type; 2097 + #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 2098 + #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 2099 + #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 2100 + u8 led2_group_id; 2101 + u8 unused_3; 2102 + __le16 led2_state_caps; 2103 + #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 2104 + #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 2105 + #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 2106 + #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2107 + #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2108 + __le16 led2_color_caps; 2109 + #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 2110 + #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2111 + #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2112 + u8 led3_id; 2113 + u8 led3_type; 2114 + #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 2115 + #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 2116 + #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 2117 + u8 led3_group_id; 2118 + u8 unused_4; 2119 + __le16 led3_state_caps; 2120 + #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 2121 + #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 2122 + #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 2123 + #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2124 + #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2125 + __le16 led3_color_caps; 2126 + #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 2127 + #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2128 + #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2129 + u8 unused_5; 2130 + u8 unused_6; 2131 + u8 unused_7; 1921 2132 u8 valid; 1922 2133 }; 1923 2134 ··· 4307 4092 __le64 src_data_addr; 4308 4093 __le16 data_len; 4309 4094 u8 hdr_cnt; 4310 - u8 unused_0; 4311 - __le16 port_id; 4312 - __le16 unused_1; 4095 + u8 unused_0[5]; 4313 4096 }; 4314 4097 4315 4098 /* Output (16 bytes) */ ··· 4324 4111 }; 4325 4112 4326 4113 /* hwrm_fw_get_structured_data */ 4327 - /* Input (40 bytes) */ 4114 + /* Input (32 bytes) */ 4328 4115 struct hwrm_fw_get_structured_data_input { 4329 4116 __le16 req_type; 4330 4117 __le16 cmpl_ring; ··· 4344 4131 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 4345 4132 u8 count; 4346 4133 u8 unused_0; 4347 - __le16 port_id; 4348 - __le16 unused_1[3]; 4349 4134 }; 4350 4135 4351 4136 /* Output (16 bytes) */ ··· 4827 4616 __le32 install_type; 4828 4617 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 4829 4618 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 4830 - __le32 unused_0; 4619 + __le16 flags; 4620 + __le16 unused_0; 4831 4621 }; 4832 4622 4833 4623 /* Output (24 bytes) */ ··· 5185 4973 struct hwrm_struct_hdr { 5186 4974 __le16 struct_id; 5187 4975 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 5188 - #define STRUCT_HDR_STRUCT_ID_DCBX_ETS_CFG 0x41dUL 5189 - #define STRUCT_HDR_STRUCT_ID_DCBX_PFC_CFG 0x41fUL 5190 - #define STRUCT_HDR_STRUCT_ID_DCBX_APP_CFG 0x421UL 5191 - #define STRUCT_HDR_STRUCT_ID_DCBX_STATE_CFG 0x422UL 5192 - #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC_CFG 0x424UL 5193 - #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE_CFG 0x426UL 4976 + #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 4977 + #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 4978 + #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 4979 + #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 4980 + #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 4981 + #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 4982 + #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 5194 4983 __le16 len; 5195 4984 u8 version; 5196 4985 u8 count; ··· 5201 4988 __le16 unused_0[3]; 5202 4989 }; 5203 4990 5204 - /* DCBX Application configuration structure (8 bytes) */ 5205 - struct hwrm_struct_data_dcbx_app_cfg { 5206 - __le16 protocol_id; 4991 + /* DCBX Application configuration structure (1057) (8 bytes) */ 4992 + struct hwrm_struct_data_dcbx_app { 4993 + __be16 protocol_id; 5207 4994 u8 protocol_selector; 5208 - #define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 5209 - #define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 5210 - #define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 5211 - #define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 4995 + #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 4996 + #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 4997 + #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 4998 + #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 5212 4999 u8 priority; 5213 5000 u8 valid; 5214 5001 u8 unused_0[3];
+5
drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c
··· 15 15 #include <linux/etherdevice.h> 16 16 #include "bnxt_hsi.h" 17 17 #include "bnxt.h" 18 + #include "bnxt_ulp.h" 18 19 #include "bnxt_sriov.h" 19 20 #include "bnxt_ethtool.h" 20 21 ··· 556 555 if (rc) 557 556 goto err_out2; 558 557 558 + bnxt_ulp_sriov_cfg(bp, *num_vfs); 559 + 559 560 rc = pci_enable_sriov(bp->pdev, *num_vfs); 560 561 if (rc) 561 562 goto err_out2; ··· 599 596 rtnl_lock(); 600 597 bnxt_restore_pf_fw_resources(bp); 601 598 rtnl_unlock(); 599 + 600 + bnxt_ulp_sriov_cfg(bp, 0); 602 601 } 603 602 604 603 int bnxt_sriov_configure(struct pci_dev *pdev, int num_vfs)