Merge tag 'edac_updates_for_v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

+3 -2

MAINTAINERS

··· 6467 6467 F: fs/ecryptfs/ 6468 6468 6469 6469 EDAC-AMD64 6470 - M: Borislav Petkov <bp@alien8.de> 6470 + M: Yazen Ghannam <yazen.ghannam@amd.com> 6471 6471 L: linux-edac@vger.kernel.org 6472 - S: Maintained 6472 + S: Supported 6473 6473 F: drivers/edac/amd64_edac* 6474 + F: drivers/edac/mce_amd* 6474 6475 6475 6476 EDAC-ARMADA 6476 6477 M: Jan Luebbe <jlu@pengutronix.de>

+2 -1

drivers/edac/Kconfig

··· 270 270 271 271 config EDAC_IGEN6 272 272 tristate "Intel client SoC Integrated MC" 273 - depends on PCI && X86_64 && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 273 + depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 274 + depends on X64_64 && X86_MCE_INTEL 274 275 help 275 276 Support for error detection and correction on the Intel 276 277 client SoC Integrated Memory Controller using In-Band ECC IP.

+2 -2

drivers/edac/aspeed_edac.c

··· 254 254 return rc; 255 255 } 256 256 257 - dev_dbg(mci->pdev, "dt: /memory node resources: first page r.start=0x%x, resource_size=0x%x, PAGE_SHIFT macro=0x%x\n", 258 - r.start, resource_size(&r), PAGE_SHIFT); 257 + dev_dbg(mci->pdev, "dt: /memory node resources: first page %pR, PAGE_SHIFT macro=0x%x\n", 258 + &r, PAGE_SHIFT); 259 259 260 260 csrow->first_page = r.start >> PAGE_SHIFT; 261 261 nr_pages = resource_size(&r) >> PAGE_SHIFT;

+162 -12

drivers/edac/i10nm_base.c

··· 13 13 #include "edac_module.h" 14 14 #include "skx_common.h" 15 15 16 - #define I10NM_REVISION "v0.0.4" 16 + #define I10NM_REVISION "v0.0.5" 17 17 #define EDAC_MOD_STR "i10nm_edac" 18 18 19 19 /* Debug macros */ ··· 24 24 pci_read_config_dword((d)->uracu, 0xd0, &(reg)) 25 25 #define I10NM_GET_IMC_BAR(d, i, reg) \ 26 26 pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg)) 27 + #define I10NM_GET_SAD(d, offset, i, reg)\ 28 + pci_read_config_dword((d)->sad_all, (offset) + (i) * 8, &(reg)) 29 + #define I10NM_GET_HBM_IMC_BAR(d, reg) \ 30 + pci_read_config_dword((d)->uracu, 0xd4, &(reg)) 31 + #define I10NM_GET_CAPID3_CFG(d, reg) \ 32 + pci_read_config_dword((d)->pcu_cr3, 0x90, &(reg)) 27 33 #define I10NM_GET_DIMMMTR(m, i, j) \ 28 - readl((m)->mbase + 0x2080c + (i) * (m)->chan_mmio_sz + (j) * 4) 34 + readl((m)->mbase + ((m)->hbm_mc ? 0x80c : 0x2080c) + \ 35 + (i) * (m)->chan_mmio_sz + (j) * 4) 29 36 #define I10NM_GET_MCDDRTCFG(m, i, j) \ 30 - readl((m)->mbase + 0x20970 + (i) * (m)->chan_mmio_sz + (j) * 4) 37 + readl((m)->mbase + ((m)->hbm_mc ? 0x970 : 0x20970) + \ 38 + (i) * (m)->chan_mmio_sz + (j) * 4) 31 39 #define I10NM_GET_MCMTR(m, i) \ 32 - readl((m)->mbase + 0x20ef8 + (i) * (m)->chan_mmio_sz) 40 + readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : 0x20ef8) + \ 41 + (i) * (m)->chan_mmio_sz) 33 42 #define I10NM_GET_AMAP(m, i) \ 34 - readl((m)->mbase + 0x20814 + (i) * (m)->chan_mmio_sz) 43 + readl((m)->mbase + ((m)->hbm_mc ? 0x814 : 0x20814) + \ 44 + (i) * (m)->chan_mmio_sz) 35 45 36 46 #define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23) 37 47 #define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12) 38 48 #define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \ 39 49 GET_BITFIELD(reg, 0, 10) + 1) << 12) 50 + #define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg) \ 51 + ((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000) 52 + 53 + #define I10NM_HBM_IMC_MMIO_SIZE 0x9000 54 + #define I10NM_IS_HBM_PRESENT(reg) GET_BITFIELD(reg, 27, 30) 55 + #define I10NM_IS_HBM_IMC(reg) GET_BITFIELD(reg, 29, 29) 56 + 57 + #define I10NM_MAX_SAD 16 58 + #define I10NM_SAD_ENABLE(reg) GET_BITFIELD(reg, 0, 0) 59 + #define I10NM_SAD_NM_CACHEABLE(reg) GET_BITFIELD(reg, 5, 5) 40 60 41 61 static struct list_head *i10nm_edac_list; 42 62 ··· 83 63 return pdev; 84 64 } 85 65 86 - static int i10nm_get_all_munits(void) 66 + static bool i10nm_check_2lm(struct res_config *cfg) 67 + { 68 + struct skx_dev *d; 69 + u32 reg; 70 + int i; 71 + 72 + list_for_each_entry(d, i10nm_edac_list, list) { 73 + d->sad_all = pci_get_dev_wrapper(d->seg, d->bus[1], 74 + PCI_SLOT(cfg->sad_all_devfn), 75 + PCI_FUNC(cfg->sad_all_devfn)); 76 + if (!d->sad_all) 77 + continue; 78 + 79 + for (i = 0; i < I10NM_MAX_SAD; i++) { 80 + I10NM_GET_SAD(d, cfg->sad_all_offset, i, reg); 81 + if (I10NM_SAD_ENABLE(reg) && I10NM_SAD_NM_CACHEABLE(reg)) { 82 + edac_dbg(2, "2-level memory configuration.\n"); 83 + return true; 84 + } 85 + } 86 + } 87 + 88 + return false; 89 + } 90 + 91 + static int i10nm_get_ddr_munits(void) 87 92 { 88 93 struct pci_dev *mdev; 89 94 void __iomem *mbase; ··· 136 91 edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n", 137 92 j++, base, reg); 138 93 139 - for (i = 0; i < I10NM_NUM_IMC; i++) { 94 + for (i = 0; i < I10NM_NUM_DDR_IMC; i++) { 140 95 mdev = pci_get_dev_wrapper(d->seg, d->bus[0], 141 96 12 + i, 0); 142 97 if (i == 0 && !mdev) { ··· 172 127 return 0; 173 128 } 174 129 130 + static bool i10nm_check_hbm_imc(struct skx_dev *d) 131 + { 132 + u32 reg; 133 + 134 + if (I10NM_GET_CAPID3_CFG(d, reg)) { 135 + i10nm_printk(KERN_ERR, "Failed to get capid3_cfg\n"); 136 + return false; 137 + } 138 + 139 + return I10NM_IS_HBM_PRESENT(reg) != 0; 140 + } 141 + 142 + static int i10nm_get_hbm_munits(void) 143 + { 144 + struct pci_dev *mdev; 145 + void __iomem *mbase; 146 + u32 reg, off, mcmtr; 147 + struct skx_dev *d; 148 + int i, lmc; 149 + u64 base; 150 + 151 + list_for_each_entry(d, i10nm_edac_list, list) { 152 + d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[1], 30, 3); 153 + if (!d->pcu_cr3) 154 + return -ENODEV; 155 + 156 + if (!i10nm_check_hbm_imc(d)) { 157 + i10nm_printk(KERN_DEBUG, "No hbm memory\n"); 158 + return -ENODEV; 159 + } 160 + 161 + if (I10NM_GET_SCK_BAR(d, reg)) { 162 + i10nm_printk(KERN_ERR, "Failed to get socket bar\n"); 163 + return -ENODEV; 164 + } 165 + base = I10NM_GET_SCK_MMIO_BASE(reg); 166 + 167 + if (I10NM_GET_HBM_IMC_BAR(d, reg)) { 168 + i10nm_printk(KERN_ERR, "Failed to get hbm mc bar\n"); 169 + return -ENODEV; 170 + } 171 + base += I10NM_GET_HBM_IMC_MMIO_OFFSET(reg); 172 + 173 + lmc = I10NM_NUM_DDR_IMC; 174 + 175 + for (i = 0; i < I10NM_NUM_HBM_IMC; i++) { 176 + mdev = pci_get_dev_wrapper(d->seg, d->bus[0], 177 + 12 + i / 4, 1 + i % 4); 178 + if (i == 0 && !mdev) { 179 + i10nm_printk(KERN_ERR, "No hbm mc found\n"); 180 + return -ENODEV; 181 + } 182 + if (!mdev) 183 + continue; 184 + 185 + d->imc[lmc].mdev = mdev; 186 + off = i * I10NM_HBM_IMC_MMIO_SIZE; 187 + 188 + edac_dbg(2, "hbm mc%d mmio base 0x%llx size 0x%x\n", 189 + lmc, base + off, I10NM_HBM_IMC_MMIO_SIZE); 190 + 191 + mbase = ioremap(base + off, I10NM_HBM_IMC_MMIO_SIZE); 192 + if (!mbase) { 193 + i10nm_printk(KERN_ERR, "Failed to ioremap for hbm mc 0x%llx\n", 194 + base + off); 195 + return -ENOMEM; 196 + } 197 + 198 + d->imc[lmc].mbase = mbase; 199 + d->imc[lmc].hbm_mc = true; 200 + 201 + mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0); 202 + if (!I10NM_IS_HBM_IMC(mcmtr)) { 203 + i10nm_printk(KERN_ERR, "This isn't an hbm mc!\n"); 204 + return -ENODEV; 205 + } 206 + 207 + lmc++; 208 + } 209 + } 210 + 211 + return 0; 212 + } 213 + 175 214 static struct res_config i10nm_cfg0 = { 176 215 .type = I10NM, 177 216 .decs_did = 0x3452, 178 217 .busno_cfg_offset = 0xcc, 179 218 .ddr_chan_mmio_sz = 0x4000, 219 + .sad_all_devfn = PCI_DEVFN(29, 0), 220 + .sad_all_offset = 0x108, 180 221 }; 181 222 182 223 static struct res_config i10nm_cfg1 = { ··· 270 139 .decs_did = 0x3452, 271 140 .busno_cfg_offset = 0xd0, 272 141 .ddr_chan_mmio_sz = 0x4000, 142 + .sad_all_devfn = PCI_DEVFN(29, 0), 143 + .sad_all_offset = 0x108, 273 144 }; 274 145 275 146 static struct res_config spr_cfg = { ··· 279 146 .decs_did = 0x3252, 280 147 .busno_cfg_offset = 0xd0, 281 148 .ddr_chan_mmio_sz = 0x8000, 149 + .hbm_chan_mmio_sz = 0x4000, 282 150 .support_ddr5 = true, 151 + .sad_all_devfn = PCI_DEVFN(10, 0), 152 + .sad_all_offset = 0x300, 283 153 }; 284 154 285 155 static const struct x86_cpu_id i10nm_cpuids[] = { ··· 315 179 struct dimm_info *dimm; 316 180 int i, j, ndimms; 317 181 318 - for (i = 0; i < I10NM_NUM_CHANNELS; i++) { 182 + for (i = 0; i < imc->num_channels; i++) { 319 183 if (!imc->mbase) 320 184 continue; 321 185 322 186 ndimms = 0; 323 187 amap = I10NM_GET_AMAP(imc, i); 324 - for (j = 0; j < I10NM_NUM_DIMMS; j++) { 188 + for (j = 0; j < imc->num_dimms; j++) { 325 189 dimm = edac_get_dimm(mci, i, j, 0); 326 190 mtr = I10NM_GET_DIMMMTR(imc, i, j); 327 191 mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i, j); ··· 414 278 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 415 279 return -EBUSY; 416 280 281 + if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 282 + return -ENODEV; 283 + 417 284 id = x86_match_cpu(i10nm_cpuids); 418 285 if (!id) 419 286 return -ENODEV; ··· 435 296 return -ENODEV; 436 297 } 437 298 438 - rc = i10nm_get_all_munits(); 439 - if (rc < 0) 299 + skx_set_mem_cfg(i10nm_check_2lm(cfg)); 300 + 301 + rc = i10nm_get_ddr_munits(); 302 + 303 + if (i10nm_get_hbm_munits() && rc) 440 304 goto fail; 441 305 442 306 list_for_each_entry(d, i10nm_edac_list, list) { ··· 460 318 d->imc[i].lmc = i; 461 319 d->imc[i].src_id = src_id; 462 320 d->imc[i].node_id = node_id; 463 - d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz; 321 + if (d->imc[i].hbm_mc) { 322 + d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz; 323 + d->imc[i].num_channels = I10NM_NUM_HBM_CHANNELS; 324 + d->imc[i].num_dimms = I10NM_NUM_HBM_DIMMS; 325 + } else { 326 + d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz; 327 + d->imc[i].num_channels = I10NM_NUM_DDR_CHANNELS; 328 + d->imc[i].num_dimms = I10NM_NUM_DDR_DIMMS; 329 + } 464 330 465 331 rc = skx_register_mci(&d->imc[i], d->imc[i].mdev, 466 332 "Intel_10nm Socket", EDAC_MOD_STR,

+349 -25

drivers/edac/igen6_edac.c

··· 22 22 #include <linux/io.h> 23 23 #include <asm/mach_traps.h> 24 24 #include <asm/nmi.h> 25 + #include <asm/mce.h> 25 26 26 27 #include "edac_mc.h" 27 28 #include "edac_module.h" 28 29 29 - #define IGEN6_REVISION "v2.4" 30 + #define IGEN6_REVISION "v2.5" 30 31 31 32 #define EDAC_MOD_STR "igen6_edac" 32 33 #define IGEN6_NMI_NAME "igen6_ibecc" ··· 41 40 42 41 #define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo)) 43 42 44 - #define NUM_IMC 1 /* Max memory controllers */ 43 + #define NUM_IMC 2 /* Max memory controllers */ 45 44 #define NUM_CHANNELS 2 /* Max channels */ 46 45 #define NUM_DIMMS 2 /* Max DIMMs per channel */ 47 46 ··· 54 53 /* Capability register C */ 55 54 #define CAPID_C_OFFSET 0xec 56 55 #define CAPID_C_IBECC BIT(15) 56 + 57 + /* Capability register E */ 58 + #define CAPID_E_OFFSET 0xf0 59 + #define CAPID_E_IBECC BIT(12) 57 60 58 61 /* Error Status */ 59 62 #define ERRSTS_OFFSET 0xc8 ··· 75 70 #define IBECC_ACTIVATE_EN BIT(0) 76 71 77 72 /* IBECC error log */ 78 - #define ECC_ERROR_LOG_OFFSET (IBECC_BASE + 0x170) 73 + #define ECC_ERROR_LOG_OFFSET (IBECC_BASE + res_cfg->ibecc_error_log_offset) 79 74 #define ECC_ERROR_LOG_CE BIT_ULL(62) 80 75 #define ECC_ERROR_LOG_UE BIT_ULL(63) 81 76 #define ECC_ERROR_LOG_ADDR_SHIFT 5 ··· 89 84 #define MCHBAR_SIZE 0x10000 90 85 91 86 /* Parameters for the channel decode stage */ 92 - #define MAD_INTER_CHANNEL_OFFSET 0x5000 87 + #define IMC_BASE (res_cfg->imc_base) 88 + #define MAD_INTER_CHANNEL_OFFSET IMC_BASE 93 89 #define MAD_INTER_CHANNEL_DDR_TYPE(v) GET_BITFIELD(v, 0, 2) 94 90 #define MAD_INTER_CHANNEL_ECHM(v) GET_BITFIELD(v, 3, 3) 95 91 #define MAD_INTER_CHANNEL_CH_L_MAP(v) GET_BITFIELD(v, 4, 4) 96 92 #define MAD_INTER_CHANNEL_CH_S_SIZE(v) ((u64)GET_BITFIELD(v, 12, 19) << 29) 97 93 98 94 /* Parameters for DRAM decode stage */ 99 - #define MAD_INTRA_CH0_OFFSET 0x5004 95 + #define MAD_INTRA_CH0_OFFSET (IMC_BASE + 4) 100 96 #define MAD_INTRA_CH_DIMM_L_MAP(v) GET_BITFIELD(v, 0, 0) 101 97 102 98 /* DIMM characteristics */ 103 - #define MAD_DIMM_CH0_OFFSET 0x500c 99 + #define MAD_DIMM_CH0_OFFSET (IMC_BASE + 0xc) 104 100 #define MAD_DIMM_CH_DIMM_L_SIZE(v) ((u64)GET_BITFIELD(v, 0, 6) << 29) 105 101 #define MAD_DIMM_CH_DLW(v) GET_BITFIELD(v, 7, 8) 106 102 #define MAD_DIMM_CH_DIMM_S_SIZE(v) ((u64)GET_BITFIELD(v, 16, 22) << 29) 107 103 #define MAD_DIMM_CH_DSW(v) GET_BITFIELD(v, 24, 25) 108 104 105 + /* Hash for memory controller selection */ 106 + #define MAD_MC_HASH_OFFSET (IMC_BASE + 0x1b8) 107 + #define MAC_MC_HASH_LSB(v) GET_BITFIELD(v, 1, 3) 108 + 109 109 /* Hash for channel selection */ 110 - #define CHANNEL_HASH_OFFSET 0X5024 110 + #define CHANNEL_HASH_OFFSET (IMC_BASE + 0x24) 111 111 /* Hash for enhanced channel selection */ 112 - #define CHANNEL_EHASH_OFFSET 0X5028 112 + #define CHANNEL_EHASH_OFFSET (IMC_BASE + 0x28) 113 113 #define CHANNEL_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6) 114 114 #define CHANNEL_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26) 115 115 #define CHANNEL_HASH_MODE(v) GET_BITFIELD(v, 28, 28) 116 116 117 + /* Parameters for memory slice decode stage */ 118 + #define MEM_SLICE_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6) 119 + #define MEM_SLICE_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26) 120 + 117 121 static struct res_config { 122 + bool machine_check; 118 123 int num_imc; 124 + u32 imc_base; 125 + u32 cmf_base; 126 + u32 cmf_size; 127 + u32 ms_hash_offset; 119 128 u32 ibecc_base; 129 + u32 ibecc_error_log_offset; 120 130 bool (*ibecc_available)(struct pci_dev *pdev); 121 131 /* Convert error address logged in IBECC to system physical address */ 122 - u64 (*err_addr_to_sys_addr)(u64 eaddr); 132 + u64 (*err_addr_to_sys_addr)(u64 eaddr, int mc); 123 133 /* Convert error address logged in IBECC to integrated memory controller address */ 124 - u64 (*err_addr_to_imc_addr)(u64 eaddr); 134 + u64 (*err_addr_to_imc_addr)(u64 eaddr, int mc); 125 135 } *res_cfg; 126 136 127 137 struct igen6_imc { ··· 145 125 struct pci_dev *pdev; 146 126 struct device dev; 147 127 void __iomem *window; 128 + u64 size; 148 129 u64 ch_s_size; 149 130 int ch_l_map; 150 131 u64 dimm_s_size[NUM_CHANNELS]; ··· 155 134 156 135 static struct igen6_pvt { 157 136 struct igen6_imc imc[NUM_IMC]; 137 + u64 ms_hash; 138 + u64 ms_s_size; 139 + int ms_l_map; 158 140 } *igen6_pvt; 159 141 160 142 /* The top of low usable DRAM */ ··· 207 183 #define DID_EHL_SKU14 0x4534 208 184 #define DID_EHL_SKU15 0x4536 209 185 186 + /* Compute die IDs for ICL-NNPI with IBECC */ 187 + #define DID_ICL_SKU8 0x4581 188 + #define DID_ICL_SKU10 0x4585 189 + #define DID_ICL_SKU11 0x4589 190 + #define DID_ICL_SKU12 0x458d 191 + 192 + /* Compute die IDs for Tiger Lake with IBECC */ 193 + #define DID_TGL_SKU 0x9a14 194 + 195 + /* Compute die IDs for Alder Lake with IBECC */ 196 + #define DID_ADL_SKU1 0x4601 197 + #define DID_ADL_SKU2 0x4602 198 + #define DID_ADL_SKU3 0x4621 199 + #define DID_ADL_SKU4 0x4641 200 + 210 201 static bool ehl_ibecc_available(struct pci_dev *pdev) 211 202 { 212 203 u32 v; ··· 232 193 return !!(CAPID_C_IBECC & v); 233 194 } 234 195 235 - static u64 ehl_err_addr_to_sys_addr(u64 eaddr) 196 + static u64 ehl_err_addr_to_sys_addr(u64 eaddr, int mc) 236 197 { 237 198 return eaddr; 238 199 } 239 200 240 - static u64 ehl_err_addr_to_imc_addr(u64 eaddr) 201 + static u64 ehl_err_addr_to_imc_addr(u64 eaddr, int mc) 241 202 { 242 203 if (eaddr < igen6_tolud) 243 204 return eaddr; ··· 251 212 return eaddr; 252 213 } 253 214 215 + static bool icl_ibecc_available(struct pci_dev *pdev) 216 + { 217 + u32 v; 218 + 219 + if (pci_read_config_dword(pdev, CAPID_C_OFFSET, &v)) 220 + return false; 221 + 222 + return !(CAPID_C_IBECC & v) && 223 + (boot_cpu_data.x86_stepping >= 1); 224 + } 225 + 226 + static bool tgl_ibecc_available(struct pci_dev *pdev) 227 + { 228 + u32 v; 229 + 230 + if (pci_read_config_dword(pdev, CAPID_E_OFFSET, &v)) 231 + return false; 232 + 233 + return !(CAPID_E_IBECC & v); 234 + } 235 + 236 + static u64 mem_addr_to_sys_addr(u64 maddr) 237 + { 238 + if (maddr < igen6_tolud) 239 + return maddr; 240 + 241 + if (igen6_tom <= _4GB) 242 + return maddr - igen6_tolud + _4GB; 243 + 244 + if (maddr < _4GB) 245 + return maddr - igen6_tolud + igen6_tom; 246 + 247 + return maddr; 248 + } 249 + 250 + static u64 mem_slice_hash(u64 addr, u64 mask, u64 hash_init, int intlv_bit) 251 + { 252 + u64 hash_addr = addr & mask, hash = hash_init; 253 + u64 intlv = (addr >> intlv_bit) & 1; 254 + int i; 255 + 256 + for (i = 6; i < 20; i++) 257 + hash ^= (hash_addr >> i) & 1; 258 + 259 + return hash ^ intlv; 260 + } 261 + 262 + static u64 tgl_err_addr_to_mem_addr(u64 eaddr, int mc) 263 + { 264 + u64 maddr, hash, mask, ms_s_size; 265 + int intlv_bit; 266 + u32 ms_hash; 267 + 268 + ms_s_size = igen6_pvt->ms_s_size; 269 + if (eaddr >= ms_s_size) 270 + return eaddr + ms_s_size; 271 + 272 + ms_hash = igen6_pvt->ms_hash; 273 + 274 + mask = MEM_SLICE_HASH_MASK(ms_hash); 275 + intlv_bit = MEM_SLICE_HASH_LSB_MASK_BIT(ms_hash) + 6; 276 + 277 + maddr = GET_BITFIELD(eaddr, intlv_bit, 63) << (intlv_bit + 1) | 278 + GET_BITFIELD(eaddr, 0, intlv_bit - 1); 279 + 280 + hash = mem_slice_hash(maddr, mask, mc, intlv_bit); 281 + 282 + return maddr | (hash << intlv_bit); 283 + } 284 + 285 + static u64 tgl_err_addr_to_sys_addr(u64 eaddr, int mc) 286 + { 287 + u64 maddr = tgl_err_addr_to_mem_addr(eaddr, mc); 288 + 289 + return mem_addr_to_sys_addr(maddr); 290 + } 291 + 292 + static u64 tgl_err_addr_to_imc_addr(u64 eaddr, int mc) 293 + { 294 + return eaddr; 295 + } 296 + 297 + static u64 adl_err_addr_to_sys_addr(u64 eaddr, int mc) 298 + { 299 + return mem_addr_to_sys_addr(eaddr); 300 + } 301 + 302 + static u64 adl_err_addr_to_imc_addr(u64 eaddr, int mc) 303 + { 304 + u64 imc_addr, ms_s_size = igen6_pvt->ms_s_size; 305 + struct igen6_imc *imc = &igen6_pvt->imc[mc]; 306 + int intlv_bit; 307 + u32 mc_hash; 308 + 309 + if (eaddr >= 2 * ms_s_size) 310 + return eaddr - ms_s_size; 311 + 312 + mc_hash = readl(imc->window + MAD_MC_HASH_OFFSET); 313 + 314 + intlv_bit = MAC_MC_HASH_LSB(mc_hash) + 6; 315 + 316 + imc_addr = GET_BITFIELD(eaddr, intlv_bit + 1, 63) << intlv_bit | 317 + GET_BITFIELD(eaddr, 0, intlv_bit - 1); 318 + 319 + return imc_addr; 320 + } 321 + 254 322 static struct res_config ehl_cfg = { 255 - .num_imc = 1, 256 - .ibecc_base = 0xdc00, 257 - .ibecc_available = ehl_ibecc_available, 258 - .err_addr_to_sys_addr = ehl_err_addr_to_sys_addr, 259 - .err_addr_to_imc_addr = ehl_err_addr_to_imc_addr, 323 + .num_imc = 1, 324 + .imc_base = 0x5000, 325 + .ibecc_base = 0xdc00, 326 + .ibecc_available = ehl_ibecc_available, 327 + .ibecc_error_log_offset = 0x170, 328 + .err_addr_to_sys_addr = ehl_err_addr_to_sys_addr, 329 + .err_addr_to_imc_addr = ehl_err_addr_to_imc_addr, 330 + }; 331 + 332 + static struct res_config icl_cfg = { 333 + .num_imc = 1, 334 + .imc_base = 0x5000, 335 + .ibecc_base = 0xd800, 336 + .ibecc_error_log_offset = 0x170, 337 + .ibecc_available = icl_ibecc_available, 338 + .err_addr_to_sys_addr = ehl_err_addr_to_sys_addr, 339 + .err_addr_to_imc_addr = ehl_err_addr_to_imc_addr, 340 + }; 341 + 342 + static struct res_config tgl_cfg = { 343 + .machine_check = true, 344 + .num_imc = 2, 345 + .imc_base = 0x5000, 346 + .cmf_base = 0x11000, 347 + .cmf_size = 0x800, 348 + .ms_hash_offset = 0xac, 349 + .ibecc_base = 0xd400, 350 + .ibecc_error_log_offset = 0x170, 351 + .ibecc_available = tgl_ibecc_available, 352 + .err_addr_to_sys_addr = tgl_err_addr_to_sys_addr, 353 + .err_addr_to_imc_addr = tgl_err_addr_to_imc_addr, 354 + }; 355 + 356 + static struct res_config adl_cfg = { 357 + .machine_check = true, 358 + .num_imc = 2, 359 + .imc_base = 0xd800, 360 + .ibecc_base = 0xd400, 361 + .ibecc_error_log_offset = 0x68, 362 + .ibecc_available = tgl_ibecc_available, 363 + .err_addr_to_sys_addr = adl_err_addr_to_sys_addr, 364 + .err_addr_to_imc_addr = adl_err_addr_to_imc_addr, 260 365 }; 261 366 262 367 static const struct pci_device_id igen6_pci_tbl[] = { ··· 415 232 { PCI_VDEVICE(INTEL, DID_EHL_SKU13), (kernel_ulong_t)&ehl_cfg }, 416 233 { PCI_VDEVICE(INTEL, DID_EHL_SKU14), (kernel_ulong_t)&ehl_cfg }, 417 234 { PCI_VDEVICE(INTEL, DID_EHL_SKU15), (kernel_ulong_t)&ehl_cfg }, 235 + { PCI_VDEVICE(INTEL, DID_ICL_SKU8), (kernel_ulong_t)&icl_cfg }, 236 + { PCI_VDEVICE(INTEL, DID_ICL_SKU10), (kernel_ulong_t)&icl_cfg }, 237 + { PCI_VDEVICE(INTEL, DID_ICL_SKU11), (kernel_ulong_t)&icl_cfg }, 238 + { PCI_VDEVICE(INTEL, DID_ICL_SKU12), (kernel_ulong_t)&icl_cfg }, 239 + { PCI_VDEVICE(INTEL, DID_TGL_SKU), (kernel_ulong_t)&tgl_cfg }, 240 + { PCI_VDEVICE(INTEL, DID_ADL_SKU1), (kernel_ulong_t)&adl_cfg }, 241 + { PCI_VDEVICE(INTEL, DID_ADL_SKU2), (kernel_ulong_t)&adl_cfg }, 242 + { PCI_VDEVICE(INTEL, DID_ADL_SKU3), (kernel_ulong_t)&adl_cfg }, 243 + { PCI_VDEVICE(INTEL, DID_ADL_SKU4), (kernel_ulong_t)&adl_cfg }, 418 244 { }, 419 245 }; 420 246 MODULE_DEVICE_TABLE(pci, igen6_pci_tbl); ··· 682 490 eaddr = ECC_ERROR_LOG_ADDR(node->ecclog) << 683 491 ECC_ERROR_LOG_ADDR_SHIFT; 684 492 res.mc = node->mc; 685 - res.sys_addr = res_cfg->err_addr_to_sys_addr(eaddr); 686 - res.imc_addr = res_cfg->err_addr_to_imc_addr(eaddr); 493 + res.sys_addr = res_cfg->err_addr_to_sys_addr(eaddr, res.mc); 494 + res.imc_addr = res_cfg->err_addr_to_imc_addr(eaddr, res.mc); 687 495 688 496 mci = igen6_pvt->imc[res.mc].mci; 689 497 ··· 732 540 return NMI_HANDLED; 733 541 } 734 542 543 + static int ecclog_mce_handler(struct notifier_block *nb, unsigned long val, 544 + void *data) 545 + { 546 + struct mce *mce = (struct mce *)data; 547 + char *type; 548 + 549 + if (mce->kflags & MCE_HANDLED_CEC) 550 + return NOTIFY_DONE; 551 + 552 + /* 553 + * Ignore unless this is a memory related error. 554 + * We don't check the bit MCI_STATUS_ADDRV of MCi_STATUS here, 555 + * since this bit isn't set on some CPU (e.g., Tiger Lake UP3). 556 + */ 557 + if ((mce->status & 0xefff) >> 7 != 1) 558 + return NOTIFY_DONE; 559 + 560 + if (mce->mcgstatus & MCG_STATUS_MCIP) 561 + type = "Exception"; 562 + else 563 + type = "Event"; 564 + 565 + edac_dbg(0, "CPU %d: Machine Check %s: 0x%llx Bank %d: 0x%llx\n", 566 + mce->extcpu, type, mce->mcgstatus, 567 + mce->bank, mce->status); 568 + edac_dbg(0, "TSC 0x%llx\n", mce->tsc); 569 + edac_dbg(0, "ADDR 0x%llx\n", mce->addr); 570 + edac_dbg(0, "MISC 0x%llx\n", mce->misc); 571 + edac_dbg(0, "PROCESSOR %u:0x%x TIME %llu SOCKET %u APIC 0x%x\n", 572 + mce->cpuvendor, mce->cpuid, mce->time, 573 + mce->socketid, mce->apicid); 574 + /* 575 + * We just use the Machine Check for the memory error notification. 576 + * Each memory controller is associated with an IBECC instance. 577 + * Directly read and clear the error information(error address and 578 + * error type) on all the IBECC instances so that we know on which 579 + * memory controller the memory error(s) occurred. 580 + */ 581 + if (!ecclog_handler()) 582 + return NOTIFY_DONE; 583 + 584 + mce->kflags |= MCE_HANDLED_EDAC; 585 + 586 + return NOTIFY_DONE; 587 + } 588 + 589 + static struct notifier_block ecclog_mce_dec = { 590 + .notifier_call = ecclog_mce_handler, 591 + .priority = MCE_PRIO_EDAC, 592 + }; 593 + 735 594 static bool igen6_check_ecc(struct igen6_imc *imc) 736 595 { 737 596 u32 activate = readl(imc->window + IBECC_ACTIVATE_OFFSET); ··· 816 573 imc->dimm_l_size[i] = MAD_DIMM_CH_DIMM_L_SIZE(mad_dimm); 817 574 imc->dimm_s_size[i] = MAD_DIMM_CH_DIMM_S_SIZE(mad_dimm); 818 575 imc->dimm_l_map[i] = MAD_INTRA_CH_DIMM_L_MAP(mad_intra); 576 + imc->size += imc->dimm_s_size[i]; 577 + imc->size += imc->dimm_l_size[i]; 819 578 ndimms = 0; 820 579 821 580 for (j = 0; j < NUM_DIMMS; j++) { ··· 852 607 return -ENODEV; 853 608 } 854 609 } 610 + 611 + edac_dbg(0, "MC %d, total size %llu MiB\n", mc, imc->size >> 20); 855 612 856 613 return 0; 857 614 } ··· 1104 857 } 1105 858 } 1106 859 860 + static int igen6_mem_slice_setup(u64 mchbar) 861 + { 862 + struct igen6_imc *imc = &igen6_pvt->imc[0]; 863 + u64 base = mchbar + res_cfg->cmf_base; 864 + u32 offset = res_cfg->ms_hash_offset; 865 + u32 size = res_cfg->cmf_size; 866 + u64 ms_s_size, ms_hash; 867 + void __iomem *cmf; 868 + int ms_l_map; 869 + 870 + edac_dbg(2, "\n"); 871 + 872 + if (imc[0].size < imc[1].size) { 873 + ms_s_size = imc[0].size; 874 + ms_l_map = 1; 875 + } else { 876 + ms_s_size = imc[1].size; 877 + ms_l_map = 0; 878 + } 879 + 880 + igen6_pvt->ms_s_size = ms_s_size; 881 + igen6_pvt->ms_l_map = ms_l_map; 882 + 883 + edac_dbg(0, "ms_s_size: %llu MiB, ms_l_map %d\n", 884 + ms_s_size >> 20, ms_l_map); 885 + 886 + if (!size) 887 + return 0; 888 + 889 + cmf = ioremap(base, size); 890 + if (!cmf) { 891 + igen6_printk(KERN_ERR, "Failed to ioremap cmf 0x%llx\n", base); 892 + return -ENODEV; 893 + } 894 + 895 + ms_hash = readq(cmf + offset); 896 + igen6_pvt->ms_hash = ms_hash; 897 + 898 + edac_dbg(0, "MEM_SLICE_HASH: 0x%llx\n", ms_hash); 899 + 900 + iounmap(cmf); 901 + 902 + return 0; 903 + } 904 + 905 + static int register_err_handler(void) 906 + { 907 + int rc; 908 + 909 + if (res_cfg->machine_check) { 910 + mce_register_decode_chain(&ecclog_mce_dec); 911 + return 0; 912 + } 913 + 914 + rc = register_nmi_handler(NMI_SERR, ecclog_nmi_handler, 915 + 0, IGEN6_NMI_NAME); 916 + if (rc) { 917 + igen6_printk(KERN_ERR, "Failed to register NMI handler\n"); 918 + return rc; 919 + } 920 + 921 + return 0; 922 + } 923 + 924 + static void unregister_err_handler(void) 925 + { 926 + if (res_cfg->machine_check) { 927 + mce_unregister_decode_chain(&ecclog_mce_dec); 928 + return; 929 + } 930 + 931 + unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME); 932 + } 933 + 1107 934 static int igen6_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1108 935 { 1109 936 u64 mchbar; ··· 1201 880 goto fail2; 1202 881 } 1203 882 883 + if (res_cfg->num_imc > 1) { 884 + rc = igen6_mem_slice_setup(mchbar); 885 + if (rc) 886 + goto fail2; 887 + } 888 + 1204 889 ecclog_pool = ecclog_gen_pool_create(); 1205 890 if (!ecclog_pool) { 1206 891 rc = -ENOMEM; ··· 1219 892 /* Check if any pending errors before registering the NMI handler */ 1220 893 ecclog_handler(); 1221 894 1222 - rc = register_nmi_handler(NMI_SERR, ecclog_nmi_handler, 1223 - 0, IGEN6_NMI_NAME); 1224 - if (rc) { 1225 - igen6_printk(KERN_ERR, "Failed to register NMI handler\n"); 895 + rc = register_err_handler(); 896 + if (rc) 1226 897 goto fail3; 1227 - } 1228 898 1229 899 /* Enable error reporting */ 1230 900 rc = errcmd_enable_error_reporting(true); ··· 1249 925 1250 926 igen6_debug_teardown(); 1251 927 errcmd_enable_error_reporting(false); 1252 - unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME); 928 + unregister_err_handler(); 1253 929 irq_work_sync(&ecclog_irq_work); 1254 930 flush_work(&ecclog_work); 1255 931 gen_pool_destroy(ecclog_pool);

+3

drivers/edac/pnd2_edac.c

··· 1554 1554 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 1555 1555 return -EBUSY; 1556 1556 1557 + if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 1558 + return -ENODEV; 1559 + 1557 1560 id = x86_match_cpu(pnd2_cpuids); 1558 1561 if (!id) 1559 1562 return -ENODEV;

+3

drivers/edac/sb_edac.c

··· 3510 3510 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 3511 3511 return -EBUSY; 3512 3512 3513 + if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 3514 + return -ENODEV; 3515 + 3513 3516 id = x86_match_cpu(sbridge_cpuids); 3514 3517 if (!id) 3515 3518 return -ENODEV;

+3

drivers/edac/skx_base.c

··· 656 656 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 657 657 return -EBUSY; 658 658 659 + if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 660 + return -ENODEV; 661 + 659 662 id = x86_match_cpu(skx_cpuids); 660 663 if (!id) 661 664 return -ENODEV;

+67 -15

drivers/edac/skx_common.c

··· 23 23 #include "skx_common.h" 24 24 25 25 static const char * const component_names[] = { 26 - [INDEX_SOCKET] = "ProcessorSocketId", 27 - [INDEX_MEMCTRL] = "MemoryControllerId", 28 - [INDEX_CHANNEL] = "ChannelId", 29 - [INDEX_DIMM] = "DimmSlotId", 26 + [INDEX_SOCKET] = "ProcessorSocketId", 27 + [INDEX_MEMCTRL] = "MemoryControllerId", 28 + [INDEX_CHANNEL] = "ChannelId", 29 + [INDEX_DIMM] = "DimmSlotId", 30 + [INDEX_NM_MEMCTRL] = "NmMemoryControllerId", 31 + [INDEX_NM_CHANNEL] = "NmChannelId", 32 + [INDEX_NM_DIMM] = "NmDimmSlotId", 30 33 }; 31 34 32 35 static int component_indices[ARRAY_SIZE(component_names)]; ··· 37 34 static const char * const *adxl_component_names; 38 35 static u64 *adxl_values; 39 36 static char *adxl_msg; 37 + static unsigned long adxl_nm_bitmap; 40 38 41 39 static char skx_msg[MSG_SIZE]; 42 40 static skx_decode_f skx_decode; 43 41 static skx_show_retry_log_f skx_show_retry_rd_err_log; 44 42 static u64 skx_tolm, skx_tohm; 45 43 static LIST_HEAD(dev_edac_list); 44 + static bool skx_mem_cfg_2lm; 46 45 47 46 int __init skx_adxl_get(void) 48 47 { ··· 61 56 for (j = 0; names[j]; j++) { 62 57 if (!strcmp(component_names[i], names[j])) { 63 58 component_indices[i] = j; 59 + 60 + if (i >= INDEX_NM_FIRST) 61 + adxl_nm_bitmap |= 1 << i; 62 + 64 63 break; 65 64 } 66 65 } 67 66 68 - if (!names[j]) 67 + if (!names[j] && i < INDEX_NM_FIRST) 69 68 goto err; 69 + } 70 + 71 + if (skx_mem_cfg_2lm) { 72 + if (!adxl_nm_bitmap) 73 + skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n"); 74 + else 75 + edac_dbg(2, "adxl_nm_bitmap: 0x%lx\n", adxl_nm_bitmap); 70 76 } 71 77 72 78 adxl_component_names = names; ··· 115 99 kfree(adxl_msg); 116 100 } 117 101 118 - static bool skx_adxl_decode(struct decoded_addr *res) 102 + static bool skx_adxl_decode(struct decoded_addr *res, bool error_in_1st_level_mem) 119 103 { 120 104 struct skx_dev *d; 121 105 int i, len = 0; ··· 132 116 } 133 117 134 118 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]]; 135 - res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]]; 136 - res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]]; 137 - res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]]; 119 + if (error_in_1st_level_mem) { 120 + res->imc = (adxl_nm_bitmap & BIT_NM_MEMCTRL) ? 121 + (int)adxl_values[component_indices[INDEX_NM_MEMCTRL]] : -1; 122 + res->channel = (adxl_nm_bitmap & BIT_NM_CHANNEL) ? 123 + (int)adxl_values[component_indices[INDEX_NM_CHANNEL]] : -1; 124 + res->dimm = (adxl_nm_bitmap & BIT_NM_DIMM) ? 125 + (int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1; 126 + } else { 127 + res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]]; 128 + res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]]; 129 + res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]]; 130 + } 138 131 139 - if (res->imc > NUM_IMC - 1) { 132 + if (res->imc > NUM_IMC - 1 || res->imc < 0) { 140 133 skx_printk(KERN_ERR, "Bad imc %d\n", res->imc); 141 134 return false; 142 135 } ··· 174 149 } 175 150 176 151 return true; 152 + } 153 + 154 + void skx_set_mem_cfg(bool mem_cfg_2lm) 155 + { 156 + skx_mem_cfg_2lm = mem_cfg_2lm; 177 157 } 178 158 179 159 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log) ··· 343 313 344 314 ranks = numrank(mtr); 345 315 rows = numrow(mtr); 346 - cols = numcol(mtr); 316 + cols = imc->hbm_mc ? 6 : numcol(mtr); 347 317 348 - if (cfg->support_ddr5 && (amap & 0x8)) { 318 + if (cfg->support_ddr5 && ((amap & 0x8) || imc->hbm_mc)) { 349 319 banks = 32; 350 320 mtype = MEM_DDR5; 351 321 } else { ··· 374 344 dimm->dtype = get_width(mtr); 375 345 dimm->mtype = mtype; 376 346 dimm->edac_mode = EDAC_SECDED; /* likely better than this */ 377 - snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", 378 - imc->src_id, imc->lmc, chan, dimmno); 347 + 348 + if (imc->hbm_mc) 349 + snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u", 350 + imc->src_id, imc->lmc, chan); 351 + else 352 + snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", 353 + imc->src_id, imc->lmc, chan, dimmno); 379 354 380 355 return 1; 381 356 } ··· 613 578 optype, skx_msg); 614 579 } 615 580 581 + static bool skx_error_in_1st_level_mem(const struct mce *m) 582 + { 583 + u32 errcode; 584 + 585 + if (!skx_mem_cfg_2lm) 586 + return false; 587 + 588 + errcode = GET_BITFIELD(m->status, 0, 15); 589 + 590 + if ((errcode & 0xef80) != 0x280) 591 + return false; 592 + 593 + return true; 594 + } 595 + 616 596 int skx_mce_check_error(struct notifier_block *nb, unsigned long val, 617 597 void *data) 618 598 { ··· 647 597 res.addr = mce->addr; 648 598 649 599 if (adxl_component_count) { 650 - if (!skx_adxl_decode(&res)) 600 + if (!skx_adxl_decode(&res, skx_error_in_1st_level_mem(mce))) 651 601 return NOTIFY_DONE; 652 602 } else if (!skx_decode || !skx_decode(&res)) { 653 603 return NOTIFY_DONE; ··· 708 658 } 709 659 if (d->util_all) 710 660 pci_dev_put(d->util_all); 661 + if (d->pcu_cr3) 662 + pci_dev_put(d->pcu_cr3); 711 663 if (d->sad_all) 712 664 pci_dev_put(d->sad_all); 713 665 if (d->uracu)

+31 -3

drivers/edac/skx_common.h

··· 9 9 #ifndef _SKX_COMM_EDAC_H 10 10 #define _SKX_COMM_EDAC_H 11 11 12 + #include <linux/bits.h> 13 + 12 14 #define MSG_SIZE 1024 13 15 14 16 /* ··· 32 30 #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */ 33 31 #define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */ 34 32 35 - #define I10NM_NUM_IMC 4 36 - #define I10NM_NUM_CHANNELS 2 37 - #define I10NM_NUM_DIMMS 2 33 + #define I10NM_NUM_DDR_IMC 4 34 + #define I10NM_NUM_DDR_CHANNELS 2 35 + #define I10NM_NUM_DDR_DIMMS 2 36 + 37 + #define I10NM_NUM_HBM_IMC 16 38 + #define I10NM_NUM_HBM_CHANNELS 2 39 + #define I10NM_NUM_HBM_DIMMS 1 40 + 41 + #define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC) 42 + #define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS) 43 + #define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS) 38 44 39 45 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 40 46 #define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC) ··· 64 54 struct pci_dev *sad_all; 65 55 struct pci_dev *util_all; 66 56 struct pci_dev *uracu; /* for i10nm CPU */ 57 + struct pci_dev *pcu_cr3; /* for HBM memory detection */ 67 58 u32 mcroute; 68 59 struct skx_imc { 69 60 struct mem_ctl_info *mci; 70 61 struct pci_dev *mdev; /* for i10nm CPU */ 71 62 void __iomem *mbase; /* for i10nm CPU */ 72 63 int chan_mmio_sz; /* for i10nm CPU */ 64 + int num_channels; /* channels per memory controller */ 65 + int num_dimms; /* dimms per channel */ 66 + bool hbm_mc; 73 67 u8 mc; /* system wide mc# */ 74 68 u8 lmc; /* socket relative mc# */ 75 69 u8 src_id, node_id; ··· 106 92 INDEX_MEMCTRL, 107 93 INDEX_CHANNEL, 108 94 INDEX_DIMM, 95 + INDEX_NM_FIRST, 96 + INDEX_NM_MEMCTRL = INDEX_NM_FIRST, 97 + INDEX_NM_CHANNEL, 98 + INDEX_NM_DIMM, 109 99 INDEX_MAX 110 100 }; 101 + 102 + #define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL) 103 + #define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL) 104 + #define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM) 111 105 112 106 struct decoded_addr { 113 107 struct skx_dev *dev; ··· 144 122 int busno_cfg_offset; 145 123 /* Per DDR channel memory-mapped I/O size */ 146 124 int ddr_chan_mmio_sz; 125 + /* Per HBM channel memory-mapped I/O size */ 126 + int hbm_chan_mmio_sz; 147 127 bool support_ddr5; 128 + /* SAD device number and function number */ 129 + unsigned int sad_all_devfn; 130 + int sad_all_offset; 148 131 }; 149 132 150 133 typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci, ··· 160 133 int __init skx_adxl_get(void); 161 134 void __exit skx_adxl_put(void); 162 135 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log); 136 + void skx_set_mem_cfg(bool mem_cfg_2lm); 163 137 164 138 int skx_get_src_id(struct skx_dev *d, int off, u8 *id); 165 139 int skx_get_node_id(struct skx_dev *d, u8 *id);

+2 -2

drivers/edac/thunderx_edac.c

··· 1368 1368 name, 1, "CCPI", 1, 1369 1369 0, NULL, 0, idx); 1370 1370 if (!edac_dev) { 1371 - dev_err(&pdev->dev, "Cannot allocate EDAC device: %d\n", ret); 1371 + dev_err(&pdev->dev, "Cannot allocate EDAC device\n"); 1372 1372 return -ENOMEM; 1373 1373 } 1374 1374 ocx = edac_dev->pvt_info; ··· 1380 1380 1381 1381 ocx->regs = pcim_iomap_table(pdev)[0]; 1382 1382 if (!ocx->regs) { 1383 - dev_err(&pdev->dev, "Cannot map PCI resources: %d\n", ret); 1383 + dev_err(&pdev->dev, "Cannot map PCI resources\n"); 1384 1384 ret = -ENODEV; 1385 1385 goto err_free; 1386 1386 }

+1

drivers/edac/ti_edac.c

··· 197 197 { .compatible = "ti,emif-dra7xx", .data = (void *)EMIF_TYPE_DRA7 }, 198 198 {}, 199 199 }; 200 + MODULE_DEVICE_TABLE(of, ti_edac_of_match); 200 201 201 202 static int _emif_get_id(struct device_node *node) 202 203 {