Merge branch 'ib-gpio_generic_chip_init' into devel

+90 -91

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

··· 4 4 5 5 #include <linux/device.h> 6 6 #include <linux/gpio/driver.h> 7 + #include <linux/gpio/generic.h> 7 8 #include <linux/interrupt.h> 8 9 #include <linux/irq.h> 9 10 #include <linux/mfd/syscon.h> ··· 78 77 /* Structure for register banks */ 79 78 struct npcm7xx_gpio { 80 79 void __iomem *base; 81 - struct gpio_chip gc; 80 + struct gpio_generic_chip chip; 82 81 int irqbase; 83 82 int irq; 84 83 u32 pinctrl_id; ··· 100 99 }; 101 100 102 101 /* GPIO handling in the pinctrl driver */ 103 - static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg, 102 + static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *reg, 104 103 unsigned int pinmask) 105 104 { 106 - unsigned long flags; 107 105 unsigned long val; 108 106 109 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 107 + guard(gpio_generic_lock_irqsave)(chip); 110 108 111 109 val = ioread32(reg) | pinmask; 112 110 iowrite32(val, reg); 113 - 114 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 115 111 } 116 112 117 - static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, 113 + static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *reg, 118 114 unsigned int pinmask) 119 115 { 120 - unsigned long flags; 121 116 unsigned long val; 122 117 123 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 118 + guard(gpio_generic_lock_irqsave)(chip); 124 119 125 120 val = ioread32(reg) & ~pinmask; 126 121 iowrite32(val, reg); 127 - 128 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 129 122 } 130 123 131 124 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) ··· 127 132 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); 128 133 129 134 seq_printf(s, "-- module %d [gpio%d - %d]\n", 130 - bank->gc.base / bank->gc.ngpio, 131 - bank->gc.base, 132 - bank->gc.base + bank->gc.ngpio); 135 + bank->chip.gc.base / bank->chip.gc.ngpio, 136 + bank->chip.gc.base, 137 + bank->chip.gc.base + bank->chip.gc.ngpio); 133 138 seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n", 134 139 ioread32(bank->base + NPCM7XX_GP_N_DIN), 135 140 ioread32(bank->base + NPCM7XX_GP_N_DOUT), ··· 215 220 chained_irq_enter(chip, desc); 216 221 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); 217 222 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); 218 - dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts, 223 + dev_dbg(bank->chip.gc.parent, "==> got irq sts %.8lx %.8lx\n", sts, 219 224 en); 220 225 221 226 sts &= en; ··· 230 235 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); 231 236 unsigned int gpio = BIT(irqd_to_hwirq(d)); 232 237 233 - dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio, 238 + dev_dbg(bank->chip.gc.parent, "setirqtype: %u.%u = %u\n", gpio, 234 239 d->irq, type); 235 240 switch (type) { 236 241 case IRQ_TYPE_EDGE_RISING: 237 - dev_dbg(bank->gc.parent, "edge.rising\n"); 238 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); 239 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 242 + dev_dbg(bank->chip.gc.parent, "edge.rising\n"); 243 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); 244 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 240 245 break; 241 246 case IRQ_TYPE_EDGE_FALLING: 242 - dev_dbg(bank->gc.parent, "edge.falling\n"); 243 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); 244 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 247 + dev_dbg(bank->chip.gc.parent, "edge.falling\n"); 248 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); 249 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 245 250 break; 246 251 case IRQ_TYPE_EDGE_BOTH: 247 - dev_dbg(bank->gc.parent, "edge.both\n"); 248 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); 252 + dev_dbg(bank->chip.gc.parent, "edge.both\n"); 253 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); 249 254 break; 250 255 case IRQ_TYPE_LEVEL_LOW: 251 - dev_dbg(bank->gc.parent, "level.low\n"); 252 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 256 + dev_dbg(bank->chip.gc.parent, "level.low\n"); 257 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 253 258 break; 254 259 case IRQ_TYPE_LEVEL_HIGH: 255 - dev_dbg(bank->gc.parent, "level.high\n"); 256 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); 260 + dev_dbg(bank->chip.gc.parent, "level.high\n"); 261 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 257 262 break; 258 263 default: 259 - dev_dbg(bank->gc.parent, "invalid irq type\n"); 264 + dev_dbg(bank->chip.gc.parent, "invalid irq type\n"); 260 265 return -EINVAL; 261 266 } 262 267 263 268 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 264 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 269 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 265 270 irq_set_handler_locked(d, handle_level_irq); 266 271 } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING 267 272 | IRQ_TYPE_EDGE_FALLING)) { 268 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 273 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 269 274 irq_set_handler_locked(d, handle_edge_irq); 270 275 } 271 276 ··· 278 283 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); 279 284 unsigned int gpio = irqd_to_hwirq(d); 280 285 281 - dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); 286 + dev_dbg(bank->chip.gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); 282 287 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); 283 288 } 284 289 ··· 290 295 unsigned int gpio = irqd_to_hwirq(d); 291 296 292 297 /* Clear events */ 293 - dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); 298 + dev_dbg(bank->chip.gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); 294 299 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); 295 300 gpiochip_disable_irq(gc, gpio); 296 301 } ··· 304 309 305 310 /* Enable events */ 306 311 gpiochip_enable_irq(gc, gpio); 307 - dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); 312 + dev_dbg(bank->chip.gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); 308 313 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); 309 314 } 310 315 ··· 1418 1423 struct regmap *gcr_regmap, unsigned int pin) 1419 1424 { 1420 1425 u32 val; 1421 - int gpio = (pin % bank->gc.ngpio); 1426 + int gpio = (pin % bank->chip.gc.ngpio); 1422 1427 unsigned long pinmask = BIT(gpio); 1423 1428 1424 1429 if (pincfg[pin].flag & SLEW) ··· 1438 1443 struct regmap *gcr_regmap, unsigned int pin, 1439 1444 int arg) 1440 1445 { 1441 - int gpio = BIT(pin % bank->gc.ngpio); 1446 + int gpio = BIT(pin % bank->chip.gc.ngpio); 1442 1447 1443 1448 if (pincfg[pin].flag & SLEW) { 1444 1449 switch (arg) { 1445 1450 case 0: 1446 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, 1451 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_OSRC, 1447 1452 gpio); 1448 1453 return 0; 1449 1454 case 1: 1450 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, 1455 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_OSRC, 1451 1456 gpio); 1452 1457 return 0; 1453 1458 default: ··· 1480 1485 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1481 1486 struct npcm7xx_gpio *bank = 1482 1487 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1483 - int gpio = (pin % bank->gc.ngpio); 1488 + int gpio = (pin % bank->chip.gc.ngpio); 1484 1489 unsigned long pinmask = BIT(gpio); 1485 1490 u32 ds = 0; 1486 1491 int flg, val; ··· 1491 1496 val = ioread32(bank->base + NPCM7XX_GP_N_ODSC) 1492 1497 & pinmask; 1493 1498 ds = val ? DSHI(flg) : DSLO(flg); 1494 - dev_dbg(bank->gc.parent, 1499 + dev_dbg(bank->chip.gc.parent, 1495 1500 "pin %d strength %d = %d\n", pin, val, ds); 1496 1501 return ds; 1497 1502 } ··· 1506 1511 int v; 1507 1512 struct npcm7xx_gpio *bank = 1508 1513 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1509 - int gpio = BIT(pin % bank->gc.ngpio); 1514 + int gpio = BIT(pin % bank->chip.gc.ngpio); 1510 1515 1511 1516 v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK); 1512 1517 if (!nval || !v) 1513 1518 return -ENOTSUPP; 1514 1519 if (DSLO(v) == nval) { 1515 - dev_dbg(bank->gc.parent, 1520 + dev_dbg(bank->chip.gc.parent, 1516 1521 "setting pin %d to low strength [%d]\n", pin, nval); 1517 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1522 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1518 1523 return 0; 1519 1524 } else if (DSHI(v) == nval) { 1520 - dev_dbg(bank->gc.parent, 1525 + dev_dbg(bank->chip.gc.parent, 1521 1526 "setting pin %d to high strength [%d]\n", pin, nval); 1522 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1527 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1523 1528 return 0; 1524 1529 } 1525 1530 ··· 1652 1657 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1653 1658 struct npcm7xx_gpio *bank = 1654 1659 &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK]; 1655 - int gpio = BIT(offset % bank->gc.ngpio); 1660 + int gpio = BIT(offset % bank->chip.gc.ngpio); 1656 1661 1657 - dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset, 1662 + dev_dbg(bank->chip.gc.parent, "GPIO Set Direction: %d = %d\n", offset, 1658 1663 input); 1659 1664 if (input) 1660 1665 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); ··· 1682 1687 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1683 1688 struct npcm7xx_gpio *bank = 1684 1689 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1685 - int gpio = (pin % bank->gc.ngpio); 1690 + int gpio = (pin % bank->chip.gc.ngpio); 1686 1691 unsigned long pinmask = BIT(gpio); 1687 1692 u32 ie, oe, pu, pd; 1688 1693 int rc = 0; ··· 1745 1750 u16 arg = pinconf_to_config_argument(config); 1746 1751 struct npcm7xx_gpio *bank = 1747 1752 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1748 - int gpio = BIT(pin % bank->gc.ngpio); 1753 + int gpio = BIT(pin % bank->chip.gc.ngpio); 1749 1754 1750 - dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin); 1755 + dev_dbg(bank->chip.gc.parent, "param=%d %d[GPIO]\n", param, pin); 1751 1756 switch (param) { 1752 1757 case PIN_CONFIG_BIAS_DISABLE: 1753 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); 1754 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); 1758 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); 1759 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); 1755 1760 break; 1756 1761 case PIN_CONFIG_BIAS_PULL_DOWN: 1757 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); 1758 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); 1762 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); 1763 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); 1759 1764 break; 1760 1765 case PIN_CONFIG_BIAS_PULL_UP: 1761 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); 1762 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); 1766 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); 1767 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); 1763 1768 break; 1764 1769 case PIN_CONFIG_INPUT_ENABLE: 1765 1770 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); 1766 - bank->direction_input(&bank->gc, pin % bank->gc.ngpio); 1771 + bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio); 1767 1772 break; 1768 1773 case PIN_CONFIG_OUTPUT: 1769 - bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); 1774 + bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg); 1770 1775 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); 1771 1776 break; 1772 1777 case PIN_CONFIG_DRIVE_PUSH_PULL: 1773 - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1778 + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1774 1779 break; 1775 1780 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1776 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1781 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1777 1782 break; 1778 1783 case PIN_CONFIG_INPUT_DEBOUNCE: 1779 - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio); 1784 + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_DBNC, gpio); 1780 1785 break; 1781 1786 case PIN_CONFIG_SLEW_RATE: 1782 1787 return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); ··· 1824 1829 1825 1830 static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl) 1826 1831 { 1832 + struct gpio_generic_chip_config config; 1827 1833 int ret = -ENXIO; 1828 1834 struct device *dev = pctrl->dev; 1829 1835 struct fwnode_reference_args args; ··· 1836 1840 if (!pctrl->gpio_bank[id].base) 1837 1841 return -EINVAL; 1838 1842 1839 - ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, 1840 - pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN, 1841 - pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT, 1842 - NULL, 1843 - NULL, 1844 - pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM, 1845 - BGPIOF_READ_OUTPUT_REG_SET); 1843 + config = (typeof(config)){ 1844 + .dev = dev, 1845 + .sz = 4, 1846 + .dat = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN, 1847 + .set = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT, 1848 + .dirin = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM, 1849 + .flags = BGPIOF_READ_OUTPUT_REG_SET, 1850 + }; 1851 + 1852 + ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config); 1846 1853 if (ret) { 1847 - dev_err(dev, "bgpio_init() failed\n"); 1854 + dev_err(dev, "failed to initialize the generic GPIO chip\n"); 1848 1855 return ret; 1849 1856 } 1850 1857 ··· 1865 1866 pctrl->gpio_bank[id].irq = ret; 1866 1867 pctrl->gpio_bank[id].irqbase = id * NPCM7XX_GPIO_PER_BANK; 1867 1868 pctrl->gpio_bank[id].pinctrl_id = args.args[0]; 1868 - pctrl->gpio_bank[id].gc.base = args.args[1]; 1869 - pctrl->gpio_bank[id].gc.ngpio = args.args[2]; 1870 - pctrl->gpio_bank[id].gc.owner = THIS_MODULE; 1871 - pctrl->gpio_bank[id].gc.parent = dev; 1872 - pctrl->gpio_bank[id].gc.fwnode = child; 1873 - pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); 1874 - if (pctrl->gpio_bank[id].gc.label == NULL) 1869 + pctrl->gpio_bank[id].chip.gc.base = args.args[1]; 1870 + pctrl->gpio_bank[id].chip.gc.ngpio = args.args[2]; 1871 + pctrl->gpio_bank[id].chip.gc.owner = THIS_MODULE; 1872 + pctrl->gpio_bank[id].chip.gc.parent = dev; 1873 + pctrl->gpio_bank[id].chip.gc.fwnode = child; 1874 + pctrl->gpio_bank[id].chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); 1875 + if (pctrl->gpio_bank[id].chip.gc.label == NULL) 1875 1876 return -ENOMEM; 1876 1877 1877 - pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; 1878 - pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input; 1879 - pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input; 1880 - pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output; 1881 - pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output; 1882 - pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request; 1883 - pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; 1884 - pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free; 1878 + pctrl->gpio_bank[id].chip.gc.dbg_show = npcmgpio_dbg_show; 1879 + pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].chip.gc.direction_input; 1880 + pctrl->gpio_bank[id].chip.gc.direction_input = npcmgpio_direction_input; 1881 + pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].chip.gc.direction_output; 1882 + pctrl->gpio_bank[id].chip.gc.direction_output = npcmgpio_direction_output; 1883 + pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].chip.gc.request; 1884 + pctrl->gpio_bank[id].chip.gc.request = npcmgpio_gpio_request; 1885 + pctrl->gpio_bank[id].chip.gc.free = pinctrl_gpio_free; 1885 1886 id++; 1886 1887 } 1887 1888 ··· 1896 1897 for (id = 0 ; id < pctrl->bank_num ; id++) { 1897 1898 struct gpio_irq_chip *girq; 1898 1899 1899 - girq = &pctrl->gpio_bank[id].gc.irq; 1900 + girq = &pctrl->gpio_bank[id].chip.gc.irq; 1900 1901 gpio_irq_chip_set_chip(girq, &npcmgpio_irqchip); 1901 1902 girq->parent_handler = npcmgpio_irq_handler; 1902 1903 girq->num_parents = 1; ··· 1911 1912 girq->default_type = IRQ_TYPE_NONE; 1912 1913 girq->handler = handle_level_irq; 1913 1914 ret = devm_gpiochip_add_data(pctrl->dev, 1914 - &pctrl->gpio_bank[id].gc, 1915 + &pctrl->gpio_bank[id].chip.gc, 1915 1916 &pctrl->gpio_bank[id]); 1916 1917 if (ret) { 1917 1918 dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id); 1918 1919 goto err_register; 1919 1920 } 1920 1921 1921 - ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc, 1922 + ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].chip.gc, 1922 1923 dev_name(pctrl->dev), 1923 1924 pctrl->gpio_bank[id].pinctrl_id, 1924 - pctrl->gpio_bank[id].gc.base, 1925 - pctrl->gpio_bank[id].gc.ngpio); 1925 + pctrl->gpio_bank[id].chip.gc.base, 1926 + pctrl->gpio_bank[id].chip.gc.ngpio); 1926 1927 if (ret < 0) { 1927 1928 dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id); 1928 - gpiochip_remove(&pctrl->gpio_bank[id].gc); 1929 + gpiochip_remove(&pctrl->gpio_bank[id].chip.gc); 1929 1930 goto err_register; 1930 1931 } 1931 1932 } ··· 1934 1935 1935 1936 err_register: 1936 1937 for (; id > 0; id--) 1937 - gpiochip_remove(&pctrl->gpio_bank[id - 1].gc); 1938 + gpiochip_remove(&pctrl->gpio_bank[id - 1].chip.gc); 1938 1939 1939 1940 return ret; 1940 1941 }

+78 -76

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

··· 4 4 #include <linux/bits.h> 5 5 #include <linux/device.h> 6 6 #include <linux/gpio/driver.h> 7 + #include <linux/gpio/generic.h> 7 8 #include <linux/interrupt.h> 8 9 #include <linux/irq.h> 9 10 #include <linux/mfd/syscon.h> ··· 91 90 }; 92 91 93 92 struct npcm8xx_gpio { 94 - struct gpio_chip gc; 93 + struct gpio_generic_chip chip; 95 94 void __iomem *base; 96 95 struct debounce_time debounce; 97 96 int irqbase; ··· 116 115 }; 117 116 118 117 /* GPIO handling in the pinctrl driver */ 119 - static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg, 118 + static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *reg, 120 119 unsigned int pinmask) 121 120 { 122 - unsigned long flags; 121 + guard(gpio_generic_lock_irqsave)(chip); 123 122 124 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 125 123 iowrite32(ioread32(reg) | pinmask, reg); 126 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 127 124 } 128 125 129 - static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, 126 + static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *reg, 130 127 unsigned int pinmask) 131 128 { 132 - unsigned long flags; 129 + guard(gpio_generic_lock_irqsave)(chip); 133 130 134 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 135 131 iowrite32(ioread32(reg) & ~pinmask, reg); 136 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 137 132 } 138 133 139 134 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) ··· 230 233 231 234 switch (type) { 232 235 case IRQ_TYPE_EDGE_RISING: 233 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); 234 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 236 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio); 237 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); 235 238 break; 236 239 case IRQ_TYPE_EDGE_FALLING: 237 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); 238 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 240 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio); 241 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); 239 242 break; 240 243 case IRQ_TYPE_EDGE_BOTH: 241 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 242 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); 244 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); 245 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio); 243 246 break; 244 247 case IRQ_TYPE_LEVEL_LOW: 245 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 248 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); 246 249 break; 247 250 case IRQ_TYPE_LEVEL_HIGH: 248 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); 251 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); 249 252 break; 250 253 default: 251 254 return -EINVAL; 252 255 } 253 256 254 257 if (type & IRQ_TYPE_LEVEL_MASK) { 255 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); 258 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio); 256 259 irq_set_handler_locked(d, handle_level_irq); 257 260 } else if (type & IRQ_TYPE_EDGE_BOTH) { 258 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); 261 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio); 259 262 irq_set_handler_locked(d, handle_edge_irq); 260 263 } 261 264 ··· 1839 1842 static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank, 1840 1843 struct regmap *gcr_regmap, unsigned int pin) 1841 1844 { 1842 - int gpio = pin % bank->gc.ngpio; 1845 + int gpio = pin % bank->chip.gc.ngpio; 1843 1846 unsigned long pinmask = BIT(gpio); 1844 1847 u32 val; 1845 1848 ··· 1859 1862 int arg) 1860 1863 { 1861 1864 void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC; 1862 - int gpio = BIT(pin % bank->gc.ngpio); 1865 + int gpio = BIT(pin % bank->chip.gc.ngpio); 1863 1866 1864 1867 if (pincfg[pin].flag & SLEW) { 1865 1868 switch (arg) { 1866 1869 case 0: 1867 - npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio); 1870 + npcm_gpio_clr(&bank->chip, OSRC_Offset, gpio); 1868 1871 return 0; 1869 1872 case 1: 1870 - npcm_gpio_set(&bank->gc, OSRC_Offset, gpio); 1873 + npcm_gpio_set(&bank->chip, OSRC_Offset, gpio); 1871 1874 return 0; 1872 1875 default: 1873 1876 return -EINVAL; ··· 1899 1902 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1900 1903 struct npcm8xx_gpio *bank = 1901 1904 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 1902 - int gpio = pin % bank->gc.ngpio; 1905 + int gpio = pin % bank->chip.gc.ngpio; 1903 1906 unsigned long pinmask = BIT(gpio); 1904 1907 int flg, val; 1905 1908 u32 ds = 0; ··· 1910 1913 1911 1914 val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask; 1912 1915 ds = val ? DSHI(flg) : DSLO(flg); 1913 - dev_dbg(bank->gc.parent, "pin %d strength %d = %d\n", pin, val, ds); 1916 + dev_dbg(bank->chip.gc.parent, "pin %d strength %d = %d\n", pin, val, ds); 1914 1917 1915 1918 return ds; 1916 1919 } ··· 1920 1923 { 1921 1924 struct npcm8xx_gpio *bank = 1922 1925 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 1923 - int gpio = BIT(pin % bank->gc.ngpio); 1926 + int gpio = BIT(pin % bank->chip.gc.ngpio); 1924 1927 int v; 1925 1928 1926 1929 v = pincfg[pin].flag & DRIVE_STRENGTH_MASK; 1927 1930 1928 1931 if (DSLO(v) == nval) 1929 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); 1932 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio); 1930 1933 else if (DSHI(v) == nval) 1931 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); 1934 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio); 1932 1935 else 1933 1936 return -ENOTSUPP; 1934 1937 ··· 2051 2054 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 2052 2055 struct npcm8xx_gpio *bank = 2053 2056 &npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK]; 2054 - int gpio = BIT(offset % bank->gc.ngpio); 2057 + int gpio = BIT(offset % bank->chip.gc.ngpio); 2055 2058 2056 2059 if (input) 2057 2060 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); ··· 2082 2085 if (bank->debounce.set_val[i]) { 2083 2086 if (bank->debounce.nanosec_val[i] == nanosecs) { 2084 2087 debounce_select = i << gpio_debounce; 2085 - npcm_gpio_set(&bank->gc, DBNCS_offset, 2088 + npcm_gpio_set(&bank->chip, DBNCS_offset, 2086 2089 debounce_select); 2087 2090 break; 2088 2091 } ··· 2090 2093 bank->debounce.set_val[i] = true; 2091 2094 bank->debounce.nanosec_val[i] = nanosecs; 2092 2095 debounce_select = i << gpio_debounce; 2093 - npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select); 2096 + npcm_gpio_set(&bank->chip, DBNCS_offset, debounce_select); 2094 2097 switch (nanosecs) { 2095 2098 case 1 ... 1040: 2096 2099 iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); ··· 2142 2145 { 2143 2146 struct npcm8xx_gpio *bank = 2144 2147 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 2145 - int gpio = BIT(pin % bank->gc.ngpio); 2148 + int gpio = BIT(pin % bank->chip.gc.ngpio); 2146 2149 int ret; 2147 2150 2148 2151 if (nanosecs) { 2149 - ret = debounce_timing_setting(bank, pin % bank->gc.ngpio, 2152 + ret = debounce_timing_setting(bank, pin % bank->chip.gc.ngpio, 2150 2153 nanosecs); 2151 2154 if (ret) 2152 2155 dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debounce values\n", pin); 2153 2156 else 2154 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, 2157 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC, 2155 2158 gpio); 2156 2159 return ret; 2157 2160 } 2158 2161 2159 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio); 2162 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC, gpio); 2160 2163 2161 2164 return 0; 2162 2165 } ··· 2169 2172 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 2170 2173 struct npcm8xx_gpio *bank = 2171 2174 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 2172 - int gpio = pin % bank->gc.ngpio; 2175 + int gpio = pin % bank->chip.gc.ngpio; 2173 2176 unsigned long pinmask = BIT(gpio); 2174 2177 u32 ie, oe, pu, pd; 2175 2178 int rc = 0; ··· 2232 2235 struct npcm8xx_gpio *bank = 2233 2236 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; 2234 2237 u32 arg = pinconf_to_config_argument(config); 2235 - int gpio = BIT(pin % bank->gc.ngpio); 2238 + int gpio = BIT(pin % bank->chip.gc.ngpio); 2236 2239 2237 2240 switch (param) { 2238 2241 case PIN_CONFIG_BIAS_DISABLE: 2239 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); 2240 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); 2242 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio); 2243 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio); 2241 2244 break; 2242 2245 case PIN_CONFIG_BIAS_PULL_DOWN: 2243 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); 2244 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); 2246 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio); 2247 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio); 2245 2248 break; 2246 2249 case PIN_CONFIG_BIAS_PULL_UP: 2247 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); 2248 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); 2250 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio); 2251 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio); 2249 2252 break; 2250 2253 case PIN_CONFIG_INPUT_ENABLE: 2251 2254 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); 2252 - bank->direction_input(&bank->gc, pin % bank->gc.ngpio); 2255 + bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio); 2253 2256 break; 2254 2257 case PIN_CONFIG_OUTPUT: 2255 - bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); 2258 + bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg); 2256 2259 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); 2257 2260 break; 2258 2261 case PIN_CONFIG_DRIVE_PUSH_PULL: 2259 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); 2262 + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio); 2260 2263 break; 2261 2264 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 2262 - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); 2265 + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio); 2263 2266 break; 2264 2267 case PIN_CONFIG_INPUT_DEBOUNCE: 2265 2268 return npcm_set_debounce(npcm, pin, arg * 1000); ··· 2310 2313 { 2311 2314 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); 2312 2315 2313 - return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent), 2314 - bank->pinctrl_id, bank->gc.base, 2315 - bank->gc.ngpio); 2316 + return gpiochip_add_pin_range(&bank->chip.gc, dev_name(chip->parent), 2317 + bank->pinctrl_id, bank->chip.gc.base, 2318 + bank->chip.gc.ngpio); 2316 2319 } 2317 2320 2318 2321 static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl) 2319 2322 { 2323 + struct gpio_generic_chip_config config; 2320 2324 struct fwnode_reference_args args; 2321 2325 struct device *dev = pctrl->dev; 2322 2326 struct fwnode_handle *child; ··· 2329 2331 if (!pctrl->gpio_bank[id].base) 2330 2332 return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id); 2331 2333 2332 - ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, 2333 - pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN, 2334 - pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT, 2335 - NULL, 2336 - NULL, 2337 - pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM, 2338 - BGPIOF_READ_OUTPUT_REG_SET); 2334 + config = (typeof(config)){ 2335 + .dev = dev, 2336 + .sz = 4, 2337 + .dat = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN, 2338 + .set = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT, 2339 + .dirin = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM, 2340 + .flags = BGPIOF_READ_OUTPUT_REG_SET, 2341 + }; 2342 + 2343 + ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config); 2339 2344 if (ret) 2340 - return dev_err_probe(dev, ret, "bgpio_init() failed\n"); 2345 + return dev_err_probe(dev, ret, 2346 + "failed to initialize the generic GPIO chip\n"); 2341 2347 2342 2348 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args); 2343 2349 if (ret < 0) ··· 2355 2353 pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; 2356 2354 pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK; 2357 2355 pctrl->gpio_bank[id].pinctrl_id = args.args[0]; 2358 - pctrl->gpio_bank[id].gc.base = -1; 2359 - pctrl->gpio_bank[id].gc.ngpio = args.args[2]; 2360 - pctrl->gpio_bank[id].gc.owner = THIS_MODULE; 2361 - pctrl->gpio_bank[id].gc.parent = dev; 2362 - pctrl->gpio_bank[id].gc.fwnode = child; 2363 - pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); 2364 - if (pctrl->gpio_bank[id].gc.label == NULL) 2356 + pctrl->gpio_bank[id].chip.gc.base = -1; 2357 + pctrl->gpio_bank[id].chip.gc.ngpio = args.args[2]; 2358 + pctrl->gpio_bank[id].chip.gc.owner = THIS_MODULE; 2359 + pctrl->gpio_bank[id].chip.gc.parent = dev; 2360 + pctrl->gpio_bank[id].chip.gc.fwnode = child; 2361 + pctrl->gpio_bank[id].chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); 2362 + if (pctrl->gpio_bank[id].chip.gc.label == NULL) 2365 2363 return -ENOMEM; 2366 2364 2367 - pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; 2368 - pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input; 2369 - pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input; 2370 - pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output; 2371 - pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output; 2372 - pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request; 2373 - pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; 2374 - pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free; 2365 + pctrl->gpio_bank[id].chip.gc.dbg_show = npcmgpio_dbg_show; 2366 + pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].chip.gc.direction_input; 2367 + pctrl->gpio_bank[id].chip.gc.direction_input = npcmgpio_direction_input; 2368 + pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].chip.gc.direction_output; 2369 + pctrl->gpio_bank[id].chip.gc.direction_output = npcmgpio_direction_output; 2370 + pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].chip.gc.request; 2371 + pctrl->gpio_bank[id].chip.gc.request = npcmgpio_gpio_request; 2372 + pctrl->gpio_bank[id].chip.gc.free = pinctrl_gpio_free; 2375 2373 for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) 2376 2374 pctrl->gpio_bank[id].debounce.set_val[i] = false; 2377 - pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges; 2375 + pctrl->gpio_bank[id].chip.gc.add_pin_ranges = npcmgpio_add_pin_ranges; 2378 2376 id++; 2379 2377 } 2380 2378 ··· 2389 2387 for (id = 0 ; id < pctrl->bank_num ; id++) { 2390 2388 struct gpio_irq_chip *girq; 2391 2389 2392 - girq = &pctrl->gpio_bank[id].gc.irq; 2390 + girq = &pctrl->gpio_bank[id].chip.gc.irq; 2393 2391 girq->chip = &pctrl->gpio_bank[id].irq_chip; 2394 2392 girq->parent_handler = npcmgpio_irq_handler; 2395 2393 girq->num_parents = 1; ··· 2403 2401 girq->default_type = IRQ_TYPE_NONE; 2404 2402 girq->handler = handle_level_irq; 2405 2403 ret = devm_gpiochip_add_data(pctrl->dev, 2406 - &pctrl->gpio_bank[id].gc, 2404 + &pctrl->gpio_bank[id].chip.gc, 2407 2405 &pctrl->gpio_bank[id]); 2408 2406 if (ret) 2409 2407 return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id);

+28 -16

drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

··· 11 11 12 12 #include <linux/device.h> 13 13 #include <linux/gpio/driver.h> 14 + #include <linux/gpio/generic.h> 14 15 #include <linux/interrupt.h> 15 16 #include <linux/irq.h> 16 17 #include <linux/mfd/syscon.h> ··· 48 47 struct wpcm450_bank; 49 48 50 49 struct wpcm450_gpio { 51 - struct gpio_chip gc; 50 + struct gpio_generic_chip chip; 52 51 struct wpcm450_pinctrl *pctrl; 53 52 const struct wpcm450_bank *bank; 54 53 }; ··· 185 184 } 186 185 187 186 /* 188 - * This is an implementation of the gpio_chip->get() function, for use in 189 - * wpcm450_gpio_fix_evpol. Unfortunately, we can't use the bgpio-provided 190 - * implementation there, because it would require taking gpio_chip->bgpio_lock, 191 - * which is a spin lock, but wpcm450_gpio_fix_evpol must work in contexts where 192 - * a raw spin lock is held. 187 + * FIXME: This is an implementation of the gpio_chip->get() function, for use 188 + * in wpcm450_gpio_fix_evpol(). It was implemented back when gpio-mmio used a 189 + * regular spinlock internally, while wpcm450_gpio_fix_evpol() needed to work 190 + * in contexts with a raw spinlock held. Since then, the gpio generic chip has 191 + * been switched to using a raw spinlock so this should be converted to using 192 + * the locking interfaces provided in linux/gpio/gneneric.h. 193 193 */ 194 194 static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset) 195 195 { ··· 331 329 for_each_set_bit(bit, &pending, 32) { 332 330 int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit); 333 331 334 - generic_handle_domain_irq(gpio->gc.irq.domain, offset); 332 + generic_handle_domain_irq(gpio->chip.gc.irq.domain, offset); 335 333 } 336 334 chained_irq_exit(chip, desc); 337 335 } ··· 1014 1012 struct wpcm450_gpio *gpio = gpiochip_get_data(chip); 1015 1013 const struct wpcm450_bank *bank = gpio->bank; 1016 1014 1017 - return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev), 1015 + return gpiochip_add_pin_range(&gpio->chip.gc, dev_name(gpio->pctrl->dev), 1018 1016 0, bank->base, bank->length); 1019 1017 } 1020 1018 ··· 1031 1029 "Resource fail for GPIO controller\n"); 1032 1030 1033 1031 for_each_gpiochip_node(dev, child) { 1032 + struct gpio_generic_chip_config config; 1034 1033 void __iomem *dat = NULL; 1035 1034 void __iomem *set = NULL; 1036 1035 void __iomem *dirout = NULL; ··· 1063 1060 } else { 1064 1061 flags = BGPIOF_NO_OUTPUT; 1065 1062 } 1066 - ret = bgpio_init(&gpio->gc, dev, 4, 1067 - dat, set, NULL, dirout, NULL, flags); 1063 + 1064 + config = (typeof(config)){ 1065 + .dev = dev, 1066 + .sz = 4, 1067 + .dat = dat, 1068 + .set = set, 1069 + .dirout = dirout, 1070 + .flags = flags, 1071 + }; 1072 + 1073 + ret = gpio_generic_chip_init(&gpio->chip, &config); 1068 1074 if (ret < 0) 1069 1075 return dev_err_probe(dev, ret, "GPIO initialization failed\n"); 1070 1076 1071 - gpio->gc.ngpio = bank->length; 1072 - gpio->gc.set_config = wpcm450_gpio_set_config; 1073 - gpio->gc.fwnode = child; 1074 - gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges; 1077 + gpio->chip.gc.ngpio = bank->length; 1078 + gpio->chip.gc.set_config = wpcm450_gpio_set_config; 1079 + gpio->chip.gc.fwnode = child; 1080 + gpio->chip.gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges; 1075 1081 1076 - girq = &gpio->gc.irq; 1082 + girq = &gpio->chip.gc.irq; 1077 1083 gpio_irq_chip_set_chip(girq, &wpcm450_gpio_irqchip); 1078 1084 girq->parent_handler = wpcm450_gpio_irqhandler; 1079 1085 girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS, ··· 1106 1094 girq->num_parents++; 1107 1095 } 1108 1096 1109 - ret = devm_gpiochip_add_data(dev, &gpio->gc, gpio); 1097 + ret = devm_gpiochip_add_data(dev, &gpio->chip.gc, gpio); 1110 1098 if (ret) 1111 1099 return dev_err_probe(dev, ret, "Failed to add GPIO chip\n"); 1112 1100 }

+16 -10

drivers/pinctrl/pinctrl-equilibrium.c

··· 2 2 /* Copyright (C) 2019 Intel Corporation */ 3 3 4 4 #include <linux/gpio/driver.h> 5 + #include <linux/gpio/generic.h> 5 6 #include <linux/module.h> 6 7 #include <linux/of.h> 7 8 #include <linux/of_address.h> ··· 180 179 struct gpio_irq_chip *girq; 181 180 struct gpio_chip *gc; 182 181 183 - gc = &gctrl->chip; 182 + gc = &gctrl->chip.gc; 184 183 gc->label = gctrl->name; 185 184 gc->fwnode = gctrl->fwnode; 186 185 gc->request = gpiochip_generic_request; ··· 192 191 return 0; 193 192 } 194 193 195 - girq = &gctrl->chip.irq; 194 + girq = &gctrl->chip.gc.irq; 196 195 gpio_irq_chip_set_chip(girq, &eqbr_irq_chip); 197 196 girq->parent_handler = eqbr_irq_handler; 198 197 girq->num_parents = 1; ··· 209 208 210 209 static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata) 211 210 { 211 + struct gpio_generic_chip_config config; 212 212 struct device *dev = drvdata->dev; 213 213 struct eqbr_gpio_ctrl *gctrl; 214 214 struct device_node *np; ··· 241 239 } 242 240 raw_spin_lock_init(&gctrl->lock); 243 241 244 - ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8, 245 - gctrl->membase + GPIO_IN, 246 - gctrl->membase + GPIO_OUTSET, 247 - gctrl->membase + GPIO_OUTCLR, 248 - gctrl->membase + GPIO_DIR, 249 - NULL, 0); 242 + config = (typeof(config)){ 243 + .dev = dev, 244 + .sz = gctrl->bank->nr_pins / 8, 245 + .dat = gctrl->membase + GPIO_IN, 246 + .set = gctrl->membase + GPIO_OUTSET, 247 + .clr = gctrl->membase + GPIO_OUTCLR, 248 + .dirout = gctrl->membase + GPIO_DIR, 249 + }; 250 + 251 + ret = gpio_generic_chip_init(&gctrl->chip, &config); 250 252 if (ret) { 251 253 dev_err(dev, "unable to init generic GPIO\n"); 252 254 return ret; ··· 260 254 if (ret) 261 255 return ret; 262 256 263 - ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl); 257 + ret = devm_gpiochip_add_data(dev, &gctrl->chip.gc, gctrl); 264 258 if (ret) 265 259 return ret; 266 260 } ··· 505 499 bank->pin_base, pin); 506 500 return -ENODEV; 507 501 } 508 - gc = &gctrl->chip; 502 + gc = &gctrl->chip.gc; 509 503 gc->direction_output(gc, offset, 0); 510 504 continue; 511 505 default:

+1 -1

drivers/pinctrl/pinctrl-equilibrium.h

··· 96 96 * @lock: spin lock to protect gpio register write. 97 97 */ 98 98 struct eqbr_gpio_ctrl { 99 - struct gpio_chip chip; 99 + struct gpio_generic_chip chip; 100 100 struct fwnode_handle *fwnode; 101 101 struct eqbr_pin_bank *bank; 102 102 void __iomem *membase;

+19 -13

drivers/pinctrl/stm32/pinctrl-stm32-hdp.c

··· 6 6 #include <linux/bits.h> 7 7 #include <linux/clk.h> 8 8 #include <linux/gpio/driver.h> 9 + #include <linux/gpio/generic.h> 9 10 #include <linux/io.h> 10 11 #include <linux/of.h> 11 12 #include <linux/of_device.h> ··· 46 45 void __iomem *base; 47 46 struct clk *clk; 48 47 struct pinctrl_dev *pctl_dev; 49 - struct gpio_chip gpio_chip; 48 + struct gpio_generic_chip gpio_chip; 50 49 u32 mux_conf; 51 50 u32 gposet_conf; 52 51 const char * const *func_name; ··· 604 603 605 604 static int stm32_hdp_probe(struct platform_device *pdev) 606 605 { 606 + struct gpio_generic_chip_config config; 607 607 struct device *dev = &pdev->dev; 608 608 struct stm32_hdp *hdp; 609 609 u8 version; ··· 637 635 if (err) 638 636 return dev_err_probe(dev, err, "Failed to enable pinctrl\n"); 639 637 640 - hdp->gpio_chip.get_direction = stm32_hdp_gpio_get_direction; 641 - hdp->gpio_chip.ngpio = ARRAY_SIZE(stm32_hdp_pins); 642 - hdp->gpio_chip.can_sleep = true; 643 - hdp->gpio_chip.names = stm32_hdp_pins_group; 638 + hdp->gpio_chip.gc.get_direction = stm32_hdp_gpio_get_direction; 639 + hdp->gpio_chip.gc.ngpio = ARRAY_SIZE(stm32_hdp_pins); 640 + hdp->gpio_chip.gc.can_sleep = true; 641 + hdp->gpio_chip.gc.names = stm32_hdp_pins_group; 644 642 645 - err = bgpio_init(&hdp->gpio_chip, dev, 4, 646 - hdp->base + HDP_GPOVAL, 647 - hdp->base + HDP_GPOSET, 648 - hdp->base + HDP_GPOCLR, 649 - NULL, NULL, BGPIOF_NO_INPUT); 643 + config = (typeof(config)){ 644 + .dev = dev, 645 + .sz = 4, 646 + .dat = hdp->base + HDP_GPOVAL, 647 + .set = hdp->base + HDP_GPOSET, 648 + .clr = hdp->base + HDP_GPOCLR, 649 + .flags = BGPIOF_NO_INPUT, 650 + }; 651 + 652 + err = gpio_generic_chip_init(&hdp->gpio_chip, &config); 650 653 if (err) 651 - return dev_err_probe(dev, err, "Failed to init bgpio\n"); 654 + return dev_err_probe(dev, err, "Failed to init the generic GPIO chip\n"); 652 655 653 - 654 - err = devm_gpiochip_add_data(dev, &hdp->gpio_chip, hdp); 656 + err = devm_gpiochip_add_data(dev, &hdp->gpio_chip.gc, hdp); 655 657 if (err) 656 658 return dev_err_probe(dev, err, "Failed to add gpiochip\n"); 657 659