cxl: Increase timeout for detection of AFU mmio hang

PSL designers recommend a larger value for the mmio hang pulse, 256 us
instead of 1 us. The CAIA architecture states that it needs to be
smaller than 1/2 of the RTOS timeout set in the PHB for outbound
non-posted transactions, which is still (easily) the case here.

Signed-off-by: Frederic Barrat <[e-mail]>
Acked-by: Ian Munsie <[e-mail]>
Tested-by: Frank Haverkamp <[e-mail]>
Tested-by: Manoj Kumar <[e-mail]>
Signed-off-by: Michael Ellerman <[e-mail]>

drivers/misc/cxl/pci.c

···
 		return -ENODEV;
 	}
 
+	psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
+	psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
 	/* Tell PSL where to route data to */
-	psl_dsnctl = 0x0000900002000000ULL | (chipid << (63-5));
+	psl_dsnctl |= (chipid << (63-5));
 	psl_dsnctl |= (capp_unit_id << (63-13));
 
 	cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);