[PATCH] ARM: 2677/1: S3C2440 - UPLL frequency doubled

Patch from Ben Dooks

S3C2440 UPLL is the same as the S3C2410 UPLL, it is only the
MPLL which has an extra multiplication factor of 2 in the
multiplier.

Signed-off-by: Ben Dooks
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

authored by

Ben Dooks and committed by
Russell King
4ad3a443 9dabf9da

+1 -1
+1 -1
arch/arm/mach-s3c2410/clock.c
··· 478 { 479 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); 480 481 - s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate) * 2; 482 483 printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n", 484 print_mhz(s3c2440_clk_upll.rate));
··· 478 { 479 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); 480 481 + s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate); 482 483 printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n", 484 print_mhz(s3c2440_clk_upll.rate));