ARM: Fix wrong register in proc-arm6_7.S data abort handler

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

+1 -1
+1 -1
arch/arm/mm/proc-arm6_7.S
··· 41 ENTRY(cpu_arm7_data_abort) 42 mrc p15, 0, r1, c5, c0, 0 @ get FSR 43 mrc p15, 0, r0, c6, c0, 0 @ get FAR 44 - ldr r8, [r0] @ read arm instruction 45 tst r8, #1 << 20 @ L = 0 -> write? 46 orreq r1, r1, #1 << 11 @ yes. 47 and r7, r8, #15 << 24
··· 41 ENTRY(cpu_arm7_data_abort) 42 mrc p15, 0, r1, c5, c0, 0 @ get FSR 43 mrc p15, 0, r0, c6, c0, 0 @ get FAR 44 + ldr r8, [r2] @ read arm instruction 45 tst r8, #1 << 20 @ L = 0 -> write? 46 orreq r1, r1, #1 << 11 @ yes. 47 and r7, r8, #15 << 24