tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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big-endian support for via-velocity

* kill bitfields
* annotate
* add missing conversions
* fix a couple of brainos in zerocopy stuff (fortunately, it's ifdef'ed out)

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Al Viro and committed by
David S. Miller 4a51c0d0 ad84243e

+129 -167
+32 -38
drivers/net/via-velocity.c
··· 8 8 * for 64bit hardware platforms. 9 9 * 10 10 * TODO 11 - * Big-endian support 12 11 * rx_copybreak/alignment 13 12 * Scatter gather 14 13 * More testing ··· 680 681 * Init state, all RD entries belong to the NIC 681 682 */ 682 683 for (i = 0; i < vptr->options.numrx; ++i) 683 - vptr->rd_ring[i].rdesc0.owner = OWNED_BY_NIC; 684 + vptr->rd_ring[i].rdesc0.len |= OWNED_BY_NIC; 684 685 685 686 writew(vptr->options.numrx, &regs->RBRDU); 686 687 writel(vptr->rd_pool_dma, &regs->RDBaseLo); ··· 776 777 777 778 vptr->int_mask = INT_MASK_DEF; 778 779 779 - writel(cpu_to_le32(vptr->rd_pool_dma), &regs->RDBaseLo); 780 + writel(vptr->rd_pool_dma, &regs->RDBaseLo); 780 781 writew(vptr->options.numrx - 1, &regs->RDCSize); 781 782 mac_rx_queue_run(regs); 782 783 mac_rx_queue_wake(regs); ··· 784 785 writew(vptr->options.numtx - 1, &regs->TDCSize); 785 786 786 787 for (i = 0; i < vptr->num_txq; i++) { 787 - writel(cpu_to_le32(vptr->td_pool_dma[i]), &(regs->TDBaseLo[i])); 788 + writel(vptr->td_pool_dma[i], &regs->TDBaseLo[i]); 788 789 mac_tx_queue_run(regs, i); 789 790 } 790 791 ··· 1194 1195 dirty = vptr->rd_dirty - unusable; 1195 1196 for (avail = vptr->rd_filled & 0xfffc; avail; avail--) { 1196 1197 dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1; 1197 - vptr->rd_ring[dirty].rdesc0.owner = OWNED_BY_NIC; 1198 + vptr->rd_ring[dirty].rdesc0.len |= OWNED_BY_NIC; 1198 1199 } 1199 1200 1200 1201 writew(vptr->rd_filled & 0xfffc, &regs->RBRDU); ··· 1209 1210 struct rx_desc *rd = vptr->rd_ring + dirty; 1210 1211 1211 1212 /* Fine for an all zero Rx desc at init time as well */ 1212 - if (rd->rdesc0.owner == OWNED_BY_NIC) 1213 + if (rd->rdesc0.len & OWNED_BY_NIC) 1213 1214 break; 1214 1215 1215 1216 if (!vptr->rd_info[dirty].skb) { ··· 1412 1413 if (!vptr->rd_info[rd_curr].skb) 1413 1414 break; 1414 1415 1415 - if (rd->rdesc0.owner == OWNED_BY_NIC) 1416 + if (rd->rdesc0.len & OWNED_BY_NIC) 1416 1417 break; 1417 1418 1418 1419 rmb(); ··· 1420 1421 /* 1421 1422 * Don't drop CE or RL error frame although RXOK is off 1422 1423 */ 1423 - if ((rd->rdesc0.RSR & RSR_RXOK) || (!(rd->rdesc0.RSR & RSR_RXOK) && (rd->rdesc0.RSR & (RSR_CE | RSR_RL)))) { 1424 + if (rd->rdesc0.RSR & (RSR_RXOK | RSR_CE | RSR_RL)) { 1424 1425 if (velocity_receive_frame(vptr, rd_curr) < 0) 1425 1426 stats->rx_dropped++; 1426 1427 } else { ··· 1432 1433 stats->rx_dropped++; 1433 1434 } 1434 1435 1435 - rd->inten = 1; 1436 + rd->size |= RX_INTEN; 1436 1437 1437 1438 vptr->dev->last_rx = jiffies; 1438 1439 ··· 1553 1554 struct net_device_stats *stats = &vptr->stats; 1554 1555 struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]); 1555 1556 struct rx_desc *rd = &(vptr->rd_ring[idx]); 1556 - int pkt_len = rd->rdesc0.len; 1557 + int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff; 1557 1558 struct sk_buff *skb; 1558 1559 1559 1560 if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) { ··· 1636 1637 */ 1637 1638 1638 1639 *((u32 *) & (rd->rdesc0)) = 0; 1639 - rd->len = cpu_to_le32(vptr->rx_buf_sz); 1640 - rd->inten = 1; 1640 + rd->size = cpu_to_le16(vptr->rx_buf_sz) | RX_INTEN; 1641 1641 rd->pa_low = cpu_to_le32(rd_info->skb_dma); 1642 1642 rd->pa_high = 0; 1643 1643 return 0; ··· 1672 1674 td = &(vptr->td_rings[qnum][idx]); 1673 1675 tdinfo = &(vptr->td_infos[qnum][idx]); 1674 1676 1675 - if (td->tdesc0.owner == OWNED_BY_NIC) 1677 + if (td->tdesc0.len & OWNED_BY_NIC) 1676 1678 break; 1677 1679 1678 1680 if ((works++ > 15)) ··· 1872 1874 1873 1875 for (i = 0; i < tdinfo->nskb_dma; i++) { 1874 1876 #ifdef VELOCITY_ZERO_COPY_SUPPORT 1875 - pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], td->tdesc1.len, PCI_DMA_TODEVICE); 1877 + pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], le16_to_cpu(td->tdesc1.len), PCI_DMA_TODEVICE); 1876 1878 #else 1877 1879 pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], skb->len, PCI_DMA_TODEVICE); 1878 1880 #endif ··· 2065 2067 struct velocity_td_info *tdinfo; 2066 2068 unsigned long flags; 2067 2069 int index; 2068 - 2069 2070 int pktlen = skb->len; 2071 + __le16 len = cpu_to_le16(pktlen); 2070 2072 2071 2073 #ifdef VELOCITY_ZERO_COPY_SUPPORT 2072 2074 if (skb_shinfo(skb)->nr_frags > 6 && __skb_linearize(skb)) { ··· 2081 2083 td_ptr = &(vptr->td_rings[qnum][index]); 2082 2084 tdinfo = &(vptr->td_infos[qnum][index]); 2083 2085 2084 - td_ptr->tdesc1.TCPLS = TCPLS_NORMAL; 2085 2086 td_ptr->tdesc1.TCR = TCR0_TIC; 2086 - td_ptr->td_buf[0].queue = 0; 2087 + td_ptr->td_buf[0].size &= ~TD_QUEUE; 2087 2088 2088 2089 /* 2089 2090 * Pad short frames. ··· 2090 2093 if (pktlen < ETH_ZLEN) { 2091 2094 /* Cannot occur until ZC support */ 2092 2095 pktlen = ETH_ZLEN; 2096 + len = cpu_to_le16(ETH_ZLEN); 2093 2097 skb_copy_from_linear_data(skb, tdinfo->buf, skb->len); 2094 2098 memset(tdinfo->buf + skb->len, 0, ETH_ZLEN - skb->len); 2095 2099 tdinfo->skb = skb; 2096 2100 tdinfo->skb_dma[0] = tdinfo->buf_dma; 2097 - td_ptr->tdesc0.pktsize = pktlen; 2101 + td_ptr->tdesc0.len = len; 2098 2102 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]); 2099 2103 td_ptr->td_buf[0].pa_high = 0; 2100 - td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize; 2104 + td_ptr->td_buf[0].size = len; /* queue is 0 anyway */ 2101 2105 tdinfo->nskb_dma = 1; 2102 - td_ptr->tdesc1.CMDZ = 2; 2103 2106 } else 2104 2107 #ifdef VELOCITY_ZERO_COPY_SUPPORT 2105 2108 if (skb_shinfo(skb)->nr_frags > 0) { ··· 2108 2111 if (nfrags > 6) { 2109 2112 skb_copy_from_linear_data(skb, tdinfo->buf, skb->len); 2110 2113 tdinfo->skb_dma[0] = tdinfo->buf_dma; 2111 - td_ptr->tdesc0.pktsize = 2114 + td_ptr->tdesc0.len = len; 2112 2115 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]); 2113 2116 td_ptr->td_buf[0].pa_high = 0; 2114 - td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize; 2117 + td_ptr->td_buf[0].size = len; /* queue is 0 anyway */ 2115 2118 tdinfo->nskb_dma = 1; 2116 - td_ptr->tdesc1.CMDZ = 2; 2117 2119 } else { 2118 2120 int i = 0; 2119 2121 tdinfo->nskb_dma = 0; 2120 - tdinfo->skb_dma[i] = pci_map_single(vptr->pdev, skb->data, skb->len - skb->data_len, PCI_DMA_TODEVICE); 2122 + tdinfo->skb_dma[i] = pci_map_single(vptr->pdev, skb->data, 2123 + skb_headlen(skb), PCI_DMA_TODEVICE); 2121 2124 2122 - td_ptr->tdesc0.pktsize = pktlen; 2125 + td_ptr->tdesc0.len = len; 2123 2126 2124 2127 /* FIXME: support 48bit DMA later */ 2125 2128 td_ptr->td_buf[i].pa_low = cpu_to_le32(tdinfo->skb_dma); 2126 2129 td_ptr->td_buf[i].pa_high = 0; 2127 - td_ptr->td_buf[i].bufsize = skb->len->skb->data_len; 2130 + td_ptr->td_buf[i].size = cpu_to_le16(skb_headlen(skb)); 2128 2131 2129 2132 for (i = 0; i < nfrags; i++) { 2130 2133 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2131 - void *addr = ((void *) page_address(frag->page + frag->page_offset)); 2134 + void *addr = (void *)page_address(frag->page) + frag->page_offset; 2132 2135 2133 2136 tdinfo->skb_dma[i + 1] = pci_map_single(vptr->pdev, addr, frag->size, PCI_DMA_TODEVICE); 2134 2137 2135 2138 td_ptr->td_buf[i + 1].pa_low = cpu_to_le32(tdinfo->skb_dma[i + 1]); 2136 2139 td_ptr->td_buf[i + 1].pa_high = 0; 2137 - td_ptr->td_buf[i + 1].bufsize = frag->size; 2140 + td_ptr->td_buf[i + 1].size = cpu_to_le16(frag->size); 2138 2141 } 2139 2142 tdinfo->nskb_dma = i - 1; 2140 - td_ptr->tdesc1.CMDZ = i; 2141 2143 } 2142 2144 2143 2145 } else ··· 2148 2152 */ 2149 2153 tdinfo->skb = skb; 2150 2154 tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE); 2151 - td_ptr->tdesc0.pktsize = pktlen; 2155 + td_ptr->tdesc0.len = len; 2152 2156 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]); 2153 2157 td_ptr->td_buf[0].pa_high = 0; 2154 - td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize; 2158 + td_ptr->td_buf[0].size = len; 2155 2159 tdinfo->nskb_dma = 1; 2156 - td_ptr->tdesc1.CMDZ = 2; 2157 2160 } 2161 + td_ptr->tdesc1.cmd = TCPLS_NORMAL + (tdinfo->nskb_dma + 1) * 16; 2158 2162 2159 2163 if (vptr->vlgrp && vlan_tx_tag_present(skb)) { 2160 - td_ptr->tdesc1.pqinf.VID = vlan_tx_tag_get(skb); 2161 - td_ptr->tdesc1.pqinf.priority = 0; 2162 - td_ptr->tdesc1.pqinf.CFI = 0; 2164 + td_ptr->tdesc1.vlan = cpu_to_le16(vlan_tx_tag_get(skb)); 2163 2165 td_ptr->tdesc1.TCR |= TCR0_VETAG; 2164 2166 } 2165 2167 ··· 2179 2185 2180 2186 if (prev < 0) 2181 2187 prev = vptr->options.numtx - 1; 2182 - td_ptr->tdesc0.owner = OWNED_BY_NIC; 2188 + td_ptr->tdesc0.len |= OWNED_BY_NIC; 2183 2189 vptr->td_used[qnum]++; 2184 2190 vptr->td_curr[qnum] = (index + 1) % vptr->options.numtx; 2185 2191 ··· 2187 2193 netif_stop_queue(dev); 2188 2194 2189 2195 td_ptr = &(vptr->td_rings[qnum][prev]); 2190 - td_ptr->td_buf[0].queue = 1; 2196 + td_ptr->td_buf[0].size |= TD_QUEUE; 2191 2197 mac_tx_queue_wake(vptr->mac_regs, qnum); 2192 2198 } 2193 2199 dev->trans_start = jiffies; ··· 3404 3410 velocity_save_context(vptr, &vptr->context); 3405 3411 velocity_shutdown(vptr); 3406 3412 velocity_set_wol(vptr); 3407 - pci_enable_wake(pdev, 3, 1); 3413 + pci_enable_wake(pdev, PCI_D3hot, 1); 3408 3414 pci_set_power_state(pdev, PCI_D3hot); 3409 3415 } else { 3410 3416 velocity_save_context(vptr, &vptr->context);
+97 -129
drivers/net/via-velocity.h
··· 70 70 * Bits in the RSR0 register 71 71 */ 72 72 73 - #define RSR_DETAG 0x0080 74 - #define RSR_SNTAG 0x0040 75 - #define RSR_RXER 0x0020 76 - #define RSR_RL 0x0010 77 - #define RSR_CE 0x0008 78 - #define RSR_FAE 0x0004 79 - #define RSR_CRC 0x0002 80 - #define RSR_VIDM 0x0001 73 + #define RSR_DETAG cpu_to_le16(0x0080) 74 + #define RSR_SNTAG cpu_to_le16(0x0040) 75 + #define RSR_RXER cpu_to_le16(0x0020) 76 + #define RSR_RL cpu_to_le16(0x0010) 77 + #define RSR_CE cpu_to_le16(0x0008) 78 + #define RSR_FAE cpu_to_le16(0x0004) 79 + #define RSR_CRC cpu_to_le16(0x0002) 80 + #define RSR_VIDM cpu_to_le16(0x0001) 81 81 82 82 /* 83 83 * Bits in the RSR1 register 84 84 */ 85 85 86 - #define RSR_RXOK 0x8000 // rx OK 87 - #define RSR_PFT 0x4000 // Perfect filtering address match 88 - #define RSR_MAR 0x2000 // MAC accept multicast address packet 89 - #define RSR_BAR 0x1000 // MAC accept broadcast address packet 90 - #define RSR_PHY 0x0800 // MAC accept physical address packet 91 - #define RSR_VTAG 0x0400 // 802.1p/1q tagging packet indicator 92 - #define RSR_STP 0x0200 // start of packet 93 - #define RSR_EDP 0x0100 // end of packet 94 - 95 - /* 96 - * Bits in the RSR1 register 97 - */ 98 - 99 - #define RSR1_RXOK 0x80 // rx OK 100 - #define RSR1_PFT 0x40 // Perfect filtering address match 101 - #define RSR1_MAR 0x20 // MAC accept multicast address packet 102 - #define RSR1_BAR 0x10 // MAC accept broadcast address packet 103 - #define RSR1_PHY 0x08 // MAC accept physical address packet 104 - #define RSR1_VTAG 0x04 // 802.1p/1q tagging packet indicator 105 - #define RSR1_STP 0x02 // start of packet 106 - #define RSR1_EDP 0x01 // end of packet 86 + #define RSR_RXOK cpu_to_le16(0x8000) // rx OK 87 + #define RSR_PFT cpu_to_le16(0x4000) // Perfect filtering address match 88 + #define RSR_MAR cpu_to_le16(0x2000) // MAC accept multicast address packet 89 + #define RSR_BAR cpu_to_le16(0x1000) // MAC accept broadcast address packet 90 + #define RSR_PHY cpu_to_le16(0x0800) // MAC accept physical address packet 91 + #define RSR_VTAG cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator 92 + #define RSR_STP cpu_to_le16(0x0200) // start of packet 93 + #define RSR_EDP cpu_to_le16(0x0100) // end of packet 107 94 108 95 /* 109 96 * Bits in the CSM register ··· 107 120 * Bits in the TSR0 register 108 121 */ 109 122 110 - #define TSR0_ABT 0x0080 // Tx abort because of excessive collision 111 - #define TSR0_OWT 0x0040 // Jumbo frame Tx abort 112 - #define TSR0_OWC 0x0020 // Out of window collision 113 - #define TSR0_COLS 0x0010 // experience collision in this transmit event 114 - #define TSR0_NCR3 0x0008 // collision retry counter[3] 115 - #define TSR0_NCR2 0x0004 // collision retry counter[2] 116 - #define TSR0_NCR1 0x0002 // collision retry counter[1] 117 - #define TSR0_NCR0 0x0001 // collision retry counter[0] 118 - #define TSR0_TERR 0x8000 // 119 - #define TSR0_FDX 0x4000 // current transaction is serviced by full duplex mode 120 - #define TSR0_GMII 0x2000 // current transaction is serviced by GMII mode 121 - #define TSR0_LNKFL 0x1000 // packet serviced during link down 122 - #define TSR0_SHDN 0x0400 // shutdown case 123 - #define TSR0_CRS 0x0200 // carrier sense lost 124 - #define TSR0_CDH 0x0100 // AQE test fail (CD heartbeat) 125 - 126 - /* 127 - * Bits in the TSR1 register 128 - */ 129 - 130 - #define TSR1_TERR 0x80 // 131 - #define TSR1_FDX 0x40 // current transaction is serviced by full duplex mode 132 - #define TSR1_GMII 0x20 // current transaction is serviced by GMII mode 133 - #define TSR1_LNKFL 0x10 // packet serviced during link down 134 - #define TSR1_SHDN 0x04 // shutdown case 135 - #define TSR1_CRS 0x02 // carrier sense lost 136 - #define TSR1_CDH 0x01 // AQE test fail (CD heartbeat) 123 + #define TSR0_ABT cpu_to_le16(0x0080) // Tx abort because of excessive collision 124 + #define TSR0_OWT cpu_to_le16(0x0040) // Jumbo frame Tx abort 125 + #define TSR0_OWC cpu_to_le16(0x0020) // Out of window collision 126 + #define TSR0_COLS cpu_to_le16(0x0010) // experience collision in this transmit event 127 + #define TSR0_NCR3 cpu_to_le16(0x0008) // collision retry counter[3] 128 + #define TSR0_NCR2 cpu_to_le16(0x0004) // collision retry counter[2] 129 + #define TSR0_NCR1 cpu_to_le16(0x0002) // collision retry counter[1] 130 + #define TSR0_NCR0 cpu_to_le16(0x0001) // collision retry counter[0] 131 + #define TSR0_TERR cpu_to_le16(0x8000) // 132 + #define TSR0_FDX cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode 133 + #define TSR0_GMII cpu_to_le16(0x2000) // current transaction is serviced by GMII mode 134 + #define TSR0_LNKFL cpu_to_le16(0x1000) // packet serviced during link down 135 + #define TSR0_SHDN cpu_to_le16(0x0400) // shutdown case 136 + #define TSR0_CRS cpu_to_le16(0x0200) // carrier sense lost 137 + #define TSR0_CDH cpu_to_le16(0x0100) // AQE test fail (CD heartbeat) 137 138 138 139 // 139 140 // Bits in the TCR0 register ··· 172 197 */ 173 198 174 199 struct rdesc0 { 175 - u16 RSR; /* Receive status */ 176 - u16 len:14; /* Received packet length */ 177 - u16 reserved:1; 178 - u16 owner:1; /* Who owns this buffer ? */ 200 + __le16 RSR; /* Receive status */ 201 + __le16 len; /* bits 0--13; bit 15 - owner */ 179 202 }; 180 203 181 204 struct rdesc1 { 182 - u16 PQTAG; 205 + __le16 PQTAG; 183 206 u8 CSM; 184 207 u8 IPKT; 208 + }; 209 + 210 + enum { 211 + RX_INTEN = __constant_cpu_to_le16(0x8000) 185 212 }; 186 213 187 214 struct rx_desc { 188 215 struct rdesc0 rdesc0; 189 216 struct rdesc1 rdesc1; 190 - u32 pa_low; /* Low 32 bit PCI address */ 191 - u16 pa_high; /* Next 16 bit PCI address (48 total) */ 192 - u16 len:15; /* Frame size */ 193 - u16 inten:1; /* Enable interrupt */ 217 + __le32 pa_low; /* Low 32 bit PCI address */ 218 + __le16 pa_high; /* Next 16 bit PCI address (48 total) */ 219 + __le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */ 194 220 } __attribute__ ((__packed__)); 195 221 196 222 /* ··· 199 223 */ 200 224 201 225 struct tdesc0 { 202 - u16 TSR; /* Transmit status register */ 203 - u16 pktsize:14; /* Size of frame */ 204 - u16 reserved:1; 205 - u16 owner:1; /* Who owns the buffer */ 226 + __le16 TSR; /* Transmit status register */ 227 + __le16 len; /* bits 0--13 - size of frame, bit 15 - owner */ 206 228 }; 207 229 208 - struct pqinf { /* Priority queue info */ 209 - u16 VID:12; 210 - u16 CFI:1; 211 - u16 priority:3; 230 + struct tdesc1 { 231 + __le16 vlan; 232 + u8 TCR; 233 + u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */ 212 234 } __attribute__ ((__packed__)); 213 235 214 - struct tdesc1 { 215 - struct pqinf pqinf; 216 - u8 TCR; 217 - u8 TCPLS:2; 218 - u8 reserved:2; 219 - u8 CMDZ:4; 220 - } __attribute__ ((__packed__)); 236 + enum { 237 + TD_QUEUE = __constant_cpu_to_le16(0x8000) 238 + }; 221 239 222 240 struct td_buf { 223 - u32 pa_low; 224 - u16 pa_high; 225 - u16 bufsize:14; 226 - u16 reserved:1; 227 - u16 queue:1; 241 + __le32 pa_low; 242 + __le16 pa_high; 243 + __le16 size; /* bits 0--13 - size, bit 15 - queue */ 228 244 } __attribute__ ((__packed__)); 229 245 230 246 struct tx_desc { ··· 244 276 245 277 enum velocity_owner { 246 278 OWNED_BY_HOST = 0, 247 - OWNED_BY_NIC = 1 279 + OWNED_BY_NIC = __constant_cpu_to_le16(0x8000) 248 280 }; 249 281 250 282 ··· 980 1012 volatile u8 RCR; 981 1013 volatile u8 TCR; 982 1014 983 - volatile u32 CR0Set; /* 0x08 */ 984 - volatile u32 CR0Clr; /* 0x0C */ 1015 + volatile __le32 CR0Set; /* 0x08 */ 1016 + volatile __le32 CR0Clr; /* 0x0C */ 985 1017 986 1018 volatile u8 MARCAM[8]; /* 0x10 */ 987 1019 988 - volatile u32 DecBaseHi; /* 0x18 */ 989 - volatile u16 DbfBaseHi; /* 0x1C */ 990 - volatile u16 reserved_1E; 1020 + volatile __le32 DecBaseHi; /* 0x18 */ 1021 + volatile __le16 DbfBaseHi; /* 0x1C */ 1022 + volatile __le16 reserved_1E; 991 1023 992 - volatile u16 ISRCTL; /* 0x20 */ 1024 + volatile __le16 ISRCTL; /* 0x20 */ 993 1025 volatile u8 TXESR; 994 1026 volatile u8 RXESR; 995 1027 996 - volatile u32 ISR; /* 0x24 */ 997 - volatile u32 IMR; 1028 + volatile __le32 ISR; /* 0x24 */ 1029 + volatile __le32 IMR; 998 1030 999 - volatile u32 TDStatusPort; /* 0x2C */ 1031 + volatile __le32 TDStatusPort; /* 0x2C */ 1000 1032 1001 - volatile u16 TDCSRSet; /* 0x30 */ 1033 + volatile __le16 TDCSRSet; /* 0x30 */ 1002 1034 volatile u8 RDCSRSet; 1003 1035 volatile u8 reserved_33; 1004 - volatile u16 TDCSRClr; 1036 + volatile __le16 TDCSRClr; 1005 1037 volatile u8 RDCSRClr; 1006 1038 volatile u8 reserved_37; 1007 1039 1008 - volatile u32 RDBaseLo; /* 0x38 */ 1009 - volatile u16 RDIdx; /* 0x3C */ 1010 - volatile u16 reserved_3E; 1040 + volatile __le32 RDBaseLo; /* 0x38 */ 1041 + volatile __le16 RDIdx; /* 0x3C */ 1042 + volatile __le16 reserved_3E; 1011 1043 1012 - volatile u32 TDBaseLo[4]; /* 0x40 */ 1044 + volatile __le32 TDBaseLo[4]; /* 0x40 */ 1013 1045 1014 - volatile u16 RDCSize; /* 0x50 */ 1015 - volatile u16 TDCSize; /* 0x52 */ 1016 - volatile u16 TDIdx[4]; /* 0x54 */ 1017 - volatile u16 tx_pause_timer; /* 0x5C */ 1018 - volatile u16 RBRDU; /* 0x5E */ 1046 + volatile __le16 RDCSize; /* 0x50 */ 1047 + volatile __le16 TDCSize; /* 0x52 */ 1048 + volatile __le16 TDIdx[4]; /* 0x54 */ 1049 + volatile __le16 tx_pause_timer; /* 0x5C */ 1050 + volatile __le16 RBRDU; /* 0x5E */ 1019 1051 1020 - volatile u32 FIFOTest0; /* 0x60 */ 1021 - volatile u32 FIFOTest1; /* 0x64 */ 1052 + volatile __le32 FIFOTest0; /* 0x60 */ 1053 + volatile __le32 FIFOTest1; /* 0x64 */ 1022 1054 1023 1055 volatile u8 CAMADDR; /* 0x68 */ 1024 1056 volatile u8 CAMCR; /* 0x69 */ ··· 1031 1063 volatile u8 PHYSR1; 1032 1064 volatile u8 MIICR; 1033 1065 volatile u8 MIIADR; 1034 - volatile u16 MIIDATA; 1066 + volatile __le16 MIIDATA; 1035 1067 1036 - volatile u16 SoftTimer0; /* 0x74 */ 1037 - volatile u16 SoftTimer1; 1068 + volatile __le16 SoftTimer0; /* 0x74 */ 1069 + volatile __le16 SoftTimer1; 1038 1070 1039 1071 volatile u8 CFGA; /* 0x78 */ 1040 1072 volatile u8 CFGB; 1041 1073 volatile u8 CFGC; 1042 1074 volatile u8 CFGD; 1043 1075 1044 - volatile u16 DCFG; /* 0x7C */ 1045 - volatile u16 MCFG; 1076 + volatile __le16 DCFG; /* 0x7C */ 1077 + volatile __le16 MCFG; 1046 1078 1047 1079 volatile u8 TBIST; /* 0x80 */ 1048 1080 volatile u8 RBIST; ··· 1054 1086 volatile u8 rev_id; 1055 1087 volatile u8 PORSTS; 1056 1088 1057 - volatile u32 MIBData; /* 0x88 */ 1089 + volatile __le32 MIBData; /* 0x88 */ 1058 1090 1059 - volatile u16 EEWrData; 1091 + volatile __le16 EEWrData; 1060 1092 1061 1093 volatile u8 reserved_8E; 1062 1094 volatile u8 BPMDWr; ··· 1066 1098 volatile u8 EECHKSUM; /* 0x92 */ 1067 1099 volatile u8 EECSR; 1068 1100 1069 - volatile u16 EERdData; /* 0x94 */ 1101 + volatile __le16 EERdData; /* 0x94 */ 1070 1102 volatile u8 EADDR; 1071 1103 volatile u8 EMBCMD; 1072 1104 ··· 1080 1112 volatile u8 DEBUG; 1081 1113 volatile u8 CHIPGCR; 1082 1114 1083 - volatile u16 WOLCRSet; /* 0xA0 */ 1115 + volatile __le16 WOLCRSet; /* 0xA0 */ 1084 1116 volatile u8 PWCFGSet; 1085 1117 volatile u8 WOLCFGSet; 1086 1118 1087 - volatile u16 WOLCRClr; /* 0xA4 */ 1119 + volatile __le16 WOLCRClr; /* 0xA4 */ 1088 1120 volatile u8 PWCFGCLR; 1089 1121 volatile u8 WOLCFGClr; 1090 1122 1091 - volatile u16 WOLSRSet; /* 0xA8 */ 1092 - volatile u16 reserved_AA; 1123 + volatile __le16 WOLSRSet; /* 0xA8 */ 1124 + volatile __le16 reserved_AA; 1093 1125 1094 - volatile u16 WOLSRClr; /* 0xAC */ 1095 - volatile u16 reserved_AE; 1126 + volatile __le16 WOLSRClr; /* 0xAC */ 1127 + volatile __le16 reserved_AE; 1096 1128 1097 - volatile u16 PatternCRC[8]; /* 0xB0 */ 1098 - volatile u32 ByteMask[4][4]; /* 0xC0 */ 1129 + volatile __le16 PatternCRC[8]; /* 0xB0 */ 1130 + volatile __le32 ByteMask[4][4]; /* 0xC0 */ 1099 1131 } __attribute__ ((__packed__)); 1100 1132 1101 1133 ··· 1206 1238 struct arp_packet { 1207 1239 u8 dest_mac[ETH_ALEN]; 1208 1240 u8 src_mac[ETH_ALEN]; 1209 - u16 type; 1210 - u16 ar_hrd; 1211 - u16 ar_pro; 1241 + __be16 type; 1242 + __be16 ar_hrd; 1243 + __be16 ar_pro; 1212 1244 u8 ar_hln; 1213 1245 u8 ar_pln; 1214 - u16 ar_op; 1246 + __be16 ar_op; 1215 1247 u8 ar_sha[ETH_ALEN]; 1216 1248 u8 ar_sip[4]; 1217 1249 u8 ar_tha[ETH_ALEN]; ··· 1221 1253 struct _magic_packet { 1222 1254 u8 dest_mac[6]; 1223 1255 u8 src_mac[6]; 1224 - u16 type; 1256 + __be16 type; 1225 1257 u8 MAC[16][6]; 1226 1258 u8 password[6]; 1227 1259 } __attribute__ ((__packed__));