clk: make several parent names const · tjh.dev/kernel@4a1caed

tjh.dev / kernel

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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

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clk: make several parent names const

Since commit 2893c379461a ("clk: make strings in parent name arrays
const") the name of parent clocks can be const. So add more const in
several clock drivers.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

authored by

Uwe Kleine-König and committed by

Stephen Boyd 11 years ago 4a1caed3 90acb40f

+154 -146

17 changed files

expand all collapse all

drivers

clk

hisilicon

clk-hi3620.c

clk-hix5hd2.c

clk.h

mxs

clk-imx23.c

clk-imx28.c

clk.h

pxa

clk-pxa.h

rockchip

clk-cpu.c

clk-mmc-phase.c

clk-pll.c

clk.c

clk.h

samsung

clk-pll.c

clk-s5pv210.c

clk.c

clk.h

zynq

clkc.c

+35 -35

drivers/clk/hisilicon/clk-hi3620.c

reviewed

··· 38 38 #include "clk.h" 39 39 40 40 /* clock parent list */ 41 41 - static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", }; 42 42 - static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", }; 43 43 - static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", }; 44 44 - static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", }; 45 45 - static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", }; 46 46 - static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", }; 47 47 - static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", }; 48 48 - static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", }; 49 49 - static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", }; 50 50 - static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", }; 51 51 - static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", }; 52 52 - static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", }; 53 53 - static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", }; 54 54 - static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", }; 55 55 - static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", }; 56 56 - static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", }; 57 57 - static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", }; 58 58 - static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", }; 41 41 + static const char *const timer0_mux_p[] __initconst = { "osc32k", "timerclk01", }; 42 42 + static const char *const timer1_mux_p[] __initconst = { "osc32k", "timerclk01", }; 43 43 + static const char *const timer2_mux_p[] __initconst = { "osc32k", "timerclk23", }; 44 44 + static const char *const timer3_mux_p[] __initconst = { "osc32k", "timerclk23", }; 45 45 + static const char *const timer4_mux_p[] __initconst = { "osc32k", "timerclk45", }; 46 46 + static const char *const timer5_mux_p[] __initconst = { "osc32k", "timerclk45", }; 47 47 + static const char *const timer6_mux_p[] __initconst = { "osc32k", "timerclk67", }; 48 48 + static const char *const timer7_mux_p[] __initconst = { "osc32k", "timerclk67", }; 49 49 + static const char *const timer8_mux_p[] __initconst = { "osc32k", "timerclk89", }; 50 50 + static const char *const timer9_mux_p[] __initconst = { "osc32k", "timerclk89", }; 51 51 + static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", }; 52 52 + static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", }; 53 53 + static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", }; 54 54 + static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", }; 55 55 + static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", }; 56 56 + static const char *const spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; 57 57 + static const char *const spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; 58 58 + static const char *const spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; 59 59 /* share axi parent */ 60 60 - static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", }; 61 61 - static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", }; 62 62 - static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", }; 63 63 - static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", }; 64 64 - static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", }; 65 65 - static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", }; 66 66 - static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", }; 67 67 - static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", }; 68 68 - static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", }; 69 69 - static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", }; 70 70 - static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", }; 71 71 - static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4", 60 60 + static const char *const saxi_mux_p[] __initconst = { "armpll3", "armpll2", }; 61 61 + static const char *const pwm0_mux_p[] __initconst = { "osc32k", "osc26m", }; 62 62 + static const char *const pwm1_mux_p[] __initconst = { "osc32k", "osc26m", }; 63 63 + static const char *const sd_mux_p[] __initconst = { "armpll2", "armpll3", }; 64 64 + static const char *const mmc1_mux_p[] __initconst = { "armpll2", "armpll3", }; 65 65 + static const char *const mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", }; 66 66 + static const char *const g2d_mux_p[] __initconst = { "armpll2", "armpll3", }; 67 67 + static const char *const venc_mux_p[] __initconst = { "armpll2", "armpll3", }; 68 68 + static const char *const vdec_mux_p[] __initconst = { "armpll2", "armpll3", }; 69 69 + static const char *const vpp_mux_p[] __initconst = { "armpll2", "armpll3", }; 70 70 + static const char *const edc0_mux_p[] __initconst = { "armpll2", "armpll3", }; 71 71 + static const char *const ldi0_mux_p[] __initconst = { "armpll2", "armpll4", 72 72 "armpll3", "armpll5", }; 73 73 - static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", }; 74 74 - static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4", 73 73 + static const char *const edc1_mux_p[] __initconst = { "armpll2", "armpll3", }; 74 74 + static const char *const ldi1_mux_p[] __initconst = { "armpll2", "armpll4", 75 75 "armpll3", "armpll5", }; 76 76 - static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", }; 77 77 - static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", }; 78 78 - static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", }; 76 76 + static const char *const rclk_hsic_p[] __initconst = { "armpll3", "armpll2", }; 77 77 + static const char *const mmc2_mux_p[] __initconst = { "armpll2", "armpll3", }; 78 78 + static const char *const mmc3_mux_p[] __initconst = { "armpll2", "armpll3", }; 79 79 80 80 81 81 /* fixed rate clocks */

+3 -3

drivers/clk/hisilicon/clk-hix5hd2.c

reviewed

··· 46 46 { HIX5HD2_FIXED_83M, "83m", NULL, CLK_IS_ROOT, 83333333, }, 47 47 }; 48 48 49 49 - static const char *sfc_mux_p[] __initdata = { 49 49 + static const char *const sfc_mux_p[] __initconst = { 50 50 "24m", "150m", "200m", "100m", "75m", }; 51 51 static u32 sfc_mux_table[] = {0, 4, 5, 6, 7}; 52 52 53 53 - static const char *sdio_mux_p[] __initdata = { 53 53 + static const char *const sdio_mux_p[] __initconst = { 54 54 "75m", "100m", "50m", "15m", }; 55 55 static u32 sdio_mux_table[] = {0, 1, 2, 3}; 56 56 57 57 - static const char *fephy_mux_p[] __initdata = { "25m", "125m"}; 57 57 + static const char *const fephy_mux_p[] __initconst = { "25m", "125m"}; 58 58 static u32 fephy_mux_table[] = {0, 1}; 59 59 60 60

+1 -1

drivers/clk/hisilicon/clk.h

reviewed

··· 55 55 struct hisi_mux_clock { 56 56 unsigned int id; 57 57 const char *name; 58 58 - const char **parent_names; 58 58 + const char *const *parent_names; 59 59 u8 num_parents; 60 60 unsigned long flags; 61 61 unsigned long offset;

+6 -6

drivers/clk/mxs/clk-imx23.c

reviewed

··· 77 77 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); 78 78 } 79 79 80 80 - static const char *sel_pll[] __initdata = { "pll", "ref_xtal", }; 81 81 - static const char *sel_cpu[] __initdata = { "ref_cpu", "ref_xtal", }; 82 82 - static const char *sel_pix[] __initdata = { "ref_pix", "ref_xtal", }; 83 83 - static const char *sel_io[] __initdata = { "ref_io", "ref_xtal", }; 84 84 - static const char *cpu_sels[] __initdata = { "cpu_pll", "cpu_xtal", }; 85 85 - static const char *emi_sels[] __initdata = { "emi_pll", "emi_xtal", }; 80 80 + static const char *const sel_pll[] __initconst = { "pll", "ref_xtal", }; 81 81 + static const char *const sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; 82 82 + static const char *const sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; 83 83 + static const char *const sel_io[] __initconst = { "ref_io", "ref_xtal", }; 84 84 + static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", }; 85 85 + static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", }; 86 86 87 87 enum imx23_clk { 88 88 ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,

+9 -9

drivers/clk/mxs/clk-imx28.c

reviewed

··· 125 125 writel_relaxed(val, FRAC0); 126 126 } 127 127 128 128 - static const char *sel_cpu[] __initdata = { "ref_cpu", "ref_xtal", }; 129 129 - static const char *sel_io0[] __initdata = { "ref_io0", "ref_xtal", }; 130 130 - static const char *sel_io1[] __initdata = { "ref_io1", "ref_xtal", }; 131 131 - static const char *sel_pix[] __initdata = { "ref_pix", "ref_xtal", }; 132 132 - static const char *sel_gpmi[] __initdata = { "ref_gpmi", "ref_xtal", }; 133 133 - static const char *sel_pll0[] __initdata = { "pll0", "ref_xtal", }; 134 134 - static const char *cpu_sels[] __initdata = { "cpu_pll", "cpu_xtal", }; 135 135 - static const char *emi_sels[] __initdata = { "emi_pll", "emi_xtal", }; 136 136 - static const char *ptp_sels[] __initdata = { "ref_xtal", "pll0", }; 128 128 + static const char *const sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; 129 129 + static const char *const sel_io0[] __initconst = { "ref_io0", "ref_xtal", }; 130 130 + static const char *const sel_io1[] __initconst = { "ref_io1", "ref_xtal", }; 131 131 + static const char *const sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; 132 132 + static const char *const sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", }; 133 133 + static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", }; 134 134 + static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", }; 135 135 + static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", }; 136 136 + static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", }; 137 137 138 138 enum imx28_clk { 139 139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,

+1 -1

drivers/clk/mxs/clk.h

reviewed

··· 49 49 } 50 50 51 51 static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, 52 52 - u8 shift, u8 width, const char **parent_names, int num_parents) 52 52 + u8 shift, u8 width, const char *const *parent_names, int num_parents) 53 53 { 54 54 return clk_register_mux(NULL, name, parent_names, num_parents, 55 55 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,

+1 -1

drivers/clk/pxa/clk-pxa.h

reviewed

··· 14 14 #define _CLK_PXA_ 15 15 16 16 #define PARENTS(name) \ 17 17 - static const char *name ## _parents[] __initdata 17 17 + static const char *const name ## _parents[] __initconst 18 18 #define MUX_RO_RATE_RO_OPS(name, clk_name) \ 19 19 static struct clk_hw name ## _mux_hw; \ 20 20 static struct clk_hw name ## _rate_hw; \

+1 -1

drivers/clk/rockchip/clk-cpu.c

reviewed

··· 231 231 } 232 232 233 233 struct clk *rockchip_clk_register_cpuclk(const char *name, 234 234 - const char **parent_names, u8 num_parents, 234 234 + const char *const *parent_names, u8 num_parents, 235 235 const struct rockchip_cpuclk_reg_data *reg_data, 236 236 const struct rockchip_cpuclk_rate_table *rates, 237 237 int nrates, void __iomem *reg_base, spinlock_t *lock)

+1 -1

drivers/clk/rockchip/clk-mmc-phase.c

reviewed

··· 120 120 }; 121 121 122 122 struct clk *rockchip_clk_register_mmc(const char *name, 123 123 - const char **parent_names, u8 num_parents, 123 123 + const char *const *parent_names, u8 num_parents, 124 124 void __iomem *reg, int shift) 125 125 { 126 126 struct clk_init_data init;

+4 -4

drivers/clk/rockchip/clk-pll.c

reviewed

··· 329 329 */ 330 330 331 331 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, 332 332 - const char *name, const char **parent_names, u8 num_parents, 333 333 - void __iomem *base, int con_offset, int grf_lock_offset, 334 334 - int lock_shift, int mode_offset, int mode_shift, 335 335 - struct rockchip_pll_rate_table *rate_table, 332 332 + const char *name, const char *const *parent_names, 333 333 + u8 num_parents, void __iomem *base, int con_offset, 334 334 + int grf_lock_offset, int lock_shift, int mode_offset, 335 335 + int mode_shift, struct rockchip_pll_rate_table *rate_table, 336 336 u8 clk_pll_flags, spinlock_t *lock) 337 337 { 338 338 const char *pll_parents[3];

+4 -4

drivers/clk/rockchip/clk.c

reviewed

··· 39 39 * sometimes without one of those components. 40 40 */ 41 41 static struct clk *rockchip_clk_register_branch(const char *name, 42 42 - const char **parent_names, u8 num_parents, void __iomem *base, 42 42 + const char *const *parent_names, u8 num_parents, void __iomem *base, 43 43 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, 44 44 u8 div_shift, u8 div_width, u8 div_flags, 45 45 struct clk_div_table *div_table, int gate_offset, ··· 103 103 } 104 104 105 105 static struct clk *rockchip_clk_register_frac_branch(const char *name, 106 106 - const char **parent_names, u8 num_parents, void __iomem *base, 107 107 - int muxdiv_offset, u8 div_flags, 106 106 + const char *const *parent_names, u8 num_parents, 107 107 + void __iomem *base, int muxdiv_offset, u8 div_flags, 108 108 int gate_offset, u8 gate_shift, u8 gate_flags, 109 109 unsigned long flags, spinlock_t *lock) 110 110 { ··· 297 297 } 298 298 299 299 void __init rockchip_clk_register_armclk(unsigned int lookup_id, 300 300 - const char *name, const char **parent_names, 300 300 + const char *name, const char *const *parent_names, 301 301 u8 num_parents, 302 302 const struct rockchip_cpuclk_reg_data *reg_data, 303 303 const struct rockchip_cpuclk_rate_table *rates,

+10 -10

drivers/clk/rockchip/clk.h

reviewed

··· 108 108 struct rockchip_pll_clock { 109 109 unsigned int id; 110 110 const char *name; 111 111 - const char **parent_names; 111 111 + const char *const *parent_names; 112 112 u8 num_parents; 113 113 unsigned long flags; 114 114 int con_offset; ··· 140 140 } 141 141 142 142 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, 143 143 - const char *name, const char **parent_names, u8 num_parents, 144 144 - void __iomem *base, int con_offset, int grf_lock_offset, 145 145 - int lock_shift, int reg_mode, int mode_shift, 146 146 - struct rockchip_pll_rate_table *rate_table, 143 143 + const char *name, const char *const *parent_names, 144 144 + u8 num_parents, void __iomem *base, int con_offset, 145 145 + int grf_lock_offset, int lock_shift, int reg_mode, 146 146 + int mode_shift, struct rockchip_pll_rate_table *rate_table, 147 147 u8 clk_pll_flags, spinlock_t *lock); 148 148 149 149 struct rockchip_cpuclk_clksel { ··· 173 173 }; 174 174 175 175 struct clk *rockchip_clk_register_cpuclk(const char *name, 176 176 - const char **parent_names, u8 num_parents, 176 176 + const char *const *parent_names, u8 num_parents, 177 177 const struct rockchip_cpuclk_reg_data *reg_data, 178 178 const struct rockchip_cpuclk_rate_table *rates, 179 179 int nrates, void __iomem *reg_base, spinlock_t *lock); 180 180 181 181 struct clk *rockchip_clk_register_mmc(const char *name, 182 182 - const char **parent_names, u8 num_parents, 182 182 + const char *const *parent_names, u8 num_parents, 183 183 void __iomem *reg, int shift); 184 184 185 185 - #define PNAME(x) static const char *x[] __initdata 185 185 + #define PNAME(x) static const char *const x[] __initconst 186 186 187 187 enum rockchip_clk_branch_type { 188 188 branch_composite, ··· 197 197 unsigned int id; 198 198 enum rockchip_clk_branch_type branch_type; 199 199 const char *name; 200 200 - const char **parent_names; 200 200 + const char *const *parent_names; 201 201 u8 num_parents; 202 202 unsigned long flags; 203 203 int muxdiv_offset; ··· 403 403 void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list, 404 404 unsigned int nr_pll, int grf_lock_offset); 405 405 void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name, 406 406 - const char **parent_names, u8 num_parents, 406 406 + const char *const *parent_names, u8 num_parents, 407 407 const struct rockchip_cpuclk_reg_data *reg_data, 408 408 const struct rockchip_cpuclk_rate_table *rates, 409 409 int nrates);

+2 -2

drivers/clk/samsung/clk-pll.c

reviewed

··· 1156 1156 }; 1157 1157 1158 1158 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, 1159 1159 - struct samsung_pll_clock *pll_clk, 1159 1159 + const struct samsung_pll_clock *pll_clk, 1160 1160 void __iomem *base) 1161 1161 { 1162 1162 struct samsung_clk_pll *pll; ··· 1303 1303 } 1304 1304 1305 1305 void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, 1306 1306 - struct samsung_pll_clock *pll_list, 1306 1306 + const struct samsung_pll_clock *pll_list, 1307 1307 unsigned int nr_pll, void __iomem *base) 1308 1308 { 1309 1309 int cnt;

+44 -44

drivers/clk/samsung/clk-s5pv210.c

reviewed

··· 169 169 #endif 170 170 171 171 /* Mux parent lists. */ 172 172 - static const char *fin_pll_p[] __initdata = { 172 172 + static const char *const fin_pll_p[] __initconst = { 173 173 "xxti", 174 174 "xusbxti" 175 175 }; 176 176 177 177 - static const char *mout_apll_p[] __initdata = { 177 177 + static const char *const mout_apll_p[] __initconst = { 178 178 "fin_pll", 179 179 "fout_apll" 180 180 }; 181 181 182 182 - static const char *mout_mpll_p[] __initdata = { 182 182 + static const char *const mout_mpll_p[] __initconst = { 183 183 "fin_pll", 184 184 "fout_mpll" 185 185 }; 186 186 187 187 - static const char *mout_epll_p[] __initdata = { 187 187 + static const char *const mout_epll_p[] __initconst = { 188 188 "fin_pll", 189 189 "fout_epll" 190 190 }; 191 191 192 192 - static const char *mout_vpllsrc_p[] __initdata = { 192 192 + static const char *const mout_vpllsrc_p[] __initconst = { 193 193 "fin_pll", 194 194 "sclk_hdmi27m" 195 195 }; 196 196 197 197 - static const char *mout_vpll_p[] __initdata = { 197 197 + static const char *const mout_vpll_p[] __initconst = { 198 198 "mout_vpllsrc", 199 199 "fout_vpll" 200 200 }; 201 201 202 202 - static const char *mout_group1_p[] __initdata = { 202 202 + static const char *const mout_group1_p[] __initconst = { 203 203 "dout_a2m", 204 204 "mout_mpll", 205 205 "mout_epll", 206 206 "mout_vpll" 207 207 }; 208 208 209 209 - static const char *mout_group2_p[] __initdata = { 209 209 + static const char *const mout_group2_p[] __initconst = { 210 210 "xxti", 211 211 "xusbxti", 212 212 "sclk_hdmi27m", ··· 218 218 "mout_vpll", 219 219 }; 220 220 221 221 - static const char *mout_audio0_p[] __initdata = { 221 221 + static const char *const mout_audio0_p[] __initconst = { 222 222 "xxti", 223 223 "pcmcdclk0", 224 224 "sclk_hdmi27m", ··· 230 230 "mout_vpll", 231 231 }; 232 232 233 233 - static const char *mout_audio1_p[] __initdata = { 233 233 + static const char *const mout_audio1_p[] __initconst = { 234 234 "i2scdclk1", 235 235 "pcmcdclk1", 236 236 "sclk_hdmi27m", ··· 242 242 "mout_vpll", 243 243 }; 244 244 245 245 - static const char *mout_audio2_p[] __initdata = { 245 245 + static const char *const mout_audio2_p[] __initconst = { 246 246 "i2scdclk2", 247 247 "pcmcdclk2", 248 248 "sclk_hdmi27m", ··· 254 254 "mout_vpll", 255 255 }; 256 256 257 257 - static const char *mout_spdif_p[] __initdata = { 257 257 + static const char *const mout_spdif_p[] __initconst = { 258 258 "dout_audio0", 259 259 "dout_audio1", 260 260 "dout_audio3", 261 261 }; 262 262 263 263 - static const char *mout_group3_p[] __initdata = { 263 263 + static const char *const mout_group3_p[] __initconst = { 264 264 "mout_apll", 265 265 "mout_mpll" 266 266 }; 267 267 268 268 - static const char *mout_group4_p[] __initdata = { 268 268 + static const char *const mout_group4_p[] __initconst = { 269 269 "mout_mpll", 270 270 "dout_a2m" 271 271 }; 272 272 273 273 - static const char *mout_flash_p[] __initdata = { 273 273 + static const char *const mout_flash_p[] __initconst = { 274 274 "dout_hclkd", 275 275 "dout_hclkp" 276 276 }; 277 277 278 278 - static const char *mout_dac_p[] __initdata = { 278 278 + static const char *const mout_dac_p[] __initconst = { 279 279 "mout_vpll", 280 280 "sclk_hdmiphy" 281 281 }; 282 282 283 283 - static const char *mout_hdmi_p[] __initdata = { 283 283 + static const char *const mout_hdmi_p[] __initconst = { 284 284 "sclk_hdmiphy", 285 285 "dout_tblk" 286 286 }; 287 287 288 288 - static const char *mout_mixer_p[] __initdata = { 288 288 + static const char *const mout_mixer_p[] __initconst = { 289 289 "mout_dac", 290 290 "mout_hdmi" 291 291 }; 292 292 293 293 - static const char *mout_vpll_6442_p[] __initdata = { 293 293 + static const char *const mout_vpll_6442_p[] __initconst = { 294 294 "fin_pll", 295 295 "fout_vpll" 296 296 }; 297 297 298 298 - static const char *mout_mixer_6442_p[] __initdata = { 298 298 + static const char *const mout_mixer_6442_p[] __initconst = { 299 299 "mout_vpll", 300 300 "dout_mixer" 301 301 }; 302 302 303 303 - static const char *mout_d0sync_6442_p[] __initdata = { 303 303 + static const char *const mout_d0sync_6442_p[] __initconst = { 304 304 "mout_dsys", 305 305 "div_apll" 306 306 }; 307 307 308 308 - static const char *mout_d1sync_6442_p[] __initdata = { 308 308 + static const char *const mout_d1sync_6442_p[] __initconst = { 309 309 "mout_psys", 310 310 "div_apll" 311 311 }; 312 312 313 313 - static const char *mout_group2_6442_p[] __initdata = { 313 313 + static const char *const mout_group2_6442_p[] __initconst = { 314 314 "fin_pll", 315 315 "none", 316 316 "none", ··· 322 322 "mout_vpll", 323 323 }; 324 324 325 325 - static const char *mout_audio0_6442_p[] __initdata = { 325 325 + static const char *const mout_audio0_6442_p[] __initconst = { 326 326 "fin_pll", 327 327 "pcmcdclk0", 328 328 "none", ··· 334 334 "mout_vpll", 335 335 }; 336 336 337 337 - static const char *mout_audio1_6442_p[] __initdata = { 337 337 + static const char *const mout_audio1_6442_p[] __initconst = { 338 338 "i2scdclk1", 339 339 "pcmcdclk1", 340 340 "none", ··· 347 347 "fin_pll", 348 348 }; 349 349 350 350 - static const char *mout_clksel_p[] __initdata = { 350 350 + static const char *const mout_clksel_p[] __initconst = { 351 351 "fout_apll_clkout", 352 352 "fout_mpll_clkout", 353 353 "fout_epll", ··· 370 370 "div_dclk" 371 371 }; 372 372 373 373 - static const char *mout_clksel_6442_p[] __initdata = { 373 373 + static const char *const mout_clksel_6442_p[] __initconst = { 374 374 "fout_apll_clkout", 375 375 "fout_mpll_clkout", 376 376 "fout_epll", ··· 393 393 "div_dclk" 394 394 }; 395 395 396 396 - static const char *mout_clkout_p[] __initdata = { 396 396 + static const char *const mout_clkout_p[] __initconst = { 397 397 "dout_clkout", 398 398 "none", 399 399 "xxti", ··· 401 401 }; 402 402 403 403 /* Common fixed factor clocks. */ 404 404 - static struct samsung_fixed_factor_clock ffactor_clks[] __initdata = { 404 404 + static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = { 405 405 FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0), 406 406 FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0), 407 407 FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0), 408 408 }; 409 409 410 410 /* PLL input mux (fin_pll), which needs to be registered before PLLs. */ 411 411 - static struct samsung_mux_clock early_mux_clks[] __initdata = { 411 411 + static const struct samsung_mux_clock early_mux_clks[] __initconst = { 412 412 MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1, 413 413 CLK_MUX_READ_ONLY, 0), 414 414 }; 415 415 416 416 /* Common clock muxes. */ 417 417 - static struct samsung_mux_clock mux_clks[] __initdata = { 417 417 + static const struct samsung_mux_clock mux_clks[] __initconst = { 418 418 MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1), 419 419 MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1), 420 420 MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1), ··· 427 427 }; 428 428 429 429 /* S5PV210-specific clock muxes. */ 430 430 - static struct samsung_mux_clock s5pv210_mux_clks[] __initdata = { 430 430 + static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = { 431 431 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1), 432 432 433 433 MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1), ··· 472 472 }; 473 473 474 474 /* S5P6442-specific clock muxes. */ 475 475 - static struct samsung_mux_clock s5p6442_mux_clks[] __initdata = { 475 475 + static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = { 476 476 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1), 477 477 478 478 MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4), ··· 504 504 }; 505 505 506 506 /* S5PV210-specific fixed rate clocks generated inside the SoC. */ 507 507 - static struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initdata = { 507 507 + static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = { 508 508 FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 509 509 FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 510 510 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), ··· 512 512 }; 513 513 514 514 /* S5P6442-specific fixed rate clocks generated inside the SoC. */ 515 515 - static struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initdata = { 515 515 + static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = { 516 516 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 30000000), 517 517 }; 518 518 519 519 /* Common clock dividers. */ 520 520 - static struct samsung_div_clock div_clks[] __initdata = { 520 520 + static const struct samsung_div_clock div_clks[] __initconst = { 521 521 DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3), 522 522 DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3), 523 523 DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3), ··· 549 549 }; 550 550 551 551 /* S5PV210-specific clock dividers. */ 552 552 - static struct samsung_div_clock s5pv210_div_clks[] __initdata = { 552 552 + static const struct samsung_div_clock s5pv210_div_clks[] __initconst = { 553 553 DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4), 554 554 DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4), 555 555 DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3), ··· 578 578 }; 579 579 580 580 /* S5P6442-specific clock dividers. */ 581 581 - static struct samsung_div_clock s5p6442_div_clks[] __initdata = { 581 581 + static const struct samsung_div_clock s5p6442_div_clks[] __initconst = { 582 582 DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4), 583 583 DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4), 584 584 ··· 586 586 }; 587 587 588 588 /* Common clock gates. */ 589 589 - static struct samsung_gate_clock gate_clks[] __initdata = { 589 589 + static const struct samsung_gate_clock gate_clks[] __initconst = { 590 590 GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0), 591 591 GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0), 592 592 GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0), ··· 666 666 }; 667 667 668 668 /* S5PV210-specific clock gates. */ 669 669 - static struct samsung_gate_clock s5pv210_gate_clks[] __initdata = { 669 669 + static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = { 670 670 GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0), 671 671 GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0), 672 672 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0), ··· 728 728 }; 729 729 730 730 /* S5P6442-specific clock gates. */ 731 731 - static struct samsung_gate_clock s5p6442_gate_clks[] __initdata = { 731 731 + static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = { 732 732 GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0), 733 733 GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0), 734 734 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0), ··· 748 748 * Clock aliases for legacy clkdev look-up. 749 749 * NOTE: Needed only to support legacy board files. 750 750 */ 751 751 - static struct samsung_clock_alias s5pv210_aliases[] = { 751 751 + static const struct samsung_clock_alias s5pv210_aliases[] __initconst = { 752 752 ALIAS(DOUT_APLL, NULL, "armclk"), 753 753 ALIAS(DOUT_HCLKM, NULL, "hclk_msys"), 754 754 ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"), 755 755 }; 756 756 757 757 /* S5PV210-specific PLLs. */ 758 758 - static struct samsung_pll_clock s5pv210_pll_clks[] __initdata = { 758 758 + static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = { 759 759 [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll", 760 760 APLL_LOCK, APLL_CON0, NULL), 761 761 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", ··· 767 767 }; 768 768 769 769 /* S5P6442-specific PLLs. */ 770 770 - static struct samsung_pll_clock s5p6442_pll_clks[] __initdata = { 770 770 + static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = { 771 771 [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll", 772 772 APLL_LOCK, APLL_CON0, NULL), 773 773 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",

+7 -6

drivers/clk/samsung/clk.c

reviewed

··· 98 98 99 99 /* register a list of aliases */ 100 100 void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, 101 101 - struct samsung_clock_alias *list, 101 101 + const struct samsung_clock_alias *list, 102 102 unsigned int nr_clk) 103 103 { 104 104 struct clk *clk; ··· 132 132 133 133 /* register a list of fixed clocks */ 134 134 void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, 135 135 - struct samsung_fixed_rate_clock *list, unsigned int nr_clk) 135 135 + const struct samsung_fixed_rate_clock *list, 136 136 + unsigned int nr_clk) 136 137 { 137 138 struct clk *clk; 138 139 unsigned int idx, ret; ··· 162 161 163 162 /* register a list of fixed factor clocks */ 164 163 void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, 165 165 - struct samsung_fixed_factor_clock *list, unsigned int nr_clk) 164 164 + const struct samsung_fixed_factor_clock *list, unsigned int nr_clk) 166 165 { 167 166 struct clk *clk; 168 167 unsigned int idx; ··· 182 181 183 182 /* register a list of mux clocks */ 184 183 void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, 185 185 - struct samsung_mux_clock *list, 184 184 + const struct samsung_mux_clock *list, 186 185 unsigned int nr_clk) 187 186 { 188 187 struct clk *clk; ··· 214 213 215 214 /* register a list of div clocks */ 216 215 void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, 217 217 - struct samsung_div_clock *list, 216 216 + const struct samsung_div_clock *list, 218 217 unsigned int nr_clk) 219 218 { 220 219 struct clk *clk; ··· 253 252 254 253 /* register a list of gate clocks */ 255 254 void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, 256 256 - struct samsung_gate_clock *list, 255 255 + const struct samsung_gate_clock *list, 257 256 unsigned int nr_clk) 258 257 { 259 258 struct clk *clk;

+9 -9

drivers/clk/samsung/clk.h

reviewed

··· 121 121 unsigned int id; 122 122 const char *dev_name; 123 123 const char *name; 124 124 - const char **parent_names; 124 124 + const char *const *parent_names; 125 125 u8 num_parents; 126 126 unsigned long flags; 127 127 unsigned long offset; ··· 368 368 extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, 369 369 struct clk *clk, unsigned int id); 370 370 371 371 - extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, 372 372 - struct samsung_clock_alias *list, 371 371 + extern void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, 372 372 + const struct samsung_clock_alias *list, 373 373 unsigned int nr_clk); 374 374 extern void __init samsung_clk_register_fixed_rate( 375 375 struct samsung_clk_provider *ctx, 376 376 - struct samsung_fixed_rate_clock *clk_list, 376 376 + const struct samsung_fixed_rate_clock *clk_list, 377 377 unsigned int nr_clk); 378 378 extern void __init samsung_clk_register_fixed_factor( 379 379 struct samsung_clk_provider *ctx, 380 380 - struct samsung_fixed_factor_clock *list, 380 380 + const struct samsung_fixed_factor_clock *list, 381 381 unsigned int nr_clk); 382 382 extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, 383 383 - struct samsung_mux_clock *clk_list, 383 383 + const struct samsung_mux_clock *clk_list, 384 384 unsigned int nr_clk); 385 385 extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, 386 386 - struct samsung_div_clock *clk_list, 386 386 + const struct samsung_div_clock *clk_list, 387 387 unsigned int nr_clk); 388 388 extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, 389 389 - struct samsung_gate_clock *clk_list, 389 389 + const struct samsung_gate_clock *clk_list, 390 390 unsigned int nr_clk); 391 391 extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, 392 392 - struct samsung_pll_clock *pll_list, 392 392 + const struct samsung_pll_clock *pll_list, 393 393 unsigned int nr_clk, void __iomem *base); 394 394 395 395 extern struct samsung_clk_provider __init *samsung_cmu_register_one(

+16 -9

drivers/clk/zynq/clkc.c

reviewed

··· 85 85 static DEFINE_SPINLOCK(dbgclk_lock); 86 86 static DEFINE_SPINLOCK(aperclk_lock); 87 87 88 88 - static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"}; 89 89 - static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"}; 90 90 - static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"}; 88 88 + static const char *const armpll_parents[] __initconst = {"armpll_int", 89 89 + "ps_clk"}; 90 90 + static const char *const ddrpll_parents[] __initconst = {"ddrpll_int", 91 91 + "ps_clk"}; 92 92 + static const char *const iopll_parents[] __initconst = {"iopll_int", 93 93 + "ps_clk"}; 91 94 static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"}; 92 95 static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"}; 93 93 - static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate", 96 96 + static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate", 94 97 "can0_mio_mux"}; 95 95 - static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate", 98 98 + static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate", 96 99 "can1_mio_mux"}; 97 100 static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", 98 101 "dummy_name"}; 99 102 100 100 - static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"}; 101 101 - static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"}; 102 102 - static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"}; 103 103 - static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"}; 103 103 + static const char *const dbgtrc_emio_input_names[] __initconst = { 104 104 + "trace_emio_clk"}; 105 105 + static const char *const gem0_emio_input_names[] __initconst = { 106 106 + "gem0_emio_clk"}; 107 107 + static const char *const gem1_emio_input_names[] __initconst = { 108 108 + "gem1_emio_clk"}; 109 109 + static const char *const swdt_ext_clk_input_names[] __initconst = { 110 110 + "swdt_ext_clk"}; 104 111 105 112 static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 106 113 const char *clk_name, void __iomem *fclk_ctrl_reg,