tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'clk-rockchip' into clk-next
+116
-47
+25
-10
drivers/clk/rockchip/clk-rk3036.c
+25
-10
drivers/clk/rockchip/clk-rk3036.c
···
149
149
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
150
150
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
151
151
152
+
static struct rockchip_clk_branch rk3036_uart0_fracmux __initdata =
153
+
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
154
+
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
155
+
156
+
static struct rockchip_clk_branch rk3036_uart1_fracmux __initdata =
157
+
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
158
+
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
159
+
160
+
static struct rockchip_clk_branch rk3036_uart2_fracmux __initdata =
161
+
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
162
+
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
163
+
164
+
static struct rockchip_clk_branch rk3036_i2s_fracmux __initdata =
165
+
MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
166
+
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
167
+
168
+
static struct rockchip_clk_branch rk3036_spdif_fracmux __initdata =
169
+
MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
170
+
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
171
+
152
172
static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
153
173
/*
154
174
* Clock-Architecture Diagram 1
···
250
230
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
251
231
RK2928_CLKSEL_CON(17), 0,
252
232
RK2928_CLKGATE_CON(1), 9, GFLAGS,
253
-
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
254
-
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS)),
233
+
&rk3036_uart0_fracmux),
255
234
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
256
235
RK2928_CLKSEL_CON(18), 0,
257
236
RK2928_CLKGATE_CON(1), 11, GFLAGS,
258
-
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
259
-
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS)),
237
+
&rk3036_uart1_fracmux),
260
238
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
261
239
RK2928_CLKSEL_CON(19), 0,
262
240
RK2928_CLKGATE_CON(1), 13, GFLAGS,
263
-
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
264
-
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS)),
241
+
&rk3036_uart2_fracmux),
265
242
266
243
COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
267
244
RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
···
309
292
COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
310
293
RK2928_CLKSEL_CON(7), 0,
311
294
RK2928_CLKGATE_CON(0), 10, GFLAGS,
312
-
MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
313
-
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS)),
295
+
&rk3036_i2s_fracmux),
314
296
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
315
297
RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
316
298
RK2928_CLKGATE_CON(0), 13, GFLAGS),
···
322
306
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
323
307
RK2928_CLKSEL_CON(9), 0,
324
308
RK2928_CLKGATE_CON(2), 12, GFLAGS,
325
-
MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
326
-
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS)),
309
+
&rk3036_spdif_fracmux),
327
310
328
311
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
329
312
RK2928_CLKGATE_CON(1), 5, GFLAGS),
+50
-20
drivers/clk/rockchip/clk-rk3188.c
+50
-20
drivers/clk/rockchip/clk-rk3188.c
···
247
247
{ /* sentinel */ },
248
248
};
249
249
250
+
static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata =
251
+
MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
252
+
RK2928_CLKSEL_CON(22), 4, 2, MFLAGS);
253
+
254
+
static struct rockchip_clk_branch common_spdif_fracmux __initdata =
255
+
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
256
+
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
257
+
258
+
static struct rockchip_clk_branch common_uart0_fracmux __initdata =
259
+
MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
260
+
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
261
+
262
+
static struct rockchip_clk_branch common_uart1_fracmux __initdata =
263
+
MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
264
+
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
265
+
266
+
static struct rockchip_clk_branch common_uart2_fracmux __initdata =
267
+
MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
268
+
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
269
+
270
+
static struct rockchip_clk_branch common_uart3_fracmux __initdata =
271
+
MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
272
+
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
273
+
250
274
static struct rockchip_clk_branch common_clk_branches[] __initdata = {
251
275
/*
252
276
* Clock-Architecture Diagram 2
···
362
338
COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0,
363
339
RK2928_CLKSEL_CON(23), 0,
364
340
RK2928_CLKGATE_CON(2), 7, GFLAGS,
365
-
MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
366
-
RK2928_CLKSEL_CON(22), 4, 2, MFLAGS)),
341
+
&common_hsadc_out_fracmux),
367
342
INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
368
343
RK2928_CLKSEL_CON(22), 7, IFLAGS),
369
344
···
376
353
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pll", CLK_SET_RATE_PARENT,
377
354
RK2928_CLKSEL_CON(9), 0,
378
355
RK2928_CLKGATE_CON(0), 14, GFLAGS,
379
-
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
380
-
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS)),
356
+
&common_spdif_fracmux),
381
357
382
358
/*
383
359
* Clock-Architecture Diagram 4
···
410
388
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0,
411
389
RK2928_CLKSEL_CON(17), 0,
412
390
RK2928_CLKGATE_CON(1), 9, GFLAGS,
413
-
MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
414
-
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS)),
391
+
&common_uart0_fracmux),
415
392
COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
416
393
RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
417
394
RK2928_CLKGATE_CON(1), 10, GFLAGS),
418
395
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0,
419
396
RK2928_CLKSEL_CON(18), 0,
420
397
RK2928_CLKGATE_CON(1), 11, GFLAGS,
421
-
MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
422
-
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS)),
398
+
&common_uart1_fracmux),
423
399
COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
424
400
RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
425
401
RK2928_CLKGATE_CON(1), 12, GFLAGS),
426
402
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0,
427
403
RK2928_CLKSEL_CON(19), 0,
428
404
RK2928_CLKGATE_CON(1), 13, GFLAGS,
429
-
MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
430
-
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS)),
405
+
&common_uart2_fracmux),
431
406
COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
432
407
RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
433
408
RK2928_CLKGATE_CON(1), 14, GFLAGS),
434
409
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0,
435
410
RK2928_CLKSEL_CON(20), 0,
436
411
RK2928_CLKGATE_CON(1), 15, GFLAGS,
437
-
MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
438
-
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS)),
412
+
&common_uart3_fracmux),
439
413
440
414
GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
441
415
···
541
523
{ /* sentinel */ },
542
524
};
543
525
526
+
static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata =
527
+
MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
528
+
RK2928_CLKSEL_CON(2), 8, 2, MFLAGS);
529
+
530
+
static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata =
531
+
MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
532
+
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
533
+
534
+
static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata =
535
+
MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
536
+
RK2928_CLKSEL_CON(4), 8, 2, MFLAGS);
537
+
544
538
static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
545
539
DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
546
540
RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t),
···
617
587
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
618
588
RK2928_CLKSEL_CON(6), 0,
619
589
RK2928_CLKGATE_CON(0), 8, GFLAGS,
620
-
MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
621
-
RK2928_CLKSEL_CON(2), 8, 2, MFLAGS)),
590
+
&rk3066a_i2s0_fracmux),
622
591
COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
623
592
RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
624
593
RK2928_CLKGATE_CON(0), 9, GFLAGS),
625
594
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0,
626
595
RK2928_CLKSEL_CON(7), 0,
627
596
RK2928_CLKGATE_CON(0), 10, GFLAGS,
628
-
MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
629
-
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS)),
597
+
&rk3066a_i2s1_fracmux),
630
598
COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
631
599
RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
632
600
RK2928_CLKGATE_CON(0), 11, GFLAGS),
633
601
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0,
634
602
RK2928_CLKSEL_CON(8), 0,
635
603
RK2928_CLKGATE_CON(0), 12, GFLAGS,
636
-
MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
637
-
RK2928_CLKSEL_CON(4), 8, 2, MFLAGS)),
604
+
&rk3066a_i2s2_fracmux),
638
605
639
606
GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
640
607
GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
···
664
637
665
638
PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1",
666
639
"gpll", "cpll" };
640
+
641
+
static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
642
+
MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
643
+
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
667
644
668
645
static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
669
646
COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
···
725
694
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
726
695
RK2928_CLKSEL_CON(7), 0,
727
696
RK2928_CLKGATE_CON(0), 10, GFLAGS,
728
-
MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
729
-
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS)),
697
+
&rk3188_i2s0_fracmux),
730
698
731
699
GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
732
700
GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
+40
-16
drivers/clk/rockchip/clk-rk3288.c
+40
-16
drivers/clk/rockchip/clk-rk3288.c
···
225
225
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
226
226
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
227
227
228
+
static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata =
229
+
MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
230
+
RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);
231
+
232
+
static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata =
233
+
MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
234
+
RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);
235
+
236
+
static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata =
237
+
MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
238
+
RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);
239
+
240
+
static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata =
241
+
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
242
+
RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
243
+
244
+
static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata =
245
+
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
246
+
RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
247
+
248
+
static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata =
249
+
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
250
+
RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
251
+
252
+
static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata =
253
+
MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
254
+
RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
255
+
256
+
static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata =
257
+
MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
258
+
RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);
259
+
228
260
static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
229
261
/*
230
262
* Clock-Architecture Diagram 1
···
339
307
COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
340
308
RK3288_CLKSEL_CON(8), 0,
341
309
RK3288_CLKGATE_CON(4), 2, GFLAGS,
342
-
MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
343
-
RK3288_CLKSEL_CON(4), 8, 2, MFLAGS)),
310
+
&rk3288_i2s_fracmux),
344
311
COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
345
312
RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
346
313
RK3288_CLKGATE_CON(4), 0, GFLAGS),
···
354
323
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
355
324
RK3288_CLKSEL_CON(9), 0,
356
325
RK3288_CLKGATE_CON(4), 5, GFLAGS,
357
-
MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
358
-
RK3288_CLKSEL_CON(5), 8, 2, MFLAGS)),
326
+
&rk3288_spdif_fracmux),
359
327
GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
360
328
RK3288_CLKGATE_CON(4), 6, GFLAGS),
361
329
COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
···
363
333
COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
364
334
RK3288_CLKSEL_CON(41), 0,
365
335
RK3288_CLKGATE_CON(4), 8, GFLAGS,
366
-
MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
367
-
RK3288_CLKSEL_CON(40), 8, 2, MFLAGS)),
336
+
&rk3288_spdif_8ch_fracmux),
368
337
GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
369
338
RK3288_CLKGATE_CON(4), 9, GFLAGS),
370
339
···
570
541
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
571
542
RK3288_CLKSEL_CON(17), 0,
572
543
RK3288_CLKGATE_CON(1), 9, GFLAGS,
573
-
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
574
-
RK3288_CLKSEL_CON(13), 8, 2, MFLAGS)),
544
+
&rk3288_uart0_fracmux),
575
545
MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
576
546
RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
577
547
COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
···
579
551
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
580
552
RK3288_CLKSEL_CON(18), 0,
581
553
RK3288_CLKGATE_CON(1), 11, GFLAGS,
582
-
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
583
-
RK3288_CLKSEL_CON(14), 8, 2, MFLAGS)),
554
+
&rk3288_uart1_fracmux),
584
555
COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
585
556
RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
586
557
RK3288_CLKGATE_CON(1), 12, GFLAGS),
587
558
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
588
559
RK3288_CLKSEL_CON(19), 0,
589
560
RK3288_CLKGATE_CON(1), 13, GFLAGS,
590
-
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
591
-
RK3288_CLKSEL_CON(15), 8, 2, MFLAGS)),
561
+
&rk3288_uart2_fracmux),
592
562
COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
593
563
RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
594
564
RK3288_CLKGATE_CON(1), 14, GFLAGS),
595
565
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
596
566
RK3288_CLKSEL_CON(20), 0,
597
567
RK3288_CLKGATE_CON(1), 15, GFLAGS,
598
-
MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
599
-
RK3288_CLKSEL_CON(16), 8, 2, MFLAGS)),
568
+
&rk3288_uart3_fracmux),
600
569
COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
601
570
RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
602
571
RK3288_CLKGATE_CON(2), 12, GFLAGS),
603
572
COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
604
573
RK3288_CLKSEL_CON(7), 0,
605
574
RK3288_CLKGATE_CON(2), 13, GFLAGS,
606
-
MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
607
-
RK3288_CLKSEL_CON(3), 8, 2, MFLAGS)),
575
+
&rk3288_uart4_fracmux),
608
576
609
577
COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
610
578
RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,