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linux
cxl: docs/platform/cdat reference documentation
Add documentation for CDAT structures for CXL usages.
Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250515000923.2590820-2-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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Documentation/driver-api/cxl/index.rst
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Documentation/driver-api/cxl/index.rst
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Documentation/driver-api/cxl/platform/cdat.rst
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Documentation/driver-api/cxl/platform/cdat.rst
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.. SPDX-License-Identifier: GPL-2.0
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======================================
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Coherent Device Attribute Table (CDAT)
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======================================
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The CDAT provides functional and performance attributes of devices such
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as CXL accelerators, switches, or endpoints. The table formatting is
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similar to ACPI tables. CDAT data may be parsed by BIOS at boot or may
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be enumerated at runtime (after device hotplug, for example).
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Terminology:
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DPA - Device Physical Address, used by the CXL device to denote the address
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it supports for that device.
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DSMADHandle - A device unique handle that is associated with a DPA range
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defined by the DSMAS table.
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===============================================
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Device Scoped Memory Affinity Structure (DSMAS)
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===============================================
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The DSMAS contains information such as DSMADHandle, the DPA Base, and DPA
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Length.
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This table is used by Linux in conjunction with the Device Scoped Latency and
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Bandwidth Information Structure (DSLBIS) to determine the performance
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attributes of the CXL device itself.
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Example ::
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Structure Type : 00 [DSMAS]
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Reserved : 00
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Length : 0018 <- 24d, size of structure
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DSMADHandle : 01
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Flags : 00
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Reserved : 0000
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DPA Base : 0000000040000000 <- 1GiB base
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DPA Length : 0000000080000000 <- 2GiB size
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==================================================================
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Device Scoped Latency and Bandwidth Information Structure (DSLBIS)
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==================================================================
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This table is used by Linux in conjunction with DSMAS to determine the
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performance attributes of a CXL device. The DSLBIS contains latency
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and bandwidth information based on DSMADHandle matching.
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Example ::
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Structure Type : 01 [DSLBIS]
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Reserved : 00
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Length : 18 <- 24d, size of structure
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Handle : 0001 <- DSMAS handle
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Flags : 00 <- Matches flag field for HMAT SLLBIS
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Data Type : 00 <- Latency
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Entry Basee Unit : 0000000000001000 <- Entry Base Unit field in HMAT SSLBIS
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Entry : 010000000000 <- First byte used here, CXL LTC
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Reserved : 0000
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Structure Type : 01 [DSLBIS]
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Reserved : 00
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Length : 18 <- 24d, size of structure
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Handle : 0001 <- DSMAS handle
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Flags : 00 <- Matches flag field for HMAT SLLBIS
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Data Type : 03 <- Bandwidth
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Entry Basee Unit : 0000000000001000 <- Entry Base Unit field in HMAT SSLBIS
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Entry : 020000000000 <- First byte used here, CXL BW
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Reserved : 0000
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==================================================================
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Switch Scoped Latency and Bandwidth Information Structure (SSLBIS)
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==================================================================
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The SSLBIS contains information about the latency and bandwidth of a switch.
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The table is used by Linux to compute the performance coordinates of a CXL path
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from the device to the root port where a switch is part of the path.
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Example ::
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Structure Type : 05 [SSLBIS]
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Reserved : 00
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Length : 20 <- 32d, length of record, including SSLB entries
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Data Type : 00 <- Latency
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Reserved : 000000
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Entry Base Unit : 00000000000000001000 <- Matches Entry Base Unit in HMAT SSLBIS
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<- SSLB Entry 0
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Port X ID : 0100 <- First port, 0100h represents an upstream port
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Port Y ID : 0000 <- Second port, downstream port 0
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Latency : 0100 <- Port latency
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Reserved : 0000
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<- SSLB Entry 1
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Port X ID : 0100
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Port Y ID : 0001
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Latency : 0100
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Reserved : 0000
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Structure Type : 05 [SSLBIS]
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Reserved : 00
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Length : 18 <- 24d, length of record, including SSLB entry
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Data Type : 03 <- Bandwidth
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Reserved : 000000
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Entry Base Unit : 00000000000000001000 <- Matches Entry Base Unit in HMAT SSLBIS
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<- SSLB Entry 0
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Port X ID : 0100 <- First port, 0100h represents an upstream port
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Port Y ID : FFFF <- Second port, FFFFh indicates any port
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Bandwidth : 1200 <- Port bandwidth
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Reserved : 0000
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The CXL driver uses a combination of CDAT, HMAT, SRAT, and other data to
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generate "whole path performance" data for a CXL device.