tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

Pull idle update from Len Brown:
"Two Intel-platform-specific updates to intel_idle, and a cosmetic
tweak to the turbostat utility"

* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux:
tools/power turbostat: tweak whitespace in output format
intel_idle: Broadwell support
intel_idle: Disable Baytrail Core and Module C6 auto-demotion

Linus Torvalds 49899007 6fedb0ff

+119 -41
+3
arch/x86/include/uapi/asm/msr-index.h
··· 149 149 150 150 #define MSR_CORE_C1_RES 0x00000660 151 151 152 + #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 153 + #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 154 + 152 155 #define MSR_AMD64_MC0_MASK 0xc0010044 153 156 154 157 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
+76 -1
drivers/idle/intel_idle.c
··· 89 89 * Indicate which enable bits to clear here. 90 90 */ 91 91 unsigned long auto_demotion_disable_flags; 92 + bool byt_auto_demotion_disable_flag; 92 93 bool disable_promotion_to_c1e; 93 94 }; 94 95 ··· 443 442 { 444 443 .enter = NULL } 445 444 }; 445 + static struct cpuidle_state bdw_cstates[] = { 446 + { 447 + .name = "C1-BDW", 448 + .desc = "MWAIT 0x00", 449 + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 450 + .exit_latency = 2, 451 + .target_residency = 2, 452 + .enter = &intel_idle }, 453 + { 454 + .name = "C1E-BDW", 455 + .desc = "MWAIT 0x01", 456 + .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 457 + .exit_latency = 10, 458 + .target_residency = 20, 459 + .enter = &intel_idle }, 460 + { 461 + .name = "C3-BDW", 462 + .desc = "MWAIT 0x10", 463 + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 464 + .exit_latency = 40, 465 + .target_residency = 100, 466 + .enter = &intel_idle }, 467 + { 468 + .name = "C6-BDW", 469 + .desc = "MWAIT 0x20", 470 + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 471 + .exit_latency = 133, 472 + .target_residency = 400, 473 + .enter = &intel_idle }, 474 + { 475 + .name = "C7s-BDW", 476 + .desc = "MWAIT 0x32", 477 + .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 478 + .exit_latency = 166, 479 + .target_residency = 500, 480 + .enter = &intel_idle }, 481 + { 482 + .name = "C8-BDW", 483 + .desc = "MWAIT 0x40", 484 + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 485 + .exit_latency = 300, 486 + .target_residency = 900, 487 + .enter = &intel_idle }, 488 + { 489 + .name = "C9-BDW", 490 + .desc = "MWAIT 0x50", 491 + .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 492 + .exit_latency = 600, 493 + .target_residency = 1800, 494 + .enter = &intel_idle }, 495 + { 496 + .name = "C10-BDW", 497 + .desc = "MWAIT 0x60", 498 + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 499 + .exit_latency = 2600, 500 + .target_residency = 7700, 501 + .enter = &intel_idle }, 502 + { 503 + .enter = NULL } 504 + }; 446 505 447 506 static struct cpuidle_state atom_cstates[] = { 448 507 { ··· 674 613 static const struct idle_cpu idle_cpu_byt = { 675 614 .state_table = byt_cstates, 676 615 .disable_promotion_to_c1e = true, 616 + .byt_auto_demotion_disable_flag = true, 677 617 }; 678 618 679 619 static const struct idle_cpu idle_cpu_ivb = { ··· 689 627 690 628 static const struct idle_cpu idle_cpu_hsw = { 691 629 .state_table = hsw_cstates, 630 + .disable_promotion_to_c1e = true, 631 + }; 632 + 633 + static const struct idle_cpu idle_cpu_bdw = { 634 + .state_table = bdw_cstates, 692 635 .disable_promotion_to_c1e = true, 693 636 }; 694 637 ··· 725 658 ICPU(0x3f, idle_cpu_hsw), 726 659 ICPU(0x45, idle_cpu_hsw), 727 660 ICPU(0x46, idle_cpu_hsw), 728 - ICPU(0x4D, idle_cpu_avn), 661 + ICPU(0x4d, idle_cpu_avn), 662 + ICPU(0x3d, idle_cpu_bdw), 663 + ICPU(0x4f, idle_cpu_bdw), 664 + ICPU(0x56, idle_cpu_bdw), 729 665 {} 730 666 }; 731 667 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids); ··· 883 813 884 814 if (icpu->auto_demotion_disable_flags) 885 815 on_each_cpu(auto_demotion_disable, NULL, 1); 816 + 817 + if (icpu->byt_auto_demotion_disable_flag) { 818 + wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0); 819 + wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); 820 + } 886 821 887 822 if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */ 888 823 on_each_cpu(c1e_promotion_disable, NULL, 1);
+40 -40
tools/power/x86/turbostat/turbostat.c
··· 267 267 /* 268 268 * Example Format w/ field column widths: 269 269 * 270 - * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz SMI %Busy CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 CoreTmp PkgTmp Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt 271 - * 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 270 + * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz SMI %Busy CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 CoreTmp PkgTmp Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt 271 + * 123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678 272 272 */ 273 273 274 274 void print_header(void) 275 275 { 276 276 if (show_pkg) 277 - outp += sprintf(outp, "Package "); 277 + outp += sprintf(outp, " Package"); 278 278 if (show_core) 279 - outp += sprintf(outp, " Core "); 279 + outp += sprintf(outp, " Core"); 280 280 if (show_cpu) 281 - outp += sprintf(outp, " CPU "); 281 + outp += sprintf(outp, " CPU"); 282 282 if (has_aperf) 283 - outp += sprintf(outp, "Avg_MHz "); 283 + outp += sprintf(outp, " Avg_MHz"); 284 284 if (do_nhm_cstates) 285 - outp += sprintf(outp, " %%Busy "); 285 + outp += sprintf(outp, " %%Busy"); 286 286 if (has_aperf) 287 - outp += sprintf(outp, "Bzy_MHz "); 288 - outp += sprintf(outp, "TSC_MHz "); 287 + outp += sprintf(outp, " Bzy_MHz"); 288 + outp += sprintf(outp, " TSC_MHz"); 289 289 if (do_smi) 290 - outp += sprintf(outp, " SMI "); 290 + outp += sprintf(outp, " SMI"); 291 291 if (extra_delta_offset32) 292 - outp += sprintf(outp, " count 0x%03X ", extra_delta_offset32); 292 + outp += sprintf(outp, " count 0x%03X", extra_delta_offset32); 293 293 if (extra_delta_offset64) 294 - outp += sprintf(outp, " COUNT 0x%03X ", extra_delta_offset64); 294 + outp += sprintf(outp, " COUNT 0x%03X", extra_delta_offset64); 295 295 if (extra_msr_offset32) 296 - outp += sprintf(outp, " MSR 0x%03X ", extra_msr_offset32); 296 + outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset32); 297 297 if (extra_msr_offset64) 298 - outp += sprintf(outp, " MSR 0x%03X ", extra_msr_offset64); 298 + outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset64); 299 299 if (do_nhm_cstates) 300 - outp += sprintf(outp, " CPU%%c1 "); 300 + outp += sprintf(outp, " CPU%%c1"); 301 301 if (do_nhm_cstates && !do_slm_cstates) 302 - outp += sprintf(outp, " CPU%%c3 "); 302 + outp += sprintf(outp, " CPU%%c3"); 303 303 if (do_nhm_cstates) 304 - outp += sprintf(outp, " CPU%%c6 "); 304 + outp += sprintf(outp, " CPU%%c6"); 305 305 if (do_snb_cstates) 306 - outp += sprintf(outp, " CPU%%c7 "); 306 + outp += sprintf(outp, " CPU%%c7"); 307 307 308 308 if (do_dts) 309 - outp += sprintf(outp, "CoreTmp "); 309 + outp += sprintf(outp, " CoreTmp"); 310 310 if (do_ptm) 311 - outp += sprintf(outp, " PkgTmp "); 311 + outp += sprintf(outp, " PkgTmp"); 312 312 313 313 if (do_snb_cstates) 314 - outp += sprintf(outp, "Pkg%%pc2 "); 314 + outp += sprintf(outp, " Pkg%%pc2"); 315 315 if (do_nhm_cstates && !do_slm_cstates) 316 - outp += sprintf(outp, "Pkg%%pc3 "); 316 + outp += sprintf(outp, " Pkg%%pc3"); 317 317 if (do_nhm_cstates && !do_slm_cstates) 318 - outp += sprintf(outp, "Pkg%%pc6 "); 318 + outp += sprintf(outp, " Pkg%%pc6"); 319 319 if (do_snb_cstates) 320 - outp += sprintf(outp, "Pkg%%pc7 "); 320 + outp += sprintf(outp, " Pkg%%pc7"); 321 321 if (do_c8_c9_c10) { 322 - outp += sprintf(outp, "Pkg%%pc8 "); 323 - outp += sprintf(outp, "Pkg%%pc9 "); 324 - outp += sprintf(outp, "Pk%%pc10 "); 322 + outp += sprintf(outp, " Pkg%%pc8"); 323 + outp += sprintf(outp, " Pkg%%pc9"); 324 + outp += sprintf(outp, " Pk%%pc10"); 325 325 } 326 326 327 327 if (do_rapl && !rapl_joules) { 328 328 if (do_rapl & RAPL_PKG) 329 - outp += sprintf(outp, "PkgWatt "); 329 + outp += sprintf(outp, " PkgWatt"); 330 330 if (do_rapl & RAPL_CORES) 331 - outp += sprintf(outp, "CorWatt "); 331 + outp += sprintf(outp, " CorWatt"); 332 332 if (do_rapl & RAPL_GFX) 333 - outp += sprintf(outp, "GFXWatt "); 333 + outp += sprintf(outp, " GFXWatt"); 334 334 if (do_rapl & RAPL_DRAM) 335 - outp += sprintf(outp, "RAMWatt "); 335 + outp += sprintf(outp, " RAMWatt"); 336 336 if (do_rapl & RAPL_PKG_PERF_STATUS) 337 - outp += sprintf(outp, " PKG_%% "); 337 + outp += sprintf(outp, " PKG_%%"); 338 338 if (do_rapl & RAPL_DRAM_PERF_STATUS) 339 - outp += sprintf(outp, " RAM_%% "); 339 + outp += sprintf(outp, " RAM_%%"); 340 340 } else { 341 341 if (do_rapl & RAPL_PKG) 342 - outp += sprintf(outp, " Pkg_J "); 342 + outp += sprintf(outp, " Pkg_J"); 343 343 if (do_rapl & RAPL_CORES) 344 - outp += sprintf(outp, " Cor_J "); 344 + outp += sprintf(outp, " Cor_J"); 345 345 if (do_rapl & RAPL_GFX) 346 - outp += sprintf(outp, " GFX_J "); 346 + outp += sprintf(outp, " GFX_J"); 347 347 if (do_rapl & RAPL_DRAM) 348 - outp += sprintf(outp, " RAM_W "); 348 + outp += sprintf(outp, " RAM_W"); 349 349 if (do_rapl & RAPL_PKG_PERF_STATUS) 350 - outp += sprintf(outp, " PKG_%% "); 350 + outp += sprintf(outp, " PKG_%%"); 351 351 if (do_rapl & RAPL_DRAM_PERF_STATUS) 352 - outp += sprintf(outp, " RAM_%% "); 353 - outp += sprintf(outp, " time "); 352 + outp += sprintf(outp, " RAM_%%"); 353 + outp += sprintf(outp, " time"); 354 354 355 355 } 356 356 outp += sprintf(outp, "\n");