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dt-bindings: mailbox: Add bindings for RPMI shared memory transport
Add device tree bindings for the common RISC-V Platform Management
Interface (RPMI) shared memory transport as a mailbox controller.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-2-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
authored by
Anup Patel
and committed by
Paul Walmsley
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0b0ca959
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Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
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Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/riscv,rpmi-shmem-mbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V Platform Management Interface (RPMI) shared memory mailbox
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maintainers:
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- Anup Patel <anup@brainfault.org>
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description: |
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The RISC-V Platform Management Interface (RPMI) [1] defines a common shared
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memory based RPMI transport. This RPMI shared memory transport integrates as
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mailbox controller in the SBI implementation or supervisor software whereas
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each RPMI service group is mailbox client in the SBI implementation and
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supervisor software.
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===========================================
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References
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===========================================
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[1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher)
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https://github.com/riscv-non-isa/riscv-rpmi/releases
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properties:
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compatible:
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const: riscv,rpmi-shmem-mbox
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reg:
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minItems: 2
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items:
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- description: A2P request queue base address
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- description: P2A acknowledgment queue base address
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- description: P2A request queue base address
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- description: A2P acknowledgment queue base address
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- description: A2P doorbell address
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reg-names:
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minItems: 2
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items:
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- const: a2p-req
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- const: p2a-ack
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- enum: [ p2a-req, a2p-doorbell ]
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- const: a2p-ack
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- const: a2p-doorbell
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interrupts:
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maxItems: 1
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description:
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The RPMI shared memory transport supports P2A doorbell as a wired
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interrupt and this property specifies the interrupt source.
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msi-parent:
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description:
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The RPMI shared memory transport supports P2A doorbell as a system MSI
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and this property specifies the target MSI controller.
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riscv,slot-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 64
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description:
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Power-of-2 RPMI slot size of the RPMI shared memory transport.
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riscv,a2p-doorbell-value:
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0x1
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description:
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Value written to the 32-bit A2P doorbell register.
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riscv,p2a-doorbell-sysmsi-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The RPMI shared memory transport supports P2A doorbell as a system MSI
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and this property specifies system MSI index to be used for configuring
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the P2A doorbell MSI.
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"#mbox-cells":
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const: 1
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description:
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The first cell specifies RPMI service group ID.
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required:
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- compatible
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- reg
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- reg-names
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- riscv,slot-size
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- "#mbox-cells"
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anyOf:
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- required:
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- interrupts
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- required:
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- msi-parent
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additionalProperties: false
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examples:
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- |
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// Example 1 (RPMI shared memory with only 2 queues):
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mailbox@10080000 {
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compatible = "riscv,rpmi-shmem-mbox";
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reg = <0x10080000 0x10000>,
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<0x10090000 0x10000>;
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reg-names = "a2p-req", "p2a-ack";
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msi-parent = <&imsic_mlevel>;
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riscv,slot-size = <64>;
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#mbox-cells = <1>;
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};
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- |
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// Example 2 (RPMI shared memory with only 4 queues):
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mailbox@10001000 {
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compatible = "riscv,rpmi-shmem-mbox";
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reg = <0x10001000 0x800>,
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<0x10001800 0x800>,
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<0x10002000 0x800>,
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<0x10002800 0x800>,
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<0x10003000 0x4>;
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reg-names = "a2p-req", "p2a-ack", "p2a-req", "a2p-ack", "a2p-doorbell";
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msi-parent = <&imsic_mlevel>;
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riscv,slot-size = <64>;
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riscv,a2p-doorbell-value = <0x00008000>;
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#mbox-cells = <1>;
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};