Merge tag 'cleanup-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup

-1

arch/arm/Kconfig

··· 1175 1175 config ARM_TIMER_SP804 1176 1176 bool 1177 1177 select CLKSRC_MMIO 1178 - select HAVE_SCHED_CLOCK 1179 1178 1180 1179 source arch/arm/mm/Kconfig 1181 1180

+1 -12

arch/arm/mach-exynos/Kconfig

··· 95 95 help 96 96 Compile in platform device definitions for AHCI 97 97 98 - config EXYNOS_DEV_DRM 99 - bool 100 - help 101 - Compile in platform device definitions for core DRM device 102 - 103 98 config EXYNOS4_SETUP_FIMD0 104 99 bool 105 100 help ··· 194 199 select EXYNOS4_SETUP_SDHCI 195 200 select EXYNOS4_SETUP_USB_PHY 196 201 select EXYNOS_DEV_DMA 197 - select EXYNOS_DEV_DRM 198 202 select EXYNOS_DEV_SYSMMU 199 203 select S3C24XX_PWM 200 204 select S3C_DEV_HSMMC ··· 247 253 select EXYNOS4_SETUP_SDHCI 248 254 select EXYNOS4_SETUP_USB_PHY 249 255 select EXYNOS_DEV_DMA 250 - select EXYNOS_DEV_DRM 251 256 select EXYNOS_DEV_SYSMMU 252 - select HAVE_SCHED_CLOCK 253 257 select S3C_DEV_HSMMC 254 258 select S3C_DEV_HSMMC2 255 259 select S3C_DEV_HSMMC3 ··· 286 294 select EXYNOS4_SETUP_SDHCI 287 295 select EXYNOS4_SETUP_USB_PHY 288 296 select EXYNOS_DEV_DMA 289 - select EXYNOS_DEV_DRM 290 297 select S3C_DEV_HSMMC 291 298 select S3C_DEV_HSMMC2 292 299 select S3C_DEV_HSMMC3 ··· 321 330 select EXYNOS4_SETUP_SDHCI 322 331 select EXYNOS4_SETUP_USB_PHY 323 332 select EXYNOS_DEV_DMA 324 - select EXYNOS_DEV_DRM 325 333 select EXYNOS_DEV_SYSMMU 326 334 select S3C24XX_PWM 327 335 select S3C_DEV_HSMMC ··· 356 366 select EXYNOS4_SETUP_SDHCI 357 367 select EXYNOS4_SETUP_USB_PHY 358 368 select EXYNOS_DEV_DMA 359 - select EXYNOS_DEV_DRM 360 369 select EXYNOS_DEV_SYSMMU 361 370 select S3C24XX_PWM 362 371 select S3C_DEV_HSMMC2 ··· 396 407 depends on ARCH_EXYNOS4 397 408 select ARM_AMBA 398 409 select CPU_EXYNOS4210 399 - select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD 410 + select KEYBOARD_SAMSUNG if INPUT_KEYBOARD 400 411 select PINCTRL 401 412 select PINCTRL_EXYNOS 402 413 select USE_OF

-1

arch/arm/mach-exynos/common.c

··· 23 23 #include <linux/of_irq.h> 24 24 #include <linux/export.h> 25 25 #include <linux/irqdomain.h> 26 - #include <linux/irqchip.h> 27 26 #include <linux/of_address.h> 28 27 #include <linux/irqchip/arm-gic.h> 29 28 #include <linux/irqchip/chained_irq.h>

+1 -1

arch/arm/mach-exynos/dev-ohci.c

··· 12 12 13 13 #include <linux/dma-mapping.h> 14 14 #include <linux/platform_device.h> 15 - #include <linux/platform_data/usb-exynos.h> 15 + #include <linux/platform_data/usb-ohci-exynos.h> 16 16 17 17 #include <mach/irqs.h> 18 18 #include <mach/map.h>

+1 -1

arch/arm/mach-exynos/mach-origen.c

··· 26 26 #include <linux/platform_data/i2c-s3c2410.h> 27 27 #include <linux/platform_data/s3c-hsotg.h> 28 28 #include <linux/platform_data/usb-ehci-s5p.h> 29 - #include <linux/platform_data/usb-exynos.h> 29 + #include <linux/platform_data/usb-ohci-exynos.h> 30 30 31 31 #include <asm/mach/arch.h> 32 32 #include <asm/mach-types.h>

+1 -1

arch/arm/mach-exynos/mach-smdkv310.c

··· 23 23 #include <linux/platform_data/i2c-s3c2410.h> 24 24 #include <linux/platform_data/s3c-hsotg.h> 25 25 #include <linux/platform_data/usb-ehci-s5p.h> 26 - #include <linux/platform_data/usb-exynos.h> 26 + #include <linux/platform_data/usb-ohci-exynos.h> 27 27 28 28 #include <asm/mach/arch.h> 29 29 #include <asm/mach-types.h>

+6 -16

arch/arm/mach-s3c24xx/Kconfig

··· 36 36 37 37 config CPU_S3C2412 38 38 bool "SAMSUNG S3C2412" 39 - depends on ARCH_S3C24XX 40 39 select CPU_ARM926T 41 40 select CPU_LLSERIAL_S3C2440 42 41 select S3C2412_DMA if S3C24XX_DMA ··· 45 46 46 47 config CPU_S3C2416 47 48 bool "SAMSUNG S3C2416/S3C2450" 48 - depends on ARCH_S3C24XX 49 49 select CPU_ARM926T 50 50 select CPU_LLSERIAL_S3C2440 51 51 select S3C2416_PM if PM ··· 79 81 80 82 config CPU_S3C2443 81 83 bool "SAMSUNG S3C2443" 82 - depends on ARCH_S3C24XX 83 84 select CPU_ARM920T 84 85 select CPU_LLSERIAL_S3C2440 85 86 select S3C2443_COMMON ··· 130 133 131 134 config S3C24XX_DMA 132 135 bool "S3C2410 DMA support" 133 - depends on ARCH_S3C24XX 134 136 select S3C_DMA 135 137 help 136 138 S3C2410 DMA support. This is needed for drivers like sound which ··· 138 142 139 143 config S3C2410_DMA_DEBUG 140 144 bool "S3C2410 DMA support debug" 141 - depends on ARCH_S3C24XX && S3C2410_DMA 145 + depends on S3C2410_DMA 142 146 help 143 147 Enable debugging output for the DMA code. This option sends info 144 148 to the kernel log, at priority KERN_DEBUG. ··· 229 233 230 234 config S3C2410_CPUFREQ 231 235 bool 232 - depends on CPU_FREQ_S3C24XX && CPU_S3C2410 236 + depends on CPU_FREQ_S3C24XX 233 237 select S3C2410_CPUFREQ_UTILS 234 238 help 235 239 CPU Frequency scaling support for S3C2410 ··· 316 320 317 321 config MACH_N30 318 322 bool "Acer N30 family" 319 - select MACH_N35 320 323 select S3C_DEV_NAND 321 324 select S3C_DEV_USB_HOST 322 325 help ··· 375 380 376 381 config CPU_S3C2412_ONLY 377 382 bool 378 - depends on ARCH_S3C24XX && !CPU_S3C2410 && \ 379 - !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \ 380 - !CPU_S3C2443 && CPU_S3C2412 383 + depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \ 384 + !CPU_S3C2442 && !CPU_S3C2443 381 385 default y 382 386 383 387 config S3C2412_CPUFREQ 384 388 bool 385 - depends on CPU_FREQ_S3C24XX && CPU_S3C2412 389 + depends on CPU_FREQ_S3C24XX 386 390 default y 387 391 select S3C2412_IOTIMING 388 392 help ··· 636 642 config MACH_NEO1973_GTA02 637 643 bool "Openmoko GTA02 / Freerunner phone" 638 644 select I2C 639 - select MACH_NEO1973 640 645 select MFD_PCF50633 641 646 select PCF50633_GPIO 642 647 select POWER_SUPPLY ··· 656 663 help 657 664 Say Y here if you're using HP iPAQ rx1950 658 665 659 - config SMDK2440_CPU2442 660 - bool "SMDM2440 with S3C2442 CPU module" 661 - 662 - endif # CPU_S3C2440 666 + endif # CPU_S3C2442 663 667 664 668 if CPU_S3C2443 || CPU_S3C2416 665 669

-1

arch/arm/mach-s3c24xx/include/mach/dma.h

··· 24 24 */ 25 25 26 26 enum dma_ch { 27 - DMACH_DT_PROP = -1, /* not yet supported, do not use */ 28 27 DMACH_XD0 = 0, 29 28 DMACH_XD1, 30 29 DMACH_SDI,

+4 -199

arch/arm/mach-s3c24xx/regs-dsc.h

··· 1 - /* arch/arm/mach-s3c2410/include/mach/regs-dsc.h 2 - * 1 + /* 3 2 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> 4 3 * http://www.simtec.co.uk/products/SWLINUX/ 5 4 * ··· 11 12 12 13 13 14 #ifndef __ASM_ARCH_REGS_DSC_H 14 - #define __ASM_ARCH_REGS_DSC_H "2440-dsc" 15 + #define __ASM_ARCH_REGS_DSC_H __FILE__ 15 16 16 - #if defined(CONFIG_CPU_S3C2412) 17 + /* S3C2412 */ 17 18 #define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) 18 19 #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) 19 - #endif 20 20 21 - #if defined(CONFIG_CPU_S3C2416) 22 - #define S3C2416_DSC0 S3C2410_GPIOREG(0xc0) 23 - #define S3C2416_DSC1 S3C2410_GPIOREG(0xc4) 24 - #define S3C2416_DSC2 S3C2410_GPIOREG(0xc8) 25 - #define S3C2416_DSC3 S3C2410_GPIOREG(0x110) 26 - 27 - #define S3C2416_SELECT_DSC0 (0 << 30) 28 - #define S3C2416_SELECT_DSC1 (1 << 30) 29 - #define S3C2416_SELECT_DSC2 (2 << 30) 30 - #define S3C2416_SELECT_DSC3 (3 << 30) 31 - 32 - #define S3C2416_DSC_GETSHIFT(x) (x & 30) 33 - 34 - #define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28) 35 - #define S3C2416_DSC0_CF_5mA (0 << 28) 36 - #define S3C2416_DSC0_CF_10mA (1 << 28) 37 - #define S3C2416_DSC0_CF_15mA (2 << 28) 38 - #define S3C2416_DSC0_CF_21mA (3 << 28) 39 - #define S3C2416_DSC0_CF_MASK (3 << 28) 40 - 41 - #define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26) 42 - #define S3C2416_DSC0_nRBE_5mA (0 << 26) 43 - #define S3C2416_DSC0_nRBE_10mA (1 << 26) 44 - #define S3C2416_DSC0_nRBE_15mA (2 << 26) 45 - #define S3C2416_DSC0_nRBE_21mA (3 << 26) 46 - #define S3C2416_DSC0_nRBE_MASK (3 << 26) 47 - 48 - #define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24) 49 - #define S3C2416_DSC0_nROE_5mA (0 << 24) 50 - #define S3C2416_DSC0_nROE_10mA (1 << 24) 51 - #define S3C2416_DSC0_nROE_15mA (2 << 24) 52 - #define S3C2416_DSC0_nROE_21mA (3 << 24) 53 - #define S3C2416_DSC0_nROE_MASK (3 << 24) 54 - 55 - #endif 56 - 57 - #if defined(CONFIG_CPU_S3C244X) 58 - 21 + /* S3C2440 */ 59 22 #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) 60 23 #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) 61 - 62 - #define S3C2440_SELECT_DSC0 (0) 63 - #define S3C2440_SELECT_DSC1 (1<<31) 64 - 65 - #define S3C2440_DSC_GETSHIFT(x) ((x) & 31) 66 - 67 - #define S3C2440_DSC0_DISABLE (1<<31) 68 - 69 - #define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8) 70 - #define S3C2440_DSC0_ADDR_12mA (0<<8) 71 - #define S3C2440_DSC0_ADDR_10mA (1<<8) 72 - #define S3C2440_DSC0_ADDR_8mA (2<<8) 73 - #define S3C2440_DSC0_ADDR_6mA (3<<8) 74 - #define S3C2440_DSC0_ADDR_MASK (3<<8) 75 - 76 - /* D24..D31 */ 77 - #define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6) 78 - #define S3C2440_DSC0_DATA3_12mA (0<<6) 79 - #define S3C2440_DSC0_DATA3_10mA (1<<6) 80 - #define S3C2440_DSC0_DATA3_8mA (2<<6) 81 - #define S3C2440_DSC0_DATA3_6mA (3<<6) 82 - #define S3C2440_DSC0_DATA3_MASK (3<<6) 83 - 84 - /* D16..D23 */ 85 - #define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4) 86 - #define S3C2440_DSC0_DATA2_12mA (0<<4) 87 - #define S3C2440_DSC0_DATA2_10mA (1<<4) 88 - #define S3C2440_DSC0_DATA2_8mA (2<<4) 89 - #define S3C2440_DSC0_DATA2_6mA (3<<4) 90 - #define S3C2440_DSC0_DATA2_MASK (3<<4) 91 - 92 - /* D8..D15 */ 93 - #define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2) 94 - #define S3C2440_DSC0_DATA1_12mA (0<<2) 95 - #define S3C2440_DSC0_DATA1_10mA (1<<2) 96 - #define S3C2440_DSC0_DATA1_8mA (2<<2) 97 - #define S3C2440_DSC0_DATA1_6mA (3<<2) 98 - #define S3C2440_DSC0_DATA1_MASK (3<<2) 99 - 100 - /* D0..D7 */ 101 - #define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0) 102 - #define S3C2440_DSC0_DATA0_12mA (0<<0) 103 - #define S3C2440_DSC0_DATA0_10mA (1<<0) 104 - #define S3C2440_DSC0_DATA0_8mA (2<<0) 105 - #define S3C2440_DSC0_DATA0_6mA (3<<0) 106 - #define S3C2440_DSC0_DATA0_MASK (3<<0) 107 - 108 - #define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28) 109 - #define S3C2440_DSC1_SCK1_12mA (0<<28) 110 - #define S3C2440_DSC1_SCK1_10mA (1<<28) 111 - #define S3C2440_DSC1_SCK1_8mA (2<<28) 112 - #define S3C2440_DSC1_SCK1_6mA (3<<28) 113 - #define S3C2440_DSC1_SCK1_MASK (3<<28) 114 - 115 - #define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26) 116 - #define S3C2440_DSC1_SCK0_12mA (0<<26) 117 - #define S3C2440_DSC1_SCK0_10mA (1<<26) 118 - #define S3C2440_DSC1_SCK0_8mA (2<<26) 119 - #define S3C2440_DSC1_SCK0_6mA (3<<26) 120 - #define S3C2440_DSC1_SCK0_MASK (3<<26) 121 - 122 - #define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24) 123 - #define S3C2440_DSC1_SCKE_10mA (0<<24) 124 - #define S3C2440_DSC1_SCKE_8mA (1<<24) 125 - #define S3C2440_DSC1_SCKE_6mA (2<<24) 126 - #define S3C2440_DSC1_SCKE_4mA (3<<24) 127 - #define S3C2440_DSC1_SCKE_MASK (3<<24) 128 - 129 - /* SDRAM nRAS/nCAS */ 130 - #define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22) 131 - #define S3C2440_DSC1_SDR_10mA (0<<22) 132 - #define S3C2440_DSC1_SDR_8mA (1<<22) 133 - #define S3C2440_DSC1_SDR_6mA (2<<22) 134 - #define S3C2440_DSC1_SDR_4mA (3<<22) 135 - #define S3C2440_DSC1_SDR_MASK (3<<22) 136 - 137 - /* NAND Flash Controller */ 138 - #define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20) 139 - #define S3C2440_DSC1_NFC_10mA (0<<20) 140 - #define S3C2440_DSC1_NFC_8mA (1<<20) 141 - #define S3C2440_DSC1_NFC_6mA (2<<20) 142 - #define S3C2440_DSC1_NFC_4mA (3<<20) 143 - #define S3C2440_DSC1_NFC_MASK (3<<20) 144 - 145 - /* nBE[0..3] */ 146 - #define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18) 147 - #define S3C2440_DSC1_nBE_10mA (0<<18) 148 - #define S3C2440_DSC1_nBE_8mA (1<<18) 149 - #define S3C2440_DSC1_nBE_6mA (2<<18) 150 - #define S3C2440_DSC1_nBE_4mA (3<<18) 151 - #define S3C2440_DSC1_nBE_MASK (3<<18) 152 - 153 - #define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16) 154 - #define S3C2440_DSC1_WOE_10mA (0<<16) 155 - #define S3C2440_DSC1_WOE_8mA (1<<16) 156 - #define S3C2440_DSC1_WOE_6mA (2<<16) 157 - #define S3C2440_DSC1_WOE_4mA (3<<16) 158 - #define S3C2440_DSC1_WOE_MASK (3<<16) 159 - 160 - #define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14) 161 - #define S3C2440_DSC1_CS7_10mA (0<<14) 162 - #define S3C2440_DSC1_CS7_8mA (1<<14) 163 - #define S3C2440_DSC1_CS7_6mA (2<<14) 164 - #define S3C2440_DSC1_CS7_4mA (3<<14) 165 - #define S3C2440_DSC1_CS7_MASK (3<<14) 166 - 167 - #define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12) 168 - #define S3C2440_DSC1_CS6_10mA (0<<12) 169 - #define S3C2440_DSC1_CS6_8mA (1<<12) 170 - #define S3C2440_DSC1_CS6_6mA (2<<12) 171 - #define S3C2440_DSC1_CS6_4mA (3<<12) 172 - #define S3C2440_DSC1_CS6_MASK (3<<12) 173 - 174 - #define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10) 175 - #define S3C2440_DSC1_CS5_10mA (0<<10) 176 - #define S3C2440_DSC1_CS5_8mA (1<<10) 177 - #define S3C2440_DSC1_CS5_6mA (2<<10) 178 - #define S3C2440_DSC1_CS5_4mA (3<<10) 179 - #define S3C2440_DSC1_CS5_MASK (3<<10) 180 - 181 - #define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8) 182 - #define S3C2440_DSC1_CS4_10mA (0<<8) 183 - #define S3C2440_DSC1_CS4_8mA (1<<8) 184 - #define S3C2440_DSC1_CS4_6mA (2<<8) 185 - #define S3C2440_DSC1_CS4_4mA (3<<8) 186 - #define S3C2440_DSC1_CS4_MASK (3<<8) 187 - 188 - #define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6) 189 - #define S3C2440_DSC1_CS3_10mA (0<<6) 190 - #define S3C2440_DSC1_CS3_8mA (1<<6) 191 - #define S3C2440_DSC1_CS3_6mA (2<<6) 192 - #define S3C2440_DSC1_CS3_4mA (3<<6) 193 - #define S3C2440_DSC1_CS3_MASK (3<<6) 194 - 195 - #define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4) 196 - #define S3C2440_DSC1_CS2_10mA (0<<4) 197 - #define S3C2440_DSC1_CS2_8mA (1<<4) 198 - #define S3C2440_DSC1_CS2_6mA (2<<4) 199 - #define S3C2440_DSC1_CS2_4mA (3<<4) 200 - #define S3C2440_DSC1_CS2_MASK (3<<4) 201 - 202 - #define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2) 203 - #define S3C2440_DSC1_CS1_10mA (0<<2) 204 - #define S3C2440_DSC1_CS1_8mA (1<<2) 205 - #define S3C2440_DSC1_CS1_6mA (2<<2) 206 - #define S3C2440_DSC1_CS1_4mA (3<<2) 207 - #define S3C2440_DSC1_CS1_MASK (3<<2) 208 - 209 - #define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0) 210 - #define S3C2440_DSC1_CS0_10mA (0<<0) 211 - #define S3C2440_DSC1_CS0_8mA (1<<0) 212 - #define S3C2440_DSC1_CS0_6mA (2<<0) 213 - #define S3C2440_DSC1_CS0_4mA (3<<0) 214 - #define S3C2440_DSC1_CS0_MASK (3<<0) 215 - 216 - #endif /* CONFIG_CPU_S3C2440 */ 217 24 218 25 #endif /* __ASM_ARCH_REGS_DSC_H */ 219 26

-1

arch/arm/mach-s3c64xx/Makefile

··· 32 32 33 33 obj-y += dev-uart.o 34 34 obj-y += dev-audio.o 35 - obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o 36 35 37 36 # Device setup 38 37

-1

arch/arm/mach-s3c64xx/include/mach/dma.h

··· 21 21 */ 22 22 enum dma_ch { 23 23 /* DMA0/SDMA0 */ 24 - DMACH_DT_PROP = -1, /* not yet supported, do not use */ 25 24 DMACH_UART0 = 0, 26 25 DMACH_UART0_SRC2, 27 26 DMACH_UART1,

-14

arch/arm/plat-samsung/Kconfig

··· 37 37 38 38 comment "Boot options" 39 39 40 - config S3C_BOOT_WATCHDOG 41 - bool "S3C Initialisation watchdog" 42 - depends on S3C2410_WATCHDOG 43 - help 44 - Say y to enable the watchdog during the kernel decompression 45 - stage. If the kernel fails to uncompress, then the watchdog 46 - will trigger a reset and the system should restart. 47 - 48 40 config S3C_BOOT_ERROR_RESET 49 41 bool "S3C Reboot on decompression error" 50 42 help ··· 116 124 GPIOlib file contains the 4 bit modification functions for gpio 117 125 configuration. GPIOlib shall be compiled only for S3C64XX and S5P 118 126 series of processors. 119 - 120 - config S3C_GPIO_CFG_S3C64XX 121 - bool 122 - help 123 - Internal configuration to enable S3C64XX style GPIO configuration 124 - functions. 125 127 126 128 config S5P_GPIO_DRVSTR 127 129 bool

+1 -9

arch/arm/plat-samsung/dma-ops.c

··· 23 23 struct device *dev, char *ch_name) 24 24 { 25 25 dma_cap_mask_t mask; 26 - void *filter_param; 27 26 28 27 dma_cap_zero(mask); 29 28 dma_cap_set(param->cap, mask); 30 - 31 - /* 32 - * If a dma channel property of a device node from device tree is 33 - * specified, use that as the fliter parameter. 34 - */ 35 - filter_param = (dma_ch == DMACH_DT_PROP) ? 36 - (void *)param->dt_dmach_prop : (void *)dma_ch; 37 29 38 30 if (dev->of_node) 39 31 return (unsigned)dma_request_slave_channel(dev, ch_name); 40 32 else 41 33 return (unsigned)dma_request_channel(mask, pl330_filter, 42 - filter_param); 34 + (void *)dma_ch); 43 35 } 44 36 45 37 static int samsung_dmadev_release(unsigned ch, void *param)

-1

arch/arm/plat-samsung/include/plat/dma-ops.h

··· 18 18 19 19 struct samsung_dma_req { 20 20 enum dma_transaction_type cap; 21 - struct property *dt_dmach_prop; 22 21 struct s3c2410_dma_client *client; 23 22 }; 24 23

-1

arch/arm/plat-samsung/include/plat/dma-pl330.h

··· 21 21 * use these just as IDs. 22 22 */ 23 23 enum dma_ch { 24 - DMACH_DT_PROP = -1, 25 24 DMACH_UART0_RX = 0, 26 25 DMACH_UART0_TX, 27 26 DMACH_UART1_RX,

+1 -1

arch/arm/plat-samsung/include/plat/rtc-core.h

··· 19 19 /* re-define device name depending on support. */ 20 20 static inline void s3c_rtc_setname(char *name) 21 21 { 22 - #if defined(CONFIG_SAMSUNG_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX) 22 + #if defined(CONFIG_S3C_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX) 23 23 s3c_device_rtc.name = name; 24 24 #endif 25 25 }

+2 -2

arch/arm/plat-samsung/include/plat/sdhci.h

··· 206 206 207 207 /* S5P64X0 SDHCI setup */ 208 208 209 - #ifdef CONFIG_S5P64X0_SETUP_SDHCI 209 + #ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO 210 210 static inline void s5p64x0_default_sdhci0(void) 211 211 { 212 212 #ifdef CONFIG_S3C_DEV_HSMMC ··· 241 241 static inline void s5p6440_default_sdhci2(void) { } 242 242 static inline void s5p6450_default_sdhci2(void) { } 243 243 244 - #endif /* CONFIG_S5P64X0_SETUP_SDHCI */ 244 + #endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */ 245 245 246 246 /* S5PC100 SDHCI setup */ 247 247

+2 -1

drivers/usb/host/ohci-exynos.c

··· 14 14 #include <linux/clk.h> 15 15 #include <linux/of.h> 16 16 #include <linux/platform_device.h> 17 - #include <linux/platform_data/usb-exynos.h> 17 + #include <linux/platform_data/usb-ohci-exynos.h> 18 18 #include <linux/usb/phy.h> 19 19 #include <linux/usb/samsung_usb_phy.h> 20 + 20 21 #include <plat/usb-phy.h> 21 22 22 23 struct exynos_ohci_hcd {

include/linux/platform_data/usb-exynos.h include/linux/platform_data/usb-ohci-exynos.h