MIPS: ingenic: Hardcode mem size for qi,lb60 board

Old Device Tree for the qi,lb60 (aka. Ben Nanonote) did not have a
'memory' node. The kernel would then read the memory controller
registers to know how much RAM was available.

Since every other supported board has had a 'memory' node from the
beginning, we can just hardcode a RAM size of 32 MiB when running with
an old Device Tree without the 'memory' node.

Signed-off-by: Paul Cercueil <[e-mail]>
Signed-off-by: Thomas Bogendoerfer <[e-mail]>

arch/mips/jz4740/setup.c

···
 #include <linux/of_clk.h>
 #include <linux/of_fdt.h>
 #include <linux/pm.h>
+#include <linux/sizes.h>
 #include <linux/suspend.h>
 
 #include <asm/bootinfo.h>
···
 #include <asm/prom.h>
 #include <asm/reboot.h>
 #include <asm/time.h>
-
-#define JZ4740_EMC_BASE_ADDR 0x13010000
-
-#define JZ4740_EMC_SDRAM_CTRL 0x80
-
-static void __init jz4740_detect_mem(void)
-{
-	void __iomem *jz_emc_base;
-	u32 ctrl, bus, bank, rows, cols;
-	phys_addr_t size;
-
-	jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100);
-	ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL);
-	bus = 2 - ((ctrl >> 31) & 1);
-	bank = 1 + ((ctrl >> 19) & 1);
-	cols = 8 + ((ctrl >> 26) & 7);
-	rows = 11 + ((ctrl >> 20) & 3);
-	printk(KERN_DEBUG
-		"SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n",
-		bus, bank, rows, cols);
-	iounmap(jz_emc_base);
-
-	size = 1 << (bus + bank + cols + rows);
-	add_memory_region(0, size, BOOT_MEM_RAM);
-}
 
 static unsigned long __init get_board_mach_type(const void *fdt)
 {
···
 void __init plat_mem_setup(void)
 {
 	void *dtb = (void *)fw_passed_dtb;
-	int offset;
 
 	__dt_setup_arch(dtb);
 
-	offset = fdt_path_offset(dtb, "/memory");
-	if (offset < 0)
-		jz4740_detect_mem();
+	/*
+	 * Old devicetree files for the qi,lb60 board did not have a /memory
+	 * node. Hardcode the memory info here.
+	 */
+	if (!fdt_node_check_compatible(dtb, 0, "qi,lb60") &&
+	    fdt_path_offset(dtb, "/memory") < 0)
+		early_init_dt_add_memory_arch(0, SZ_32M);
 
 	mips_machtype = get_board_mach_type(dtb);
 }