tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/ttm: nuke memory type flags

It's not supported to specify more than one of those flags.
So it never made sense to make this a flag in the first place.

Nuke the flags and specify directly which memory type to use.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/389826/?series=81551&rev=1

Christian König 48e07c23 e03d342c

+150 -192
+15 -9
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
··· 136 136 137 137 places[c].fpfn = 0; 138 138 places[c].lpfn = 0; 139 - places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 140 - TTM_PL_FLAG_VRAM; 139 + places[c].mem_type = TTM_PL_VRAM; 140 + places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED; 141 141 142 142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 143 143 places[c].lpfn = visible_pfn; ··· 152 152 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 153 153 places[c].fpfn = 0; 154 154 places[c].lpfn = 0; 155 - places[c].flags = TTM_PL_FLAG_TT; 155 + places[c].mem_type = TTM_PL_TT; 156 + places[c].flags = 0; 156 157 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 157 158 places[c].flags |= TTM_PL_FLAG_WC | 158 159 TTM_PL_FLAG_UNCACHED; ··· 165 164 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 166 165 places[c].fpfn = 0; 167 166 places[c].lpfn = 0; 168 - places[c].flags = TTM_PL_FLAG_SYSTEM; 167 + places[c].mem_type = TTM_PL_SYSTEM; 168 + places[c].flags = 0; 169 169 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 170 170 places[c].flags |= TTM_PL_FLAG_WC | 171 171 TTM_PL_FLAG_UNCACHED; ··· 178 176 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 179 177 places[c].fpfn = 0; 180 178 places[c].lpfn = 0; 181 - places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 179 + places[c].mem_type = AMDGPU_PL_GDS; 180 + places[c].flags = TTM_PL_FLAG_UNCACHED; 182 181 c++; 183 182 } 184 183 185 184 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 186 185 places[c].fpfn = 0; 187 186 places[c].lpfn = 0; 188 - places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 187 + places[c].mem_type = AMDGPU_PL_GWS; 188 + places[c].flags = TTM_PL_FLAG_UNCACHED; 189 189 c++; 190 190 } 191 191 192 192 if (domain & AMDGPU_GEM_DOMAIN_OA) { 193 193 places[c].fpfn = 0; 194 194 places[c].lpfn = 0; 195 - places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 195 + places[c].mem_type = AMDGPU_PL_OA; 196 + places[c].flags = TTM_PL_FLAG_UNCACHED; 196 197 c++; 197 198 } 198 199 199 200 if (!c) { 200 201 places[c].fpfn = 0; 201 202 places[c].lpfn = 0; 202 - places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 203 + places[c].mem_type = TTM_PL_SYSTEM; 204 + places[c].flags = TTM_PL_MASK_CACHING; 203 205 c++; 204 206 } 205 207 ··· 597 591 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 598 592 599 593 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 600 - bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 594 + bo->tbo.mem.mem_type == TTM_PL_VRAM) { 601 595 struct dma_fence *fence; 602 596 603 597 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);
+8 -5
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 88 88 static const struct ttm_place placements = { 89 89 .fpfn = 0, 90 90 .lpfn = 0, 91 - .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 91 + .mem_type = TTM_PL_SYSTEM, 92 + .flags = TTM_PL_MASK_CACHING 92 93 }; 93 94 94 95 /* Don't handle scatter gather BOs */ ··· 534 533 placement.busy_placement = &placements; 535 534 placements.fpfn = 0; 536 535 placements.lpfn = 0; 537 - placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 536 + placements.mem_type = TTM_PL_TT; 537 + placements.flags = TTM_PL_MASK_CACHING; 538 538 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 539 539 if (unlikely(r)) { 540 540 pr_err("Failed to find GTT space for blit from VRAM\n"); ··· 591 589 placement.busy_placement = &placements; 592 590 placements.fpfn = 0; 593 591 placements.lpfn = 0; 594 - placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 592 + placements.mem_type = TTM_PL_TT; 593 + placements.flags = TTM_PL_MASK_CACHING; 595 594 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); 596 595 if (unlikely(r)) { 597 596 pr_err("Failed to find GTT space for blit to VRAM\n"); ··· 1174 1171 placement.busy_placement = &placements; 1175 1172 placements.fpfn = 0; 1176 1173 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 1177 - placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | 1178 - TTM_PL_FLAG_TT; 1174 + placements.mem_type = TTM_PL_TT; 1175 + placements.flags = bo->mem.placement; 1179 1176 1180 1177 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 1181 1178 if (unlikely(r))
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
··· 32 32 #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) 33 33 #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) 34 34 35 - #define AMDGPU_PL_FLAG_GDS (TTM_PL_FLAG_PRIV << 0) 36 - #define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1) 37 - #define AMDGPU_PL_FLAG_OA (TTM_PL_FLAG_PRIV << 2) 38 - 39 35 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 40 36 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 41 37
+6 -9
drivers/gpu/drm/drm_gem_vram_helper.c
··· 145 145 gbo->placement.placement = gbo->placements; 146 146 gbo->placement.busy_placement = gbo->placements; 147 147 148 - if (pl_flag & DRM_GEM_VRAM_PL_FLAG_VRAM) 148 + if (pl_flag & DRM_GEM_VRAM_PL_FLAG_VRAM) { 149 + gbo->placements[c].mem_type = TTM_PL_VRAM; 149 150 gbo->placements[c++].flags = TTM_PL_FLAG_WC | 150 151 TTM_PL_FLAG_UNCACHED | 151 - TTM_PL_FLAG_VRAM | 152 152 invariant_flags; 153 + } 153 154 154 - if (pl_flag & DRM_GEM_VRAM_PL_FLAG_SYSTEM) 155 + if (pl_flag & DRM_GEM_VRAM_PL_FLAG_SYSTEM || !c) { 156 + gbo->placements[c].mem_type = TTM_PL_SYSTEM; 155 157 gbo->placements[c++].flags = TTM_PL_MASK_CACHING | 156 - TTM_PL_FLAG_SYSTEM | 157 158 invariant_flags; 158 - 159 - if (!c) 160 - gbo->placements[c++].flags = TTM_PL_MASK_CACHING | 161 - TTM_PL_FLAG_SYSTEM | 162 - invariant_flags; 159 + } 163 160 164 161 gbo->placement.num_placement = c; 165 162 gbo->placement.num_busy_placement = c;
+16 -8
drivers/gpu/drm/nouveau/nouveau_bo.c
··· 345 345 { 346 346 *n = 0; 347 347 348 - if (domain & NOUVEAU_GEM_DOMAIN_VRAM) 349 - pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; 350 - if (domain & NOUVEAU_GEM_DOMAIN_GART) 351 - pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; 352 - if (domain & NOUVEAU_GEM_DOMAIN_CPU) 353 - pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; 348 + if (domain & NOUVEAU_GEM_DOMAIN_VRAM) { 349 + pl[*n].mem_type = TTM_PL_VRAM; 350 + pl[(*n)++].flags = flags; 351 + } 352 + if (domain & NOUVEAU_GEM_DOMAIN_GART) { 353 + pl[*n].mem_type = TTM_PL_TT; 354 + pl[(*n)++].flags = flags; 355 + } 356 + if (domain & NOUVEAU_GEM_DOMAIN_CPU) { 357 + pl[*n].mem_type = TTM_PL_SYSTEM; 358 + pl[(*n)++].flags = flags; 359 + } 354 360 } 355 361 356 362 static void ··· 888 882 struct ttm_place placement_memtype = { 889 883 .fpfn = 0, 890 884 .lpfn = 0, 891 - .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 885 + .mem_type = TTM_PL_TT, 886 + .flags = TTM_PL_MASK_CACHING 892 887 }; 893 888 struct ttm_placement placement; 894 889 struct ttm_resource tmp_reg; ··· 926 919 struct ttm_place placement_memtype = { 927 920 .fpfn = 0, 928 921 .lpfn = 0, 929 - .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 922 + .mem_type = TTM_PL_TT, 923 + .flags = TTM_PL_MASK_CACHING 930 924 }; 931 925 struct ttm_placement placement; 932 926 struct ttm_resource tmp_reg;
+17 -9
drivers/gpu/drm/qxl/qxl_object.c
··· 64 64 65 65 qbo->placement.placement = qbo->placements; 66 66 qbo->placement.busy_placement = qbo->placements; 67 - if (domain == QXL_GEM_DOMAIN_VRAM) 68 - qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_VRAM | pflag; 69 - if (domain == QXL_GEM_DOMAIN_SURFACE) { 70 - qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_PRIV | pflag; 71 - qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_VRAM | pflag; 67 + if (domain == QXL_GEM_DOMAIN_VRAM) { 68 + qbo->placements[c].mem_type = TTM_PL_VRAM; 69 + qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag; 72 70 } 73 - if (domain == QXL_GEM_DOMAIN_CPU) 74 - qbo->placements[c++].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM | pflag; 75 - if (!c) 76 - qbo->placements[c++].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 71 + if (domain == QXL_GEM_DOMAIN_SURFACE) { 72 + qbo->placements[c].mem_type = TTM_PL_PRIV; 73 + qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag; 74 + qbo->placements[c].mem_type = TTM_PL_VRAM; 75 + qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag; 76 + } 77 + if (domain == QXL_GEM_DOMAIN_CPU) { 78 + qbo->placements[c].mem_type = TTM_PL_SYSTEM; 79 + qbo->placements[c++].flags = TTM_PL_MASK_CACHING | pflag; 80 + } 81 + if (!c) { 82 + qbo->placements[c].mem_type = TTM_PL_SYSTEM; 83 + qbo->placements[c++].flags = TTM_PL_MASK_CACHING; 84 + } 77 85 qbo->placement.num_placement = c; 78 86 qbo->placement.num_busy_placement = c; 79 87 for (i = 0; i < c; ++i) {
+2 -1
drivers/gpu/drm/qxl/qxl_ttm.c
··· 55 55 static const struct ttm_place placements = { 56 56 .fpfn = 0, 57 57 .lpfn = 0, 58 - .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 58 + .mem_type = TTM_PL_SYSTEM, 59 + .flags = TTM_PL_MASK_CACHING 59 60 }; 60 61 61 62 if (!qxl_ttm_bo_is_qxl_bo(bo)) {
+21 -21
drivers/gpu/drm/radeon/radeon_object.c
··· 112 112 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { 113 113 rbo->placements[c].fpfn = 114 114 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 115 + rbo->placements[c].mem_type = TTM_PL_VRAM; 115 116 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 116 - TTM_PL_FLAG_UNCACHED | 117 - TTM_PL_FLAG_VRAM; 117 + TTM_PL_FLAG_UNCACHED; 118 118 } 119 119 120 120 rbo->placements[c].fpfn = 0; 121 + rbo->placements[c].mem_type = TTM_PL_VRAM; 121 122 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 122 - TTM_PL_FLAG_UNCACHED | 123 - TTM_PL_FLAG_VRAM; 123 + TTM_PL_FLAG_UNCACHED; 124 124 } 125 125 126 126 if (domain & RADEON_GEM_DOMAIN_GTT) { 127 127 if (rbo->flags & RADEON_GEM_GTT_UC) { 128 128 rbo->placements[c].fpfn = 0; 129 - rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 130 - TTM_PL_FLAG_TT; 129 + rbo->placements[c].mem_type = TTM_PL_TT; 130 + rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED; 131 131 132 132 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 133 133 (rbo->rdev->flags & RADEON_IS_AGP)) { 134 134 rbo->placements[c].fpfn = 0; 135 + rbo->placements[c].mem_type = TTM_PL_TT; 135 136 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 136 - TTM_PL_FLAG_UNCACHED | 137 - TTM_PL_FLAG_TT; 137 + TTM_PL_FLAG_UNCACHED; 138 138 } else { 139 139 rbo->placements[c].fpfn = 0; 140 - rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 141 - TTM_PL_FLAG_TT; 140 + rbo->placements[c].mem_type = TTM_PL_TT; 141 + rbo->placements[c++].flags = TTM_PL_FLAG_CACHED; 142 142 } 143 143 } 144 144 145 145 if (domain & RADEON_GEM_DOMAIN_CPU) { 146 146 if (rbo->flags & RADEON_GEM_GTT_UC) { 147 147 rbo->placements[c].fpfn = 0; 148 - rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 149 - TTM_PL_FLAG_SYSTEM; 148 + rbo->placements[c].mem_type = TTM_PL_SYSTEM; 149 + rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED; 150 150 151 151 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 152 152 rbo->rdev->flags & RADEON_IS_AGP) { 153 153 rbo->placements[c].fpfn = 0; 154 + rbo->placements[c].mem_type = TTM_PL_SYSTEM; 154 155 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 155 - TTM_PL_FLAG_UNCACHED | 156 - TTM_PL_FLAG_SYSTEM; 156 + TTM_PL_FLAG_UNCACHED; 157 157 } else { 158 158 rbo->placements[c].fpfn = 0; 159 - rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 160 - TTM_PL_FLAG_SYSTEM; 159 + rbo->placements[c].mem_type = TTM_PL_SYSTEM; 160 + rbo->placements[c++].flags = TTM_PL_FLAG_CACHED; 161 161 } 162 162 } 163 163 if (!c) { 164 164 rbo->placements[c].fpfn = 0; 165 - rbo->placements[c++].flags = TTM_PL_MASK_CACHING | 166 - TTM_PL_FLAG_SYSTEM; 165 + rbo->placements[c].mem_type = TTM_PL_SYSTEM; 166 + rbo->placements[c++].flags = TTM_PL_MASK_CACHING; 167 167 } 168 168 169 169 rbo->placement.num_placement = c; ··· 171 171 172 172 for (i = 0; i < c; ++i) { 173 173 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && 174 - (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && 174 + (rbo->placements[i].mem_type == TTM_PL_VRAM) && 175 175 !rbo->placements[i].fpfn) 176 176 rbo->placements[i].lpfn = 177 177 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; ··· 360 360 radeon_ttm_placement_from_domain(bo, domain); 361 361 for (i = 0; i < bo->placement.num_placement; i++) { 362 362 /* force to pin into visible video ram */ 363 - if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 363 + if ((bo->placements[i].mem_type == TTM_PL_VRAM) && 364 364 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && 365 365 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) 366 366 bo->placements[i].lpfn = ··· 824 824 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 825 825 for (i = 0; i < rbo->placement.num_placement; i++) { 826 826 /* Force into visible VRAM */ 827 - if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && 827 + if ((rbo->placements[i].mem_type == TTM_PL_VRAM) && 828 828 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) 829 829 rbo->placements[i].lpfn = lpfn; 830 830 }
+7 -4
drivers/gpu/drm/radeon/radeon_ttm.c
··· 88 88 static const struct ttm_place placements = { 89 89 .fpfn = 0, 90 90 .lpfn = 0, 91 - .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 91 + .mem_type = TTM_PL_SYSTEM, 92 + .flags = TTM_PL_MASK_CACHING 92 93 }; 93 94 94 95 struct radeon_bo *rbo; ··· 120 119 RADEON_GEM_DOMAIN_GTT); 121 120 rbo->placement.num_busy_placement = 0; 122 121 for (i = 0; i < rbo->placement.num_placement; i++) { 123 - if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { 122 + if (rbo->placements[i].mem_type == TTM_PL_VRAM) { 124 123 if (rbo->placements[i].fpfn < fpfn) 125 124 rbo->placements[i].fpfn = fpfn; 126 125 } else { ··· 225 224 placement.busy_placement = &placements; 226 225 placements.fpfn = 0; 227 226 placements.lpfn = 0; 228 - placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 227 + placements.mem_type = TTM_PL_TT; 228 + placements.flags = TTM_PL_MASK_CACHING; 229 229 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); 230 230 if (unlikely(r)) { 231 231 return r; ··· 271 269 placement.busy_placement = &placements; 272 270 placements.fpfn = 0; 273 271 placements.lpfn = 0; 274 - placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 272 + placements.mem_type = TTM_PL_TT; 273 + placements.flags = TTM_PL_MASK_CACHING; 275 274 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); 276 275 if (unlikely(r)) { 277 276 return r;
+14 -72
drivers/gpu/drm/ttm/ttm_bo.c
··· 64 64 kfree(bo); 65 65 } 66 66 67 - static inline int ttm_mem_type_from_place(const struct ttm_place *place, 68 - uint32_t *mem_type) 69 - { 70 - int pos; 71 - 72 - pos = ffs(place->flags & TTM_PL_MASK_MEM); 73 - if (unlikely(!pos)) 74 - return -EINVAL; 75 - 76 - *mem_type = pos - 1; 77 - return 0; 78 - } 79 - 80 67 static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo, 81 68 struct ttm_placement *placement) 82 69 { 83 70 struct drm_printer p = drm_debug_printer(TTM_PFX); 84 - int i, ret, mem_type; 85 71 struct ttm_resource_manager *man; 72 + int i, mem_type; 86 73 87 74 drm_printf(&p, "No space for %p (%lu pages, %luK, %luM)\n", 88 75 bo, bo->mem.num_pages, bo->mem.size >> 10, 89 76 bo->mem.size >> 20); 90 77 for (i = 0; i < placement->num_placement; i++) { 91 - ret = ttm_mem_type_from_place(&placement->placement[i], 92 - &mem_type); 93 - if (ret) 94 - return; 78 + mem_type = placement->placement[i].mem_type; 95 79 drm_printf(&p, " placement[%d]=0x%08X (%d)\n", 96 80 i, placement->placement[i].flags, mem_type); 97 81 man = ttm_manager_type(bo->bdev, mem_type); ··· 108 124 .sysfs_ops = &ttm_bo_global_ops, 109 125 .default_attrs = ttm_bo_global_attrs 110 126 }; 111 - 112 - 113 - static inline uint32_t ttm_bo_type_flags(unsigned type) 114 - { 115 - return 1 << (type); 116 - } 117 127 118 128 static void ttm_bo_add_mem_to_lru(struct ttm_buffer_object *bo, 119 129 struct ttm_resource *mem) ··· 888 910 return result; 889 911 } 890 912 891 - static bool ttm_bo_mt_compatible(struct ttm_resource_manager *man, 892 - uint32_t mem_type, 893 - const struct ttm_place *place, 894 - uint32_t *masked_placement) 895 - { 896 - uint32_t cur_flags = ttm_bo_type_flags(mem_type); 897 - 898 - if ((cur_flags & place->flags & TTM_PL_MASK_MEM) == 0) 899 - return false; 900 - 901 - if ((place->flags & man->available_caching) == 0) 902 - return false; 903 - 904 - cur_flags |= (place->flags & man->available_caching); 905 - 906 - *masked_placement = cur_flags; 907 - return true; 908 - } 909 - 910 913 /** 911 914 * ttm_bo_mem_placement - check if placement is compatible 912 915 * @bo: BO to find memory for ··· 905 946 struct ttm_operation_ctx *ctx) 906 947 { 907 948 struct ttm_bo_device *bdev = bo->bdev; 908 - uint32_t mem_type = TTM_PL_SYSTEM; 909 949 struct ttm_resource_manager *man; 910 950 uint32_t cur_flags = 0; 911 - int ret; 912 951 913 - ret = ttm_mem_type_from_place(place, &mem_type); 914 - if (ret) 915 - return ret; 916 - 917 - man = ttm_manager_type(bdev, mem_type); 952 + man = ttm_manager_type(bdev, place->mem_type); 918 953 if (!man || !ttm_resource_manager_used(man)) 919 954 return -EBUSY; 920 955 921 - if (!ttm_bo_mt_compatible(man, mem_type, place, &cur_flags)) 956 + if ((place->flags & man->available_caching) == 0) 922 957 return -EBUSY; 923 958 959 + cur_flags = place->flags & man->available_caching; 924 960 cur_flags = ttm_bo_select_caching(man, bo->mem.placement, cur_flags); 925 - /* 926 - * Use the access and other non-mapping-related flag bits from 927 - * the memory placement flags to the current flags 928 - */ 929 - ttm_flag_masked(&cur_flags, place->flags, ~TTM_PL_MASK_MEMTYPE); 961 + cur_flags |= place->flags & ~TTM_PL_MASK_CACHING; 930 962 931 - mem->mem_type = mem_type; 963 + mem->mem_type = place->mem_type; 932 964 mem->placement = cur_flags; 933 965 934 966 spin_lock(&ttm_bo_glob.lru_lock); ··· 956 1006 struct ttm_resource_manager *man; 957 1007 958 1008 ret = ttm_bo_mem_placement(bo, place, mem, ctx); 959 - if (ret == -EBUSY) 960 - continue; 961 1009 if (ret) 962 - goto error; 1010 + continue; 963 1011 964 1012 type_found = true; 965 1013 ret = ttm_resource_alloc(bo, place, mem); ··· 982 1034 const struct ttm_place *place = &placement->busy_placement[i]; 983 1035 984 1036 ret = ttm_bo_mem_placement(bo, place, mem, ctx); 985 - if (ret == -EBUSY) 986 - continue; 987 1037 if (ret) 988 - goto error; 1038 + continue; 989 1039 990 1040 type_found = true; 991 1041 ret = ttm_bo_mem_force_space(bo, place, mem, ctx); ··· 1054 1108 1055 1109 *new_flags = heap->flags; 1056 1110 if ((*new_flags & mem->placement & TTM_PL_MASK_CACHING) && 1057 - (*new_flags & mem->placement & TTM_PL_MASK_MEM) && 1111 + (mem->mem_type == heap->mem_type) && 1058 1112 (!(*new_flags & TTM_PL_FLAG_CONTIGUOUS) || 1059 1113 (mem->placement & TTM_PL_FLAG_CONTIGUOUS))) 1060 1114 return true; ··· 1109 1163 if (ret) 1110 1164 return ret; 1111 1165 } else { 1112 - /* 1113 - * Use the access and other non-mapping-related flag bits from 1114 - * the compatible memory placement flags to the active flags 1115 - */ 1116 - ttm_flag_masked(&bo->mem.placement, new_flags, 1117 - ~TTM_PL_MASK_MEMTYPE); 1166 + bo->mem.placement &= TTM_PL_MASK_CACHING; 1167 + bo->mem.placement |= new_flags & ~TTM_PL_MASK_CACHING; 1118 1168 } 1119 1169 /* 1120 1170 * We might need to add a TTM. ··· 1178 1236 bo->mem.bus.offset = 0; 1179 1237 bo->mem.bus.addr = NULL; 1180 1238 bo->moving = NULL; 1181 - bo->mem.placement = (TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED); 1239 + bo->mem.placement = TTM_PL_FLAG_CACHED; 1182 1240 bo->acc_size = acc_size; 1183 1241 bo->sg = sg; 1184 1242 if (resv) { ··· 1569 1627 1570 1628 evict_mem = bo->mem; 1571 1629 evict_mem.mm_node = NULL; 1572 - evict_mem.placement = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED; 1630 + evict_mem.placement = TTM_PL_FLAG_CACHED; 1573 1631 evict_mem.mem_type = TTM_PL_SYSTEM; 1574 1632 1575 1633 ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, &ctx);
-2
drivers/gpu/drm/ttm/ttm_bo_util.c
··· 69 69 70 70 ttm_tt_unbind(bo->bdev, ttm); 71 71 ttm_bo_free_old_node(bo); 72 - ttm_flag_masked(&old_mem->placement, TTM_PL_FLAG_SYSTEM, 73 - TTM_PL_MASK_MEM); 74 72 old_mem->mem_type = TTM_PL_SYSTEM; 75 73 } 76 74
+1
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
··· 354 354 355 355 pl.fpfn = 0; 356 356 pl.lpfn = 0; 357 + pl.mem_type = bo->mem.mem_type; 357 358 pl.flags = bo->mem.placement; 358 359 if (pin) 359 360 pl.flags |= TTM_PL_FLAG_NO_EVICT;
-2
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
··· 82 82 VMWGFX_NUM_GB_SCREEN_TARGET) 83 83 84 84 #define VMW_PL_GMR (TTM_PL_PRIV + 0) 85 - #define VMW_PL_FLAG_GMR (TTM_PL_FLAG_PRIV << 0) 86 85 #define VMW_PL_MOB (TTM_PL_PRIV + 1) 87 - #define VMW_PL_FLAG_MOB (TTM_PL_FLAG_PRIV << 1) 88 86 89 87 #define VMW_RES_CONTEXT ttm_driver_type0 90 88 #define VMW_RES_SURFACE ttm_driver_type1
+42 -21
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
··· 33 33 static const struct ttm_place vram_placement_flags = { 34 34 .fpfn = 0, 35 35 .lpfn = 0, 36 - .flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED 36 + .mem_type = TTM_PL_VRAM, 37 + .flags = TTM_PL_FLAG_CACHED 37 38 }; 38 39 39 40 static const struct ttm_place vram_ne_placement_flags = { 40 41 .fpfn = 0, 41 42 .lpfn = 0, 42 - .flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT 43 + .mem_type = TTM_PL_VRAM, 44 + .flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT 43 45 }; 44 46 45 47 static const struct ttm_place sys_placement_flags = { 46 48 .fpfn = 0, 47 49 .lpfn = 0, 48 - .flags = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED 50 + .mem_type = TTM_PL_SYSTEM, 51 + .flags = TTM_PL_FLAG_CACHED 49 52 }; 50 53 51 54 static const struct ttm_place sys_ne_placement_flags = { 52 55 .fpfn = 0, 53 56 .lpfn = 0, 54 - .flags = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT 57 + .mem_type = TTM_PL_SYSTEM, 58 + .flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT 55 59 }; 56 60 57 61 static const struct ttm_place gmr_placement_flags = { 58 62 .fpfn = 0, 59 63 .lpfn = 0, 60 - .flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED 64 + .mem_type = VMW_PL_GMR, 65 + .flags = TTM_PL_FLAG_CACHED 61 66 }; 62 67 63 68 static const struct ttm_place gmr_ne_placement_flags = { 64 69 .fpfn = 0, 65 70 .lpfn = 0, 66 - .flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT 71 + .mem_type = VMW_PL_GMR, 72 + .flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT 67 73 }; 68 74 69 75 static const struct ttm_place mob_placement_flags = { 70 76 .fpfn = 0, 71 77 .lpfn = 0, 72 - .flags = VMW_PL_FLAG_MOB | TTM_PL_FLAG_CACHED 78 + .mem_type = VMW_PL_MOB, 79 + .flags = TTM_PL_FLAG_CACHED 73 80 }; 74 81 75 82 static const struct ttm_place mob_ne_placement_flags = { 76 83 .fpfn = 0, 77 84 .lpfn = 0, 78 - .flags = VMW_PL_FLAG_MOB | TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT 85 + .mem_type = VMW_PL_MOB, 86 + .flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_NO_EVICT 79 87 }; 80 88 81 89 struct ttm_placement vmw_vram_placement = { ··· 97 89 { 98 90 .fpfn = 0, 99 91 .lpfn = 0, 100 - .flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED 92 + .mem_type = TTM_PL_VRAM, 93 + .flags = TTM_PL_FLAG_CACHED 101 94 }, { 102 95 .fpfn = 0, 103 96 .lpfn = 0, 104 - .flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED 97 + .mem_type = VMW_PL_GMR, 98 + .flags = TTM_PL_FLAG_CACHED 105 99 } 106 100 }; 107 101 ··· 111 101 { 112 102 .fpfn = 0, 113 103 .lpfn = 0, 114 - .flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED 104 + .mem_type = VMW_PL_GMR, 105 + .flags = TTM_PL_FLAG_CACHED 115 106 }, { 116 107 .fpfn = 0, 117 108 .lpfn = 0, 118 - .flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED 109 + .mem_type = TTM_PL_VRAM, 110 + .flags = TTM_PL_FLAG_CACHED 119 111 } 120 112 }; 121 113 ··· 132 120 { 133 121 .fpfn = 0, 134 122 .lpfn = 0, 135 - .flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED | 123 + .mem_type = TTM_PL_VRAM, 124 + .flags = TTM_PL_FLAG_CACHED | 136 125 TTM_PL_FLAG_NO_EVICT 137 126 }, { 138 127 .fpfn = 0, 139 128 .lpfn = 0, 140 - .flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED | 129 + .mem_type = VMW_PL_GMR, 130 + .flags = TTM_PL_FLAG_CACHED | 141 131 TTM_PL_FLAG_NO_EVICT 142 132 } 143 133 }; ··· 183 169 { 184 170 .fpfn = 0, 185 171 .lpfn = 0, 186 - .flags = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED 172 + .mem_type = TTM_PL_SYSTEM, 173 + .flags = TTM_PL_FLAG_CACHED 187 174 }, { 188 175 .fpfn = 0, 189 176 .lpfn = 0, 190 - .flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED 177 + .mem_type = TTM_PL_VRAM, 178 + .flags = TTM_PL_FLAG_CACHED 191 179 }, { 192 180 .fpfn = 0, 193 181 .lpfn = 0, 194 - .flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED 182 + .mem_type = VMW_PL_GMR, 183 + .flags = TTM_PL_FLAG_CACHED 195 184 }, { 196 185 .fpfn = 0, 197 186 .lpfn = 0, 198 - .flags = VMW_PL_FLAG_MOB | TTM_PL_FLAG_CACHED 187 + .mem_type = VMW_PL_MOB, 188 + .flags = TTM_PL_FLAG_CACHED 199 189 } 200 190 }; 201 191 ··· 207 189 { 208 190 .fpfn = 0, 209 191 .lpfn = 0, 210 - .flags = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED 192 + .mem_type = TTM_PL_SYSTEM, 193 + .flags = TTM_PL_FLAG_CACHED 211 194 }, { 212 195 .fpfn = 0, 213 196 .lpfn = 0, 214 - .flags = VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED 197 + .mem_type = VMW_PL_GMR, 198 + .flags = TTM_PL_FLAG_CACHED 215 199 }, { 216 200 .fpfn = 0, 217 201 .lpfn = 0, 218 - .flags = VMW_PL_FLAG_MOB | TTM_PL_FLAG_CACHED 202 + .mem_type = VMW_PL_MOB, 203 + .flags = TTM_PL_FLAG_CACHED 219 204 } 220 205 }; 221 206
-17
include/drm/ttm/ttm_bo_driver.h
··· 393 393 struct ttm_lru_bulk_move_pos swap[TTM_MAX_BO_PRIORITY]; 394 394 }; 395 395 396 - /** 397 - * ttm_flag_masked 398 - * 399 - * @old: Pointer to the result and original value. 400 - * @new: New value of bits. 401 - * @mask: Mask of bits to change. 402 - * 403 - * Convenience function to change a number of bits identified by a mask. 404 - */ 405 - 406 - static inline uint32_t 407 - ttm_flag_masked(uint32_t *old, uint32_t new, uint32_t mask) 408 - { 409 - *old ^= (*old ^ new) & mask; 410 - return *old; 411 - } 412 - 413 396 /* 414 397 * ttm_bo.c 415 398 */
+1 -8
include/drm/ttm/ttm_placement.h
··· 42 42 #define TTM_PL_VRAM 2 43 43 #define TTM_PL_PRIV 3 44 44 45 - #define TTM_PL_FLAG_SYSTEM (1 << TTM_PL_SYSTEM) 46 - #define TTM_PL_FLAG_TT (1 << TTM_PL_TT) 47 - #define TTM_PL_FLAG_VRAM (1 << TTM_PL_VRAM) 48 - #define TTM_PL_FLAG_PRIV (1 << TTM_PL_PRIV) 49 - #define TTM_PL_MASK_MEM 0x0000FFFF 50 - 51 45 /* 52 46 * Other flags that affects data placement. 53 47 * TTM_PL_FLAG_CACHED indicates cache-coherent mappings ··· 65 71 TTM_PL_FLAG_UNCACHED | \ 66 72 TTM_PL_FLAG_WC) 67 73 68 - #define TTM_PL_MASK_MEMTYPE (TTM_PL_MASK_MEM | TTM_PL_MASK_CACHING) 69 - 70 74 /** 71 75 * struct ttm_place 72 76 * ··· 77 85 struct ttm_place { 78 86 unsigned fpfn; 79 87 unsigned lpfn; 88 + uint32_t mem_type; 80 89 uint32_t flags; 81 90 }; 82 91