tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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powerpc/4xx: update ml507 .dts file to release reference design

This patch updates the Xilinx ML507 device tree to match the released
ML507 powerpc reference design (ml507_ppc440_emb_ref). This patch is
needed to boot Linux on the ML507 powerpc reference design without
manually generating and tweaking a device tree from the project directory.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

Grant Likely 48b3fd14 aafbf16b

+113 -11
+113 -11
arch/powerpc/boot/dts/virtex440-ml507.dts
··· 7 7 * This file is licensed under the terms of the GNU General Public License 8 8 * version 2. This program is licensed "as is" without any warranty of any 9 9 * kind, whether express or implied. 10 + * 11 + * --- 12 + * 13 + * Device Tree Generator version: 1.1 14 + * 15 + * CAUTION: This file is automatically generated by libgen. 16 + * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6 17 + * 18 + * XPS project directory: ml507_ppc440_emb_ref 10 19 */ 11 20 12 21 /dts-v1/; ··· 31 22 reg = < 0 0x10000000 >; 32 23 } ; 33 24 chosen { 34 - bootargs = "console=ttyS0 ip=on root=/dev/ram"; 35 - linux,stdout-path = "/plb@0/serial@83e00000"; 25 + bootargs = "console=ttyS0 root=/dev/ram"; 26 + linux,stdout-path = &RS232_Uart_1; 36 27 } ; 37 28 cpus { 38 29 #address-cells = <1>; ··· 145 136 compatible = "xlnx,ll-dma-1.00.a"; 146 137 dcr-reg = < 0x80 0x11 >; 147 138 interrupt-parent = <&xps_intc_0>; 148 - interrupts = < 9 2 0xa 2 >; 139 + interrupts = < 10 2 11 2 >; 149 140 } ; 150 141 } ; 151 142 } ; 152 143 plb_v46_0: plb@0 { 153 144 #address-cells = <1>; 154 145 #size-cells = <1>; 155 - compatible = "xlnx,plb-v46-1.02.a", "simple-bus"; 146 + compatible = "xlnx,plb-v46-1.03.a", "simple-bus"; 156 147 ranges ; 157 148 DIP_Switches_8Bit: gpio@81460000 { 158 149 compatible = "xlnx,xps-gpio-1.00.a"; 159 150 interrupt-parent = <&xps_intc_0>; 160 - interrupts = < 6 2 >; 151 + interrupts = < 7 2 >; 161 152 reg = < 0x81460000 0x10000 >; 162 153 xlnx,all-inputs = <1>; 163 154 xlnx,all-inputs-2 = <0>; ··· 171 162 xlnx,is-dual = <0>; 172 163 xlnx,tri-default = <0xffffffff>; 173 164 xlnx,tri-default-2 = <0xffffffff>; 165 + } ; 166 + FLASH: flash@fc000000 { 167 + bank-width = <2>; 168 + compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; 169 + reg = < 0xfc000000 0x2000000 >; 170 + xlnx,family = "virtex5"; 171 + xlnx,include-datawidth-matching-0 = <0x1>; 172 + xlnx,include-datawidth-matching-1 = <0x0>; 173 + xlnx,include-datawidth-matching-2 = <0x0>; 174 + xlnx,include-datawidth-matching-3 = <0x0>; 175 + xlnx,include-negedge-ioregs = <0x0>; 176 + xlnx,include-plb-ipif = <0x1>; 177 + xlnx,include-wrbuf = <0x1>; 178 + xlnx,max-mem-width = <0x10>; 179 + xlnx,mch-native-dwidth = <0x20>; 180 + xlnx,mch-plb-clk-period-ps = <0x2710>; 181 + xlnx,mch-splb-awidth = <0x20>; 182 + xlnx,mch0-accessbuf-depth = <0x10>; 183 + xlnx,mch0-protocol = <0x0>; 184 + xlnx,mch0-rddatabuf-depth = <0x10>; 185 + xlnx,mch1-accessbuf-depth = <0x10>; 186 + xlnx,mch1-protocol = <0x0>; 187 + xlnx,mch1-rddatabuf-depth = <0x10>; 188 + xlnx,mch2-accessbuf-depth = <0x10>; 189 + xlnx,mch2-protocol = <0x0>; 190 + xlnx,mch2-rddatabuf-depth = <0x10>; 191 + xlnx,mch3-accessbuf-depth = <0x10>; 192 + xlnx,mch3-protocol = <0x0>; 193 + xlnx,mch3-rddatabuf-depth = <0x10>; 194 + xlnx,mem0-width = <0x10>; 195 + xlnx,mem1-width = <0x20>; 196 + xlnx,mem2-width = <0x20>; 197 + xlnx,mem3-width = <0x20>; 198 + xlnx,num-banks-mem = <0x1>; 199 + xlnx,num-channels = <0x2>; 200 + xlnx,priority-mode = <0x0>; 201 + xlnx,synch-mem-0 = <0x0>; 202 + xlnx,synch-mem-1 = <0x0>; 203 + xlnx,synch-mem-2 = <0x0>; 204 + xlnx,synch-mem-3 = <0x0>; 205 + xlnx,synch-pipedelay-0 = <0x2>; 206 + xlnx,synch-pipedelay-1 = <0x2>; 207 + xlnx,synch-pipedelay-2 = <0x2>; 208 + xlnx,synch-pipedelay-3 = <0x2>; 209 + xlnx,tavdv-ps-mem-0 = <0x1adb0>; 210 + xlnx,tavdv-ps-mem-1 = <0x3a98>; 211 + xlnx,tavdv-ps-mem-2 = <0x3a98>; 212 + xlnx,tavdv-ps-mem-3 = <0x3a98>; 213 + xlnx,tcedv-ps-mem-0 = <0x1adb0>; 214 + xlnx,tcedv-ps-mem-1 = <0x3a98>; 215 + xlnx,tcedv-ps-mem-2 = <0x3a98>; 216 + xlnx,tcedv-ps-mem-3 = <0x3a98>; 217 + xlnx,thzce-ps-mem-0 = <0x88b8>; 218 + xlnx,thzce-ps-mem-1 = <0x1b58>; 219 + xlnx,thzce-ps-mem-2 = <0x1b58>; 220 + xlnx,thzce-ps-mem-3 = <0x1b58>; 221 + xlnx,thzoe-ps-mem-0 = <0x1b58>; 222 + xlnx,thzoe-ps-mem-1 = <0x1b58>; 223 + xlnx,thzoe-ps-mem-2 = <0x1b58>; 224 + xlnx,thzoe-ps-mem-3 = <0x1b58>; 225 + xlnx,tlzwe-ps-mem-0 = <0x88b8>; 226 + xlnx,tlzwe-ps-mem-1 = <0x0>; 227 + xlnx,tlzwe-ps-mem-2 = <0x0>; 228 + xlnx,tlzwe-ps-mem-3 = <0x0>; 229 + xlnx,twc-ps-mem-0 = <0x2af8>; 230 + xlnx,twc-ps-mem-1 = <0x3a98>; 231 + xlnx,twc-ps-mem-2 = <0x3a98>; 232 + xlnx,twc-ps-mem-3 = <0x3a98>; 233 + xlnx,twp-ps-mem-0 = <0x11170>; 234 + xlnx,twp-ps-mem-1 = <0x2ee0>; 235 + xlnx,twp-ps-mem-2 = <0x2ee0>; 236 + xlnx,twp-ps-mem-3 = <0x2ee0>; 237 + xlnx,xcl0-linesize = <0x4>; 238 + xlnx,xcl0-writexfer = <0x1>; 239 + xlnx,xcl1-linesize = <0x4>; 240 + xlnx,xcl1-writexfer = <0x1>; 241 + xlnx,xcl2-linesize = <0x4>; 242 + xlnx,xcl2-writexfer = <0x1>; 243 + xlnx,xcl3-linesize = <0x4>; 244 + xlnx,xcl3-writexfer = <0x1>; 174 245 } ; 175 246 Hard_Ethernet_MAC: xps-ll-temac@81c00000 { 176 247 #address-cells = <1>; ··· 273 184 xlnx,txcsum = <1>; 274 185 xlnx,txfifo = <0x1000>; 275 186 } ; 187 + } ; 188 + IIC_EEPROM: i2c@81600000 { 189 + compatible = "xlnx,xps-iic-2.00.a"; 190 + interrupt-parent = <&xps_intc_0>; 191 + interrupts = < 6 2 >; 192 + reg = < 0x81600000 0x10000 >; 193 + xlnx,clk-freq = <0x5f5e100>; 194 + xlnx,family = "virtex5"; 195 + xlnx,gpo-width = <0x1>; 196 + xlnx,iic-freq = <0x186a0>; 197 + xlnx,scl-inertial-delay = <0x0>; 198 + xlnx,sda-inertial-delay = <0x0>; 199 + xlnx,ten-bit-adr = <0x0>; 276 200 } ; 277 201 LEDs_8Bit: gpio@81400000 { 278 202 compatible = "xlnx,xps-gpio-1.00.a"; ··· 322 220 Push_Buttons_5Bit: gpio@81440000 { 323 221 compatible = "xlnx,xps-gpio-1.00.a"; 324 222 interrupt-parent = <&xps_intc_0>; 325 - interrupts = < 7 2 >; 223 + interrupts = < 8 2 >; 326 224 reg = < 0x81440000 0x10000 >; 327 225 xlnx,all-inputs = <1>; 328 226 xlnx,all-inputs-2 = <0>; ··· 339 237 } ; 340 238 RS232_Uart_1: serial@83e00000 { 341 239 clock-frequency = <100000000>; 342 - compatible = "xlnx,xps-uart16550-2.00.a", "ns16550"; 343 - current-speed = <0x2580>; 240 + compatible = "xlnx,xps-uart16550-2.00.b", "ns16550"; 241 + current-speed = <9600>; 344 242 device_type = "serial"; 345 243 interrupt-parent = <&xps_intc_0>; 346 - interrupts = < 8 2 >; 244 + interrupts = < 9 2 >; 347 245 reg = < 0x83e00000 0x10000 >; 348 - reg-offset = <3>; 246 + reg-offset = <0x1003>; 349 247 reg-shift = <2>; 350 248 xlnx,family = "virtex5"; 351 249 xlnx,has-external-rclk = <0>; ··· 370 268 compatible = "xlnx,xps-intc-1.00.a"; 371 269 interrupt-controller ; 372 270 reg = < 0x81800000 0x10000 >; 373 - xlnx,num-intr-inputs = <0xb>; 271 + xlnx,num-intr-inputs = <0xc>; 374 272 } ; 375 273 xps_timebase_wdt_1: xps-timebase-wdt@83a00000 { 376 274 compatible = "xlnx,xps-timebase-wdt-1.00.b";