tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'omap-for-v5.17/fixes-for-merge-window-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes

Fixes for omaps

A series of fixes for omap variants for minor issues, and a fix for a timer
regression for some omap3 beagleboard versions.

The timer fix needs to patch both the dts and the timer code because
otherwise the timer quirk handling for old dtbs will prevent the dts fix
from working.

The other changes are for issues found by automated analysis, a macasp
typo fix, and two cosmetic fixes for clocks.

* tag 'omap-for-v5.17/fixes-for-merge-window-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: Don't use legacy clock defines for dra7 clkctrl
clk: ti: Move dra7 clock devices out of the legacy section
ARM: dts: Fix timer regression for beagleboard revision c
ARM: dts: am335x-wega: Fix typo in mcasp property rx-num-evt
ARM: OMAP2+: adjust the location of put_device() call in omapdss_init_of
ARM: OMAP2+: hwmod: Add of_node_put() before break

Link: https://lore.kernel.org/r/pull-1641801310-149268@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 486343d3 63a87285

+74 -54
+3
Documentation/devicetree/bindings/arm/omap/omap.txt
··· 119 119 - OMAP3 BeagleBoard : Low cost community board 120 120 compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3" 121 121 122 + - OMAP3 BeagleBoard A to B4 : Early BeagleBoard revisions A to B4 with a timer quirk 123 + compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3" 124 + 122 125 - OMAP3 Tobi with Overo : Commercial expansion board with daughter board 123 126 compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3" 124 127
+1
arch/arm/boot/dts/Makefile
··· 806 806 logicpd-som-lv-37xx-devkit.dtb \ 807 807 omap3430-sdp.dtb \ 808 808 omap3-beagle.dtb \ 809 + omap3-beagle-ab4.dtb \ 809 810 omap3-beagle-xm.dtb \ 810 811 omap3-beagle-xm-ab.dtb \ 811 812 omap3-cm-t3517.dtb \
+1 -1
arch/arm/boot/dts/am335x-wega.dtsi
··· 55 55 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ 56 56 >; 57 57 tx-num-evt = <16>; 58 - rt-num-evt = <16>; 58 + rx-num-evt = <16>; 59 59 status = "okay"; 60 60 }; 61 61
+10 -10
arch/arm/boot/dts/dra7.dtsi
··· 160 160 target-module@48210000 { 161 161 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 162 162 power-domains = <&prm_mpu>; 163 - clocks = <&mpu_clkctrl DRA7_MPU_CLKCTRL 0>; 163 + clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>; 164 164 clock-names = "fck"; 165 165 #address-cells = <1>; 166 166 #size-cells = <1>; ··· 875 875 <0x58000014 4>; 876 876 reg-names = "rev", "syss"; 877 877 ti,syss-mask = <1>; 878 - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>, 879 - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, 880 - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>, 881 - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>; 878 + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>, 879 + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, 880 + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>, 881 + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>; 882 882 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; 883 883 #address-cells = <1>; 884 884 #size-cells = <1>; ··· 912 912 SYSC_OMAP2_SOFTRESET | 913 913 SYSC_OMAP2_AUTOIDLE)>; 914 914 ti,syss-mask = <1>; 915 - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; 915 + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; 916 916 clock-names = "fck"; 917 917 #address-cells = <1>; 918 918 #size-cells = <1>; ··· 939 939 <SYSC_IDLE_SMART>, 940 940 <SYSC_IDLE_SMART_WKUP>; 941 941 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; 942 - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, 943 - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; 942 + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, 943 + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; 944 944 clock-names = "fck", "dss_clk"; 945 945 #address-cells = <1>; 946 946 #size-cells = <1>; ··· 979 979 compatible = "vivante,gc"; 980 980 reg = <0x0 0x700>; 981 981 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 982 - clocks = <&dss_clkctrl DRA7_BB2D_CLKCTRL 0>; 982 + clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; 983 983 clock-names = "core"; 984 984 }; 985 985 }; ··· 1333 1333 ti,no-reset-on-init; 1334 1334 ti,no-idle; 1335 1335 timer@0 { 1336 - assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; 1336 + assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; 1337 1337 assigned-clock-parents = <&sys_32k_ck>; 1338 1338 }; 1339 1339 };
+47
arch/arm/boot/dts/omap3-beagle-ab4.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /dts-v1/; 3 + 4 + #include "omap3-beagle.dts" 5 + 6 + / { 7 + model = "TI OMAP3 BeagleBoard A to B4"; 8 + compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; 9 + }; 10 + 11 + /* 12 + * Workaround for capacitor C70 issue, see "Boards revision A and < B5" 13 + * section at https://elinux.org/BeagleBoard_Community 14 + */ 15 + 16 + /* Unusable as clocksource because of unreliable oscillator */ 17 + &counter32k { 18 + status = "disabled"; 19 + }; 20 + 21 + /* Unusable as clockevent because of unreliable oscillator, allow to idle */ 22 + &timer1_target { 23 + /delete-property/ti,no-reset-on-init; 24 + /delete-property/ti,no-idle; 25 + timer@0 { 26 + /delete-property/ti,timer-alwon; 27 + }; 28 + }; 29 + 30 + /* Preferred always-on timer for clocksource */ 31 + &timer12_target { 32 + ti,no-reset-on-init; 33 + ti,no-idle; 34 + timer@0 { 35 + /* Always clocked by secure_32k_fck */ 36 + }; 37 + }; 38 + 39 + /* Preferred timer for clockevent */ 40 + &timer2_target { 41 + ti,no-reset-on-init; 42 + ti,no-idle; 43 + timer@0 { 44 + assigned-clocks = <&gpt2_fck>; 45 + assigned-clock-parents = <&sys_ck>; 46 + }; 47 + };
-33
arch/arm/boot/dts/omap3-beagle.dts
··· 304 304 phys = <0 &hsusb2_phy>; 305 305 }; 306 306 307 - /* Unusable as clocksource because of unreliable oscillator */ 308 - &counter32k { 309 - status = "disabled"; 310 - }; 311 - 312 - /* Unusable as clockevent because if unreliable oscillator, allow to idle */ 313 - &timer1_target { 314 - /delete-property/ti,no-reset-on-init; 315 - /delete-property/ti,no-idle; 316 - timer@0 { 317 - /delete-property/ti,timer-alwon; 318 - }; 319 - }; 320 - 321 - /* Preferred always-on timer for clocksource */ 322 - &timer12_target { 323 - ti,no-reset-on-init; 324 - ti,no-idle; 325 - timer@0 { 326 - /* Always clocked by secure_32k_fck */ 327 - }; 328 - }; 329 - 330 - /* Preferred timer for clockevent */ 331 - &timer2_target { 332 - ti,no-reset-on-init; 333 - ti,no-idle; 334 - timer@0 { 335 - assigned-clocks = <&gpt2_fck>; 336 - assigned-clock-parents = <&sys_ck>; 337 - }; 338 - }; 339 - 340 307 &twl_gpio { 341 308 ti,use-leds; 342 309 /* pullups: BIT(1) */
+1 -1
arch/arm/mach-omap2/display.c
··· 263 263 } 264 264 265 265 r = of_platform_populate(node, NULL, NULL, &pdev->dev); 266 + put_device(&pdev->dev); 266 267 if (r) { 267 268 pr_err("Unable to populate DSS submodule devices\n"); 268 - put_device(&pdev->dev); 269 269 return r; 270 270 } 271 271
+3 -1
arch/arm/mach-omap2/omap_hwmod.c
··· 752 752 753 753 for_each_matching_node(np, ti_clkctrl_match_table) { 754 754 ret = _setup_clkctrl_provider(np); 755 - if (ret) 755 + if (ret) { 756 + of_node_put(np); 756 757 break; 758 + } 757 759 } 758 760 759 761 return ret;
+1 -1
drivers/clocksource/timer-ti-dm-systimer.c
··· 241 241 bool quirk_unreliable_oscillator = false; 242 242 243 243 /* Quirk unreliable 32 KiHz oscillator with incomplete dts */ 244 - if (of_machine_is_compatible("ti,omap3-beagle") || 244 + if (of_machine_is_compatible("ti,omap3-beagle-ab4") || 245 245 of_machine_is_compatible("timll,omap3-devkit8000")) { 246 246 quirk_unreliable_oscillator = true; 247 247 counter_32k = -ENODEV;
+7 -7
include/dt-bindings/clock/dra7.h
··· 84 84 #define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 85 85 #define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 86 86 87 - /* iva clocks */ 88 - #define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 89 - #define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 90 - 91 87 /* dss clocks */ 92 88 #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 93 89 #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 94 - 95 - /* gpu clocks */ 96 - #define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 97 90 98 91 /* l3init clocks */ 99 92 #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) ··· 260 267 #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 261 268 #define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 262 269 270 + /* iva clocks */ 271 + #define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 272 + #define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) 273 + 263 274 /* dss clocks */ 264 275 #define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 265 276 #define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) 277 + 278 + /* gpu clocks */ 279 + #define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 266 280 267 281 /* l3init clocks */ 268 282 #define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)