Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

MIPS: Align swapper_pg_dir to 64K for better TLB Refill code.

We can save an instruction in the TLB Refill path for kernel mappings
by aligning swapper_pg_dir on a 64K boundary. The address of
swapper_pg_dir can be generated with a single LUI instead of
LUI/{D}ADDUI.

The alignment of __init_end is bumped up to 64K so there are no holes
between it and swapper_pg_dir, which is placed at the very beginning
of .bss.

The alignment of invalid_pmd_table and invalid_pte_table can be
relaxed to PAGE_SIZE. We do this by using __page_aligned_bss, which
has the added benefit of eliminating alignment holes in .bss.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-arch@vger.kernel.org,
Cc: linux-kernel@vger.kernel.org
Acked-by: Arnd Bergmann <arnd@arndb.de>
Patchwork: https://patchwork.linux-mips.org/patch/4220/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

David Daney and committed by
Ralf Baechle
485172b3 c87728ca

+28 -10
+19 -2
arch/mips/kernel/vmlinux.lds.S
··· 1 1 #include <asm/asm-offsets.h> 2 2 #include <asm/page.h> 3 3 #include <asm/thread_info.h> 4 + 5 + /* 6 + * Put .bss..swapper_pg_dir as the first thing in .bss. This will 7 + * ensure that it has .bss alignment (64K). 8 + */ 9 + #define BSS_FIRST_SECTIONS *(.bss..swapper_pg_dir) 10 + 4 11 #include <asm-generic/vmlinux.lds.h> 5 12 6 13 #undef mips ··· 126 119 } 127 120 128 121 PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT) 129 - . = ALIGN(PAGE_SIZE); 122 + /* 123 + * Align to 64K in attempt to eliminate holes before the 124 + * .bss..swapper_pg_dir section at the start of .bss. This 125 + * also satisfies PAGE_SIZE alignment as the largest page size 126 + * allowed is 64K. 127 + */ 128 + . = ALIGN(0x10000); 130 129 __init_end = .; 131 130 /* freed after init ends here */ 132 131 133 - BSS_SECTION(0, 0, 0) 132 + /* 133 + * Force .bss to 64K alignment so that .bss..swapper_pg_dir 134 + * gets that alignment. .sbss should be empty, so there will be 135 + * no holes after __init_end. */ 136 + BSS_SECTION(0, 0x10000, 0) 134 137 135 138 _end = . ; 136 139
+9 -8
arch/mips/mm/init.c
··· 469 469 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 470 470 unsigned long pgd_current[NR_CPUS]; 471 471 #endif 472 - /* 473 - * On 64-bit we've got three-level pagetables with a slightly 474 - * different layout ... 475 - */ 476 - #define __page_aligned(order) __attribute__((__aligned__(PAGE_SIZE<<order))) 477 472 478 473 /* 479 474 * gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER 480 475 * are constants. So we use the variants from asm-offset.h until that gcc 481 476 * will officially be retired. 477 + * 478 + * Align swapper_pg_dir in to 64K, allows its address to be loaded 479 + * with a single LUI instruction in the TLB handlers. If we used 480 + * __aligned(64K), its size would get rounded up to the alignment 481 + * size, and waste space. So we place it in its own section and align 482 + * it in the linker script. 482 483 */ 483 - pgd_t swapper_pg_dir[_PTRS_PER_PGD] __page_aligned(_PGD_ORDER); 484 + pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir); 484 485 #ifndef __PAGETABLE_PMD_FOLDED 485 - pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned(PMD_ORDER); 486 + pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss; 486 487 #endif 487 - pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned(PTE_ORDER); 488 + pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;