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drm/panel: asus-z00t-tm5p5-n35596: transition to mipi_dsi wrapped functions

Use functions introduced in commit 966e397e4f60 ("drm/mipi-dsi:
Introduce mipi_dsi_*_write_seq_multi()") and commit f79d6d28d8fe
("drm/mipi-dsi: wrap more functions for streamline handling") for the
asus-z00t-tm5p5-n35596 panel.

Signed-off-by: Tejas Vipin <tejasvipin76@gmail.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20240621131648.131667-1-tejasvipin76@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240621131648.131667-1-tejasvipin76@gmail.com

authored by

Tejas Vipin and committed by
Neil Armstrong 47e851ec 4b12f91a

+57 -79
+57 -79
drivers/gpu/drm/panel/panel-asus-z00t-tm5p5-n35596.c
··· 33 33 usleep_range(15000, 16000); 34 34 } 35 35 36 - static int tm5p5_nt35596_on(struct tm5p5_nt35596 *ctx) 36 + static void tm5p5_nt35596_on(struct mipi_dsi_multi_context *dsi_ctx) 37 37 { 38 - struct mipi_dsi_device *dsi = ctx->dsi; 38 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xff, 0x05); 39 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfb, 0x01); 40 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc5, 0x31); 41 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xff, 0x04); 42 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x01, 0x84); 43 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x05, 0x25); 44 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x06, 0x01); 45 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x07, 0x20); 46 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x08, 0x06); 47 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x09, 0x08); 48 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0a, 0x10); 49 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0b, 0x10); 50 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0c, 0x10); 51 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0d, 0x14); 52 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0e, 0x14); 53 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x0f, 0x14); 54 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x10, 0x14); 55 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x11, 0x14); 56 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x12, 0x14); 57 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x17, 0xf3); 58 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x18, 0xc0); 59 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x19, 0xc0); 60 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1a, 0xc0); 61 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1b, 0xb3); 62 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1c, 0xb3); 63 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1d, 0xb3); 64 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1e, 0xb3); 65 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x1f, 0xb3); 66 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x20, 0xb3); 67 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfb, 0x01); 68 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xff, 0x00); 69 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfb, 0x01); 70 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x35, 0x01); 71 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd3, 0x06); 72 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd4, 0x04); 73 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x5e, 0x0d); 74 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x11, 0x00); 39 75 40 - mipi_dsi_generic_write_seq(dsi, 0xff, 0x05); 41 - mipi_dsi_generic_write_seq(dsi, 0xfb, 0x01); 42 - mipi_dsi_generic_write_seq(dsi, 0xc5, 0x31); 43 - mipi_dsi_generic_write_seq(dsi, 0xff, 0x04); 44 - mipi_dsi_generic_write_seq(dsi, 0x01, 0x84); 45 - mipi_dsi_generic_write_seq(dsi, 0x05, 0x25); 46 - mipi_dsi_generic_write_seq(dsi, 0x06, 0x01); 47 - mipi_dsi_generic_write_seq(dsi, 0x07, 0x20); 48 - mipi_dsi_generic_write_seq(dsi, 0x08, 0x06); 49 - mipi_dsi_generic_write_seq(dsi, 0x09, 0x08); 50 - mipi_dsi_generic_write_seq(dsi, 0x0a, 0x10); 51 - mipi_dsi_generic_write_seq(dsi, 0x0b, 0x10); 52 - mipi_dsi_generic_write_seq(dsi, 0x0c, 0x10); 53 - mipi_dsi_generic_write_seq(dsi, 0x0d, 0x14); 54 - mipi_dsi_generic_write_seq(dsi, 0x0e, 0x14); 55 - mipi_dsi_generic_write_seq(dsi, 0x0f, 0x14); 56 - mipi_dsi_generic_write_seq(dsi, 0x10, 0x14); 57 - mipi_dsi_generic_write_seq(dsi, 0x11, 0x14); 58 - mipi_dsi_generic_write_seq(dsi, 0x12, 0x14); 59 - mipi_dsi_generic_write_seq(dsi, 0x17, 0xf3); 60 - mipi_dsi_generic_write_seq(dsi, 0x18, 0xc0); 61 - mipi_dsi_generic_write_seq(dsi, 0x19, 0xc0); 62 - mipi_dsi_generic_write_seq(dsi, 0x1a, 0xc0); 63 - mipi_dsi_generic_write_seq(dsi, 0x1b, 0xb3); 64 - mipi_dsi_generic_write_seq(dsi, 0x1c, 0xb3); 65 - mipi_dsi_generic_write_seq(dsi, 0x1d, 0xb3); 66 - mipi_dsi_generic_write_seq(dsi, 0x1e, 0xb3); 67 - mipi_dsi_generic_write_seq(dsi, 0x1f, 0xb3); 68 - mipi_dsi_generic_write_seq(dsi, 0x20, 0xb3); 69 - mipi_dsi_generic_write_seq(dsi, 0xfb, 0x01); 70 - mipi_dsi_generic_write_seq(dsi, 0xff, 0x00); 71 - mipi_dsi_generic_write_seq(dsi, 0xfb, 0x01); 72 - mipi_dsi_generic_write_seq(dsi, 0x35, 0x01); 73 - mipi_dsi_generic_write_seq(dsi, 0xd3, 0x06); 74 - mipi_dsi_generic_write_seq(dsi, 0xd4, 0x04); 75 - mipi_dsi_generic_write_seq(dsi, 0x5e, 0x0d); 76 - mipi_dsi_generic_write_seq(dsi, 0x11, 0x00); 77 - msleep(100); 78 - mipi_dsi_generic_write_seq(dsi, 0x29, 0x00); 79 - mipi_dsi_generic_write_seq(dsi, 0x53, 0x24); 76 + mipi_dsi_msleep(dsi_ctx, 100); 80 77 81 - return 0; 78 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x29, 0x00); 79 + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x53, 0x24); 82 80 } 83 81 84 - static int tm5p5_nt35596_off(struct tm5p5_nt35596 *ctx) 82 + static void tm5p5_nt35596_off(struct mipi_dsi_multi_context *dsi_ctx) 85 83 { 86 - struct mipi_dsi_device *dsi = ctx->dsi; 87 - struct device *dev = &dsi->dev; 88 - int ret; 84 + mipi_dsi_dcs_set_display_off_multi(dsi_ctx); 89 85 90 - ret = mipi_dsi_dcs_set_display_off(dsi); 91 - if (ret < 0) { 92 - dev_err(dev, "Failed to set display off: %d\n", ret); 93 - return ret; 94 - } 95 - msleep(60); 86 + mipi_dsi_msleep(dsi_ctx, 60); 96 87 97 - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 98 - if (ret < 0) { 99 - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); 100 - return ret; 101 - } 88 + mipi_dsi_dcs_enter_sleep_mode_multi(dsi_ctx); 102 89 103 - mipi_dsi_dcs_write_seq(dsi, 0x4f, 0x01); 104 - 105 - return 0; 90 + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x4f, 0x01); 106 91 } 107 92 108 93 static int tm5p5_nt35596_prepare(struct drm_panel *panel) 109 94 { 110 95 struct tm5p5_nt35596 *ctx = to_tm5p5_nt35596(panel); 111 - struct device *dev = &ctx->dsi->dev; 112 - int ret; 96 + struct mipi_dsi_multi_context dsi_ctx = {.dsi = ctx->dsi}; 113 97 114 - ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 115 - if (ret < 0) { 116 - dev_err(dev, "Failed to enable regulators: %d\n", ret); 117 - return ret; 118 - } 98 + dsi_ctx.accum_err = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 99 + if (dsi_ctx.accum_err) 100 + return dsi_ctx.accum_err; 119 101 120 102 tm5p5_nt35596_reset(ctx); 121 103 122 - ret = tm5p5_nt35596_on(ctx); 123 - if (ret < 0) { 124 - dev_err(dev, "Failed to initialize panel: %d\n", ret); 104 + tm5p5_nt35596_on(&dsi_ctx); 105 + 106 + if (dsi_ctx.accum_err) { 125 107 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 126 108 regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), 127 109 ctx->supplies); 128 - return ret; 129 110 } 130 111 131 - return 0; 112 + return dsi_ctx.accum_err; 132 113 } 133 114 134 115 static int tm5p5_nt35596_unprepare(struct drm_panel *panel) 135 116 { 136 117 struct tm5p5_nt35596 *ctx = to_tm5p5_nt35596(panel); 137 - struct device *dev = &ctx->dsi->dev; 138 - int ret; 118 + struct mipi_dsi_multi_context dsi_ctx = {.dsi = ctx->dsi}; 139 119 140 - ret = tm5p5_nt35596_off(ctx); 141 - if (ret < 0) 142 - dev_err(dev, "Failed to un-initialize panel: %d\n", ret); 120 + tm5p5_nt35596_off(&dsi_ctx); 143 121 144 122 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 145 123 regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), 146 124 ctx->supplies); 147 125 148 - return 0; 126 + return dsi_ctx.accum_err; 149 127 } 150 128 151 129 static const struct drm_display_mode tm5p5_nt35596_mode = {