tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/nv40/disp: implement support for hotplug irq
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+52
+3
drivers/gpu/drm/nouveau/nouveau_state.c
+3
drivers/gpu/drm/nouveau/nouveau_state.c
···
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engine->display.destroy = nv04_display_destroy;
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engine->display.init = nv04_display_init;
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engine->display.fini = nv04_display_fini;
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engine->gpio.init = nv10_gpio_init;
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engine->gpio.fini = nv10_gpio_fini;
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engine->gpio.drive = nv10_gpio_drive;
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engine->gpio.sense = nv10_gpio_sense;
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engine->gpio.irq_enable = nv10_gpio_irq_enable;
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engine->pm.clocks_get = nv40_pm_clocks_get;
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engine->pm.clocks_pre = nv40_pm_clocks_pre;
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engine->pm.clocks_set = nv40_pm_clocks_set;
+8
drivers/gpu/drm/nouveau/nv04_display.c
+8
drivers/gpu/drm/nouveau/nv04_display.c
···
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#include "nouveau_hw.h"
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#include "nouveau_encoder.h"
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#include "nouveau_connector.h"
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+
#include "nouveau_gpio.h"
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static void nv04_vblank_crtc0_isr(struct drm_device *);
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static void nv04_vblank_crtc1_isr(struct drm_device *);
···
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int
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nv04_display_init(struct drm_device *dev)
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{
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struct drm_connector *connector;
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struct drm_encoder *encoder;
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struct drm_crtc *crtc;
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···
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
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crtc->funcs->restore(crtc);
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/* enable hotplug interrupts */
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list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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struct nouveau_connector *conn = nouveau_connector(connector);
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nouveau_gpio_irq(dev, 0, conn->hpd, 0xff, true);
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}
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return 0;
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}
+41
drivers/gpu/drm/nouveau/nv10_gpio.c
+41
drivers/gpu/drm/nouveau/nv10_gpio.c
···
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_hw.h"
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#include "nouveau_gpio.h"
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int
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nv10_gpio_sense(struct drm_device *dev, int line)
···
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mask = NVReadCRTC(dev, 0, reg) & ~(mask << line);
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NVWriteCRTC(dev, 0, reg, mask | (data << line));
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return 0;
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}
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void
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nv10_gpio_irq_enable(struct drm_device *dev, int line, bool on)
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{
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u32 mask = 0x00010001 << line;
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nv_wr32(dev, 0x001104, mask);
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nv_mask(dev, 0x001144, mask, on ? mask : 0);
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}
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+
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static void
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nv10_gpio_isr(struct drm_device *dev)
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{
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u32 intr = nv_rd32(dev, 0x1104);
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u32 hi = (intr & 0x0000ffff) >> 0;
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u32 lo = (intr & 0xffff0000) >> 16;
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nouveau_gpio_isr(dev, 0, hi | lo);
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nv_wr32(dev, 0x001104, intr);
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}
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int
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nv10_gpio_init(struct drm_device *dev)
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{
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nv_wr32(dev, 0x001140, 0x00000000);
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nv_wr32(dev, 0x001100, 0xffffffff);
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nv_wr32(dev, 0x001144, 0x00000000);
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nv_wr32(dev, 0x001104, 0xffffffff);
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nouveau_irq_register(dev, 28, nv10_gpio_isr); /* PBUS */
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return 0;
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}
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void
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nv10_gpio_fini(struct drm_device *dev)
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{
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nv_wr32(dev, 0x001140, 0x00000000);
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nv_wr32(dev, 0x001144, 0x00000000);
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nouveau_irq_unregister(dev, 28);
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}