Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/nv40/disp: implement support for hotplug irq

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

+52
+3
drivers/gpu/drm/nouveau/nouveau_state.c
··· 273 273 engine->display.destroy = nv04_display_destroy; 274 274 engine->display.init = nv04_display_init; 275 275 engine->display.fini = nv04_display_fini; 276 + engine->gpio.init = nv10_gpio_init; 277 + engine->gpio.fini = nv10_gpio_fini; 276 278 engine->gpio.drive = nv10_gpio_drive; 277 279 engine->gpio.sense = nv10_gpio_sense; 280 + engine->gpio.irq_enable = nv10_gpio_irq_enable; 278 281 engine->pm.clocks_get = nv40_pm_clocks_get; 279 282 engine->pm.clocks_pre = nv40_pm_clocks_pre; 280 283 engine->pm.clocks_set = nv40_pm_clocks_set;
+8
drivers/gpu/drm/nouveau/nv04_display.c
··· 31 31 #include "nouveau_hw.h" 32 32 #include "nouveau_encoder.h" 33 33 #include "nouveau_connector.h" 34 + #include "nouveau_gpio.h" 34 35 35 36 static void nv04_vblank_crtc0_isr(struct drm_device *); 36 37 static void nv04_vblank_crtc1_isr(struct drm_device *); ··· 221 220 int 222 221 nv04_display_init(struct drm_device *dev) 223 222 { 223 + struct drm_connector *connector; 224 224 struct drm_encoder *encoder; 225 225 struct drm_crtc *crtc; 226 226 ··· 241 239 242 240 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 243 241 crtc->funcs->restore(crtc); 242 + 243 + /* enable hotplug interrupts */ 244 + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 245 + struct nouveau_connector *conn = nouveau_connector(connector); 246 + nouveau_gpio_irq(dev, 0, conn->hpd, 0xff, true); 247 + } 244 248 245 249 return 0; 246 250 }
+41
drivers/gpu/drm/nouveau/nv10_gpio.c
··· 27 27 #include "drmP.h" 28 28 #include "nouveau_drv.h" 29 29 #include "nouveau_hw.h" 30 + #include "nouveau_gpio.h" 30 31 31 32 int 32 33 nv10_gpio_sense(struct drm_device *dev, int line) ··· 80 79 mask = NVReadCRTC(dev, 0, reg) & ~(mask << line); 81 80 NVWriteCRTC(dev, 0, reg, mask | (data << line)); 82 81 return 0; 82 + } 83 + 84 + void 85 + nv10_gpio_irq_enable(struct drm_device *dev, int line, bool on) 86 + { 87 + u32 mask = 0x00010001 << line; 88 + 89 + nv_wr32(dev, 0x001104, mask); 90 + nv_mask(dev, 0x001144, mask, on ? mask : 0); 91 + } 92 + 93 + static void 94 + nv10_gpio_isr(struct drm_device *dev) 95 + { 96 + u32 intr = nv_rd32(dev, 0x1104); 97 + u32 hi = (intr & 0x0000ffff) >> 0; 98 + u32 lo = (intr & 0xffff0000) >> 16; 99 + 100 + nouveau_gpio_isr(dev, 0, hi | lo); 101 + 102 + nv_wr32(dev, 0x001104, intr); 103 + } 104 + 105 + int 106 + nv10_gpio_init(struct drm_device *dev) 107 + { 108 + nv_wr32(dev, 0x001140, 0x00000000); 109 + nv_wr32(dev, 0x001100, 0xffffffff); 110 + nv_wr32(dev, 0x001144, 0x00000000); 111 + nv_wr32(dev, 0x001104, 0xffffffff); 112 + nouveau_irq_register(dev, 28, nv10_gpio_isr); /* PBUS */ 113 + return 0; 114 + } 115 + 116 + void 117 + nv10_gpio_fini(struct drm_device *dev) 118 + { 119 + nv_wr32(dev, 0x001140, 0x00000000); 120 + nv_wr32(dev, 0x001144, 0x00000000); 121 + nouveau_irq_unregister(dev, 28); 83 122 }