net: phy: mediatek: Add token ring clear bit operation support

Similar to __mtk_tr_set_bits() support. Previously in mtk-ge-soc.c,
we clear some register bits via token ring, which were also implemented
in three __phy_write(). Now we can do the same thing via
__mtk_tr_clr_bits() helper.

Signed-off-by: Sky Huang <[e-mail]>
Reviewed-by: Andrew Lunn <[e-mail]>
Link: https://patch.msgid.link/[e-mail]
Signed-off-by: Jakub Kicinski <[e-mail]>

drivers/net/phy/mediatek/mtk-ge-soc.c

···
 /* FfeUpdGainForce */
 #define FFE_UPDATE_GAIN_FORCE			BIT(6)
 
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
+/* TrFreeze */
+#define TR_FREEZE_MASK				GENMASK(11, 0)
+
 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
 /* SS: Steady-state, KP: Proportional Gain */
 /* SSTrKp100 */
···
 #define SS_TR_KP1000_SLAVE_MASK			GENMASK(9, 7)
 /* SSTrKf1000Slv */
 #define SS_TR_KF1000_SLAVE_MASK			GENMASK(6, 4)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
+/* clear this bit if wanna select from AFE */
+/* Regsigdet_sel_1000 */
+#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE	BIT(4)
 
 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
 /* RegEEE_st2TrKf1000 */
···
 /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
 /* RegEEE100Stg1_tar */
 #define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK	GENMASK(8, 0)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
+/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
+#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN	BIT(11)
 
 #define ANALOG_INTERNAL_OPERATION_MAX_US	20
 #define TXRESERVE_MIN				0
···
 			FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
 				   FFE_UPDATE_GAIN_FORCE);
 
-	/* TrFreeze = 0 (mt7988 default) */
-	__phy_write(phydev, 0x11, 0x0);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x9686);
+	__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK);
 
 	__mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
 			SS_TR_KP100_MASK | SS_TR_KF100_MASK |
···
 			 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
 
 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-	/* Regsigdet_sel_1000 = 0 */
-	__phy_write(phydev, 0x11, 0xb);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x9690);
+	__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8,
+			  EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE);
 
 	__mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
 			EEE1000_STAGE2_TR_KF_MASK,
···
 			FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
 				   0x10));
 
-	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
-	__phy_write(phydev, 0x11, 0x1463);
-	__phy_write(phydev, 0x12, 0x0);
-	__phy_write(phydev, 0x10, 0x96ca);
+	__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25,
+			  WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN);
 
 	__mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
 			DFE_TAIL_EANBLE_VGA_TRHESH_1000,

drivers/net/phy/mediatek/mtk-phy-lib.c

···
 }
 EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
 
+void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+		       u8 data_addr, u32 clr)
+{
+	__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0);
+}
+EXPORT_SYMBOL_GPL(__mtk_tr_clr_bits);
+
 int mtk_phy_read_page(struct phy_device *phydev)
 {
 	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);

drivers/net/phy/mediatek/mtk.h

···
 		   u8 data_addr, u32 mask, u32 set);
 void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 		       u8 data_addr, u32 set);
+void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+		       u8 data_addr, u32 clr);
 
 int mtk_phy_read_page(struct phy_device *phydev);
 int mtk_phy_write_page(struct phy_device *phydev, int page);