tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: Introduce i915_error_regs
Introduce i915_error_regs as the EIR/EMR counterpart
to the IIR/IMR/IER i915_irq_regs, and update the irq
reset/postingstall to utilize them accordingly.
v2: Include xe compat versions
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250217070047.953-7-ville.syrjala@linux.intel.com
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+65
-2
+27
-2
drivers/gpu/drm/i915/i915_irq.c
+27
-2
drivers/gpu/drm/i915/i915_irq.c
···
120
120
intel_uncore_posting_read(uncore, regs.imr);
121
121
}
122
122
123
+
void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs)
124
+
{
125
+
intel_uncore_write(uncore, regs.emr, 0xffffffff);
126
+
intel_uncore_posting_read(uncore, regs.emr);
127
+
128
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
129
+
intel_uncore_posting_read(uncore, regs.eir);
130
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
131
+
intel_uncore_posting_read(uncore, regs.eir);
132
+
}
133
+
134
+
void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
135
+
u32 emr_val)
136
+
{
137
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
138
+
intel_uncore_posting_read(uncore, regs.eir);
139
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
140
+
intel_uncore_posting_read(uncore, regs.eir);
141
+
142
+
intel_uncore_write(uncore, regs.emr, emr_val);
143
+
intel_uncore_posting_read(uncore, regs.emr);
144
+
}
145
+
123
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/**
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* ivb_parity_work - Workqueue called when a parity error interrupt
125
148
* occurred.
···
890
867
891
868
i9xx_display_irq_reset(dev_priv);
892
869
870
+
gen2_error_reset(uncore, GEN2_ERROR_REGS);
893
871
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
894
872
dev_priv->irq_mask = ~0u;
895
873
}
···
900
876
struct intel_uncore *uncore = &dev_priv->uncore;
901
877
u32 enable_mask;
902
878
903
-
intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv));
879
+
gen2_error_init(uncore, GEN2_ERROR_REGS, i9xx_error_mask(dev_priv));
904
880
905
881
dev_priv->irq_mask =
906
882
~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
···
996
972
997
973
i9xx_display_irq_reset(dev_priv);
998
974
975
+
gen2_error_reset(uncore, GEN2_ERROR_REGS);
999
976
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
1000
977
dev_priv->irq_mask = ~0u;
1001
978
}
···
1025
1000
struct intel_uncore *uncore = &dev_priv->uncore;
1026
1001
u32 enable_mask;
1027
1002
1028
-
intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv));
1003
+
gen2_error_init(uncore, GEN2_ERROR_REGS, i965_error_mask(dev_priv));
1029
1004
1030
1005
dev_priv->irq_mask =
1031
1006
~(I915_ASLE_INTERRUPT |
+4
drivers/gpu/drm/i915/i915_irq.h
+4
drivers/gpu/drm/i915/i915_irq.h
···
47
47
void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
48
48
u32 imr_val, u32 ier_val);
49
49
50
+
void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs);
51
+
void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
52
+
u32 emr_val);
53
+
50
54
#endif /* __I915_IRQ_H__ */
+3
drivers/gpu/drm/i915/i915_reg.h
+3
drivers/gpu/drm/i915/i915_reg.h
···
472
472
#define GM45_ERROR_CP_PRIV (1 << 3)
473
473
#define I915_ERROR_MEMORY_REFRESH (1 << 1)
474
474
#define I915_ERROR_INSTRUCTION (1 << 0)
475
+
476
+
#define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
477
+
475
478
#define INSTPM _MMIO(0x20c0)
476
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#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
477
480
#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+8
drivers/gpu/drm/i915/i915_reg_defs.h
+8
drivers/gpu/drm/i915/i915_reg_defs.h
···
294
294
#define I915_IRQ_REGS(_imr, _ier, _iir) \
295
295
((const struct i915_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) })
296
296
297
+
struct i915_error_regs {
298
+
i915_reg_t emr;
299
+
i915_reg_t eir;
300
+
};
301
+
302
+
#define I915_ERROR_REGS(_emr, _eir) \
303
+
((const struct i915_error_regs){ .emr = (_emr), .eir = (_eir) })
304
+
297
305
#endif /* __I915_REG_DEFS__ */
+23
drivers/gpu/drm/xe/display/ext/i915_irq.c
+23
drivers/gpu/drm/xe/display/ext/i915_irq.c
···
51
51
intel_uncore_posting_read(uncore, regs.imr);
52
52
}
53
53
54
+
void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs)
55
+
{
56
+
intel_uncore_write(uncore, regs.emr, 0xffffffff);
57
+
intel_uncore_posting_read(uncore, regs.emr);
58
+
59
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
60
+
intel_uncore_posting_read(uncore, regs.eir);
61
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
62
+
intel_uncore_posting_read(uncore, regs.eir);
63
+
}
64
+
65
+
void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
66
+
u32 emr_val)
67
+
{
68
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
69
+
intel_uncore_posting_read(uncore, regs.eir);
70
+
intel_uncore_write(uncore, regs.eir, 0xffffffff);
71
+
intel_uncore_posting_read(uncore, regs.eir);
72
+
73
+
intel_uncore_write(uncore, regs.emr, emr_val);
74
+
intel_uncore_posting_read(uncore, regs.emr);
75
+
}
76
+
54
77
bool intel_irqs_enabled(struct xe_device *xe)
55
78
{
56
79
return atomic_read(&xe->irq.enabled);