Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

spi: sun4i: allow transfers to set transmission speed

Allow transfers to set the transmission speed rather than using the
device max_speed_hz value. The SPI core makes sure that the speed_hz
value is always set on the transfer.

Signed-off-by: Marcus Weseloh <mweseloh42@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Marcus Weseloh and committed by
Mark Brown
47284e3e 8005c49d

+8 -8
+4 -4
drivers/spi/spi-sun4i.c
··· 229 229 230 230 /* Ensure that we have a parent clock fast enough */ 231 231 mclk_rate = clk_get_rate(sspi->mclk); 232 - if (mclk_rate < (2 * spi->max_speed_hz)) { 233 - clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz); 232 + if (mclk_rate < (2 * tfr->speed_hz)) { 233 + clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); 234 234 mclk_rate = clk_get_rate(sspi->mclk); 235 235 } 236 236 ··· 248 248 * First try CDR2, and if we can't reach the expected 249 249 * frequency, fall back to CDR1. 250 250 */ 251 - div = mclk_rate / (2 * spi->max_speed_hz); 251 + div = mclk_rate / (2 * tfr->speed_hz); 252 252 if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { 253 253 if (div > 0) 254 254 div--; 255 255 256 256 reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; 257 257 } else { 258 - div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz); 258 + div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); 259 259 reg = SUN4I_CLK_CTL_CDR1(div); 260 260 } 261 261
+4 -4
drivers/spi/spi-sun6i.c
··· 217 217 218 218 /* Ensure that we have a parent clock fast enough */ 219 219 mclk_rate = clk_get_rate(sspi->mclk); 220 - if (mclk_rate < (2 * spi->max_speed_hz)) { 221 - clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz); 220 + if (mclk_rate < (2 * tfr->speed_hz)) { 221 + clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); 222 222 mclk_rate = clk_get_rate(sspi->mclk); 223 223 } 224 224 ··· 236 236 * First try CDR2, and if we can't reach the expected 237 237 * frequency, fall back to CDR1. 238 238 */ 239 - div = mclk_rate / (2 * spi->max_speed_hz); 239 + div = mclk_rate / (2 * tfr->speed_hz); 240 240 if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { 241 241 if (div > 0) 242 242 div--; 243 243 244 244 reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS; 245 245 } else { 246 - div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz); 246 + div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); 247 247 reg = SUN6I_CLK_CTL_CDR1(div); 248 248 } 249 249