drm/i915: metadata for shared dplls

An id to match the idx (useful for register access macros) and a name
fore neater debug output.

Reviewed-by: Ville Syrjälä <[e-mail]>
Signed-off-by: Daniel Vetter <[e-mail]>

drivers/gpu/drm/i915/i915_drv.h

···
 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 		if ((intel_encoder)->base.crtc == (__crtc))
 
-struct intel_shared_dpll {
-	int refcount; /* count of number of CRTCs sharing this PLL */
-	int active; /* count of number of active CRTCs (i.e. DPMS on) */
-	bool on; /* is the PLL actually active? Disabled during modeset */
-	int pll_reg;
-	int fp0_reg;
-	int fp1_reg;
-};
-
 enum intel_dpll_id {
 	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
 	/* real shared dpll ids must be >= 0 */
···
 	DPLL_ID_PCH_PLL_B,
 };
 #define I915_NUM_PLLS 2
+
+struct intel_shared_dpll {
+	int refcount; /* count of number of CRTCs sharing this PLL */
+	int active; /* count of number of active CRTCs (i.e. DPMS on) */
+	bool on; /* is the PLL actually active? Disabled during modeset */
+	const char *name;
+	/* should match the index in the dev_priv->shared_dplls array */
+	enum intel_dpll_id id;
+	int pll_reg;
+	int fp0_reg;
+	int fp1_reg;
+};
 
 /* Used by dp and fdi links */
 struct intel_link_m_n {

drivers/gpu/drm/i915/intel_display.c

···
 	}
 
 	if (WARN (!pll,
-		  "asserting PCH PLL %s with no PLL\n", state_string(state)))
+		  "asserting DPLL %s with no DPLL\n", state_string(state)))
 		return;
 
 	val = I915_READ(pll->pll_reg);
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	WARN(cur_state != state,
-	     "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
-	     pll->pll_reg, state_string(state), state_string(cur_state), val);
+	     "%s assertion failure (expected %s, current %s), val=%08x\n",
+	     pll->name, state_string(state), state_string(cur_state), val);
 
 	/* Make sure the selected PLL is correctly attached to the transcoder */
 	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
···
 	if (WARN_ON(pll->refcount == 0))
 		return;
 
-	DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
-		      pll->pll_reg, pll->active, pll->on,
+	DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
+		      pll->name, pll->active, pll->on,
 		      crtc->base.base.id);
 
 	/* PCH refclock must be enabled first */
···
 	}
 	WARN_ON(pll->on);
 
-	DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
+	DRM_DEBUG_KMS("enabling %s\n", pll->name);
 
 	reg = pll->pll_reg;
 	val = I915_READ(reg);
···
 	if (WARN_ON(pll->refcount == 0))
 		return;
 
-	DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
-		      pll->pll_reg, pll->active, pll->on,
+	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
+		      pll->name, pll->active, pll->on,
 		      crtc->base.base.id);
 
 	if (WARN_ON(pll->active == 0)) {
···
 	if (--pll->active)
 		return;
 
-	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
+	DRM_DEBUG_KMS("disabling %s\n", pll->name);
 
 	/* Make sure transcoder isn't still depending on us */
 	assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
···
 		return;
 
 	if (pll->refcount == 0) {
-		WARN(1, "bad PCH PLL refcount\n");
+		WARN(1, "bad %s refcount\n", pll->name);
 		return;
 	}
 
···
 	enum intel_dpll_id i;
 
 	if (pll) {
-		DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
-			      crtc->base.base.id, pll->pll_reg);
+		DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
+			      crtc->base.base.id, pll->name);
 		intel_put_shared_dpll(crtc);
 	}
 
···
 		i = crtc->pipe;
 		pll = &dev_priv->shared_dplls[i];
 
-		DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
-			      crtc->base.base.id, pll->pll_reg);
+		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
+			      crtc->base.base.id, pll->name);
 
 		goto found;
 	}
···
 
 		if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
 		    fp == I915_READ(pll->fp0_reg)) {
-			DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
+			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
 				      crtc->base.base.id,
-				      pll->pll_reg, pll->refcount, pll->active);
+				      pll->name, pll->refcount, pll->active);
 
 			goto found;
 		}
···
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		pll = &dev_priv->shared_dplls[i];
 		if (pll->refcount == 0) {
-			DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
-				      crtc->base.base.id, pll->pll_reg);
+			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
+				      crtc->base.base.id, pll->name);
 			goto found;
 		}
 	}
···
 
 found:
 	crtc->config.shared_dpll = i;
-	DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe));
+	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
+			 pipe_name(crtc->pipe));
 	if (pll->active == 0) {
-		DRM_DEBUG_DRIVER("setting up pll %d\n", i);
+		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
 		WARN_ON(pll->on);
 		assert_shared_dpll_disabled(dev_priv, pll, NULL);
 
···
 		intel_ddi_pll_init(dev);
 }
 
+static char *ibx_pch_dpll_names[] = {
+	"PCH DPLL A",
+	"PCH DPLL B",
+};
+
 static void ibx_pch_dpll_init(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
···
 	dev_priv->num_shared_dpll = 2;
 
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+		dev_priv->shared_dplls[i].id = i;
+		dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
 		dev_priv->shared_dplls[i].pll_reg = _PCH_DPLL(i);
 		dev_priv->shared_dplls[i].fp0_reg = _PCH_FP0(i);
 		dev_priv->shared_dplls[i].fp1_reg = _PCH_FP1(i);