tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
media: hantro: add support for STM32MP25 VDEC
Add support for STM32MP25 VDEC video hardware decoder.
Support of H264/VP8 decoding.
No post-processor support.
VDEC has its own reset/clock/irq.
Successfully tested up to full HD.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hugues Fruchet <hugues.fruchet@foss.st.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
authored by
Hugues Fruchet
and committed by
Mauro Carvalho Chehab
46c4dffb
60314831
+114
-3
+11
-3
drivers/media/platform/verisilicon/Kconfig
+11
-3
drivers/media/platform/verisilicon/Kconfig
···
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config VIDEO_HANTRO
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tristate "Hantro VPU driver"
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depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || COMPILE_TEST
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depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || ARCH_STM32 || COMPILE_TEST
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depends on V4L_MEM2MEM_DRIVERS
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depends on VIDEO_DEV
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select MEDIA_CONTROLLER
···
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select V4L2_VP9
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help
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Support for the Hantro IP based Video Processing Units present on
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Rockchip and NXP i.MX8M SoCs, which accelerate video and image
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encoding and decoding.
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Rockchip, NXP i.MX8M and STM32MP25 SoCs, which accelerate video
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and image encoding and decoding.
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To compile this driver as a module, choose M here: the module
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will be called hantro-vpu.
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···
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default y
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help
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Enable support for H6 SoC.
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config VIDEO_HANTRO_STM32MP25
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bool "Hantro STM32MP25 support"
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depends on VIDEO_HANTRO
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depends on ARCH_STM32 || COMPILE_TEST
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default y
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help
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Enable support for STM32MP25 SoCs.
+3
drivers/media/platform/verisilicon/Makefile
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drivers/media/platform/verisilicon/Makefile
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drivers/media/platform/verisilicon/hantro_drv.c
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drivers/media/platform/verisilicon/hantro_drv.c
···
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#ifdef CONFIG_VIDEO_HANTRO_SUNXI
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{ .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, },
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#endif
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#ifdef CONFIG_VIDEO_HANTRO_STM32MP25
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{ .compatible = "st,stm32mp25-vdec", .data = &stm32mp25_vdec_variant, },
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#endif
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_hantro_match);
+1
drivers/media/platform/verisilicon/hantro_hw.h
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drivers/media/platform/verisilicon/hantro_hw.h
···
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extern const struct hantro_variant rk3588_vpu981_variant;
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extern const struct hantro_variant sama5d4_vdec_variant;
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extern const struct hantro_variant sunxi_vpu_variant;
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extern const struct hantro_variant stm32mp25_vdec_variant;
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extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
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extern const struct hantro_postproc_ops hantro_g2_postproc_ops;
+96
drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c
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drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* STM32MP25 video codec driver
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*
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* Copyright (C) STMicroelectronics SA 2024
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* Authors: Hugues Fruchet <hugues.fruchet@foss.st.com>
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* for STMicroelectronics.
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*
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*/
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#include "hantro.h"
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/*
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* Supported formats.
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*/
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static const struct hantro_fmt stm32mp25_vdec_fmts[] = {
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{
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.fourcc = V4L2_PIX_FMT_NV12,
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.codec_mode = HANTRO_MODE_NONE,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_FHD_WIDTH,
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.step_width = MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_FHD_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_VP8_FRAME,
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.codec_mode = HANTRO_MODE_VP8_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_FHD_WIDTH,
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.step_width = MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_FHD_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_H264_SLICE,
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.codec_mode = HANTRO_MODE_H264_DEC,
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.max_depth = 2,
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.frmsize = {
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.min_width = FMT_MIN_WIDTH,
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.max_width = FMT_FHD_WIDTH,
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.step_width = MB_DIM,
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.min_height = FMT_MIN_HEIGHT,
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.max_height = FMT_FHD_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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};
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/*
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* Supported codec ops.
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*/
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static const struct hantro_codec_ops stm32mp25_vdec_codec_ops[] = {
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[HANTRO_MODE_VP8_DEC] = {
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.run = hantro_g1_vp8_dec_run,
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.reset = hantro_g1_reset,
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.init = hantro_vp8_dec_init,
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.exit = hantro_vp8_dec_exit,
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},
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[HANTRO_MODE_H264_DEC] = {
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.run = hantro_g1_h264_dec_run,
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.reset = hantro_g1_reset,
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.init = hantro_h264_dec_init,
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.exit = hantro_h264_dec_exit,
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},
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};
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/*
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* Variants.
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*/
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static const struct hantro_irq stm32mp25_vdec_irqs[] = {
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{ "vdec", hantro_g1_irq },
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};
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static const char * const stm32mp25_vdec_clk_names[] = { "vdec-clk" };
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const struct hantro_variant stm32mp25_vdec_variant = {
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.dec_fmts = stm32mp25_vdec_fmts,
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.num_dec_fmts = ARRAY_SIZE(stm32mp25_vdec_fmts),
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.codec = HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
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.codec_ops = stm32mp25_vdec_codec_ops,
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.irqs = stm32mp25_vdec_irqs,
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.num_irqs = ARRAY_SIZE(stm32mp25_vdec_irqs),
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.clk_names = stm32mp25_vdec_clk_names,
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.num_clocks = ARRAY_SIZE(stm32mp25_vdec_clk_names),
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};